JPH0831269B2 - Data selection circuit - Google Patents

Description

Detailed Description of the Invention a. FIELD OF THE INVENTION The present invention relates to a data selection circuit.

B. Prior Art For example, in the field of computer graphics, multi-port video memory is used, especially dynamic RA
A 256K video RAM consisting of a combination of M (Random Access Memory) and a data register is used. In such a video memory, it is very difficult to externally control a display having a size of 1024 × 1024 dots or more (for example, 1024 × 1280 dots).
In particular, there has been no effective means to output 256-bit data at 1024 bits, which is four times that of 256-bit data.

C. It is an object of the present invention to provide a data selection circuit that can effectively process and output a plurality of parallel data.

D. According to the present invention, there are provided 2 ⁿ data registers, 2 ⁿ output terminals for receiving data output from the data registers, each of the 2 ⁿ data registers and the 2 ⁿ data registers. ⁿ
Each of which is connected to one of the output terminals,
2 ⁿ for selectively electrically connecting the output terminal to one of its own in the 2 ⁿ pieces of data registers are connected
And number of selector means, an address buffer means for holding the n-bit selection data defining the connection relation between the 2 ⁿ pieces of data registers and said 2 ⁿ pieces of output terminals, selection of the n bit and a decoder means for supplying a decoded output that controls an electrical connection one-to-one between the in accordance with the data and the 2 ⁿ data registers and the 2 ⁿ pieces of output terminals, each of said selector means Includes 2 ⁿ transfer gates respectively provided between each of the 2 ⁿ data registers and the output terminal to which the data register is connected, and each of the selectors corresponding to the decoded output. One of the 2 ⁿ transfer gates in the means is turned on to cause the 2 ⁿ data registers and the
2 and ⁿ output terminals are electrically connected in one-to-one, the data of each of the 2 ⁿ pieces of data registers of said 2 ⁿ output terminals by sequentially switching the value of the selection data is sequentially a first output mode to be continuously output, data of the 2 ⁿ pieces of data register is output in parallel to the 2 ⁿ pieces of output terminals by fixing the value of the selected data to a constant value The present invention relates to a data selection circuit characterized in that the second output mode is selected.

E. Examples Hereinafter, examples of the present invention will be described in detail.

FIG. 1 shows a 256K having a data selector according to the present invention.
1 schematically shows a main part of a video RAM.

That is, the data selectors surrounded by broken lines in the figure are the addresses A8 and A9 added to the serial address buffers A0 to A7 by the upper 2 bits, and the decoder and selector that operate by decoding these additional addresses. It consists of a section. The decoder and selector are provided with output buffers (0), (1), (2) and (3) of the data registers (0), (1), (2) and (3) and an output driver SO0. , SO1, SO2, SO3.

The decoder and selector are configured as shown in FIG. 2, for example, and the signal ASH8 from the address buffers A8 and A9 is supplied to the decoder section, while the selector section outputs the control signal L10, for example. There is. The second
Decoders and selectors similar to those in the figure have control signals L20 and L3.
Although it is provided for 0 and L40, it is omitted because it is basically the same as FIG.

These control signals are output to the output buffers (0), (1), (2) and (3) and the output driver SO as shown in FIG.
It is selectively added to the gates of the transfer gates ,,, which are connected between 0, SO1, SO2 and SO3. For example, control signals L10, L20, and L3 are applied to each gate.
When 0 and L40 are sequentially switched and added, from the output driver SO0, data register (0) → data register (1) →
Each data in the data register (2) → data register (3) is sequentially and serially output. That is, SO
At 0, 256 + 256 + 256 + 256 = 1024 data can be output. This also applies to the other SO1 to SO3. For example, from SO1, the data register (1) →
The data of (2) → (3) → (0) is output at 1024 × 1.

When the control signal is not switched as described above, 256 data are stored in each output driver (2
56 × 4 will be output in parallel).

 The specific operation will be described below.

(1) In the initial state, the additional buffers A8 and A9 are
Set “A9: A8” = “0 0”.

(2) Next, when all of A0 to A7 become "1", A8 is incremented.

(3), A8 and A9 are decoded and connected as follows.

As described above, by using the selection circuit according to the present invention, it is possible to individually fetch data in parallel from a plurality of (four in the above example) parallel data registers in a video memory or the like, and to serially fetch data. -It is possible to selectively switch between taking out by connecting a register (1024 x 1 in the above example). In other words, since the 256-bit serial register x4 and 1024 x1 can be switched, it is possible to easily cope with a large-sized display. In addition, the switching speed is high, and stable operation is possible even if the switching interval is long.

FIG. 4 shows that the above data selector is a video memory (RA
M) is used. In this memory, the address buffers A0 to A9 shown in FIG. 1 are used as column address buffers, the output is supplied to the decoder section of the data selector, and the output of the data register is passed through the I / O buffer. Is being supplied to the selector section.

5 and 6 show a reference example of the present invention.

In this example, a shift register circuit is used to serially connect a plurality of parallel data registers as described above and read the output.

Since the video memory operates at a very high speed, it is necessary to access from IN to OUT in 33nsce at a high speed and to hold OUT at 10μsec × 256 = 2.56msec for a long cycle. FIG. 6 shows a timing chart of the clock. When T0 = 33nsec, simply T1 = T2 = T3 = T4 = T5 =
Assuming X, X = 6.6 nsec. Therefore, OUT is 6.6nse
In order to output with c, in FIG. 5, the transistor size of'is made large, and the transistor size of'is made sufficiently larger than '. In this case, when the gate of'is "H" (high), a through current flows in ',', and if'is large, the capacitance of'is required to be sufficiently large. Similarly, when IN is “H”, ′,
A through current flows through the transistor of '. Also, OUT is
It is enough if you drive for 2.56 msec, but this shift
In the register circuit, OUT is held by capacitance.
Further, it is necessary to generate clocks for G1, C1, G2, and C2, and it is necessary to take the timing.

Compared to this reference example, in the embodiment described in FIGS. 1 to 4, the problem of the through current as described above and the instability factor due to the capacitance on the OUT side (change in charge due to coupling and leakage). ), The clock timing can be easily taken.

Although the present invention has been illustrated above, the above-described example can be further modified based on the technical idea of the present invention.

For example, in FIG. 1, the number of data registers may be various, but if the address buffer is added or reduced depending on the number of data registers to decode, a wide range of data can be handled. In this case, the number of data registers is 2 ⁿ
If the number is set to n, the number of additional address buffers may be set to n. Further, in the example of FIG. 1, the control is performed as shown in FIG. 3, but this control system may be variously changed. It should be noted that the present invention is considered to be effective for devices other than those described above, such as a facsimile.

F. As described above, the present invention extracts data in parallel from a plurality of parallel data registers, and serially connects these data in series (that is, the data registers are apparently connected serially). Since it can be selectively taken out by a selector, it is possible to easily deal with a large-sized display, for example, and it is possible to expand the range of use.

[Brief description of drawings]

1 to 4 show an embodiment of the present invention. FIG. 1 is a block diagram of a main part of a video memory, FIG. 2 is an equivalent circuit diagram of a decoder and a selector part, and FIG. FIG. 4 is a block diagram showing a parallel and serial data retrieval system, and FIG. 4 is a block diagram of a video memory. 5 and 6 show a reference example of the present invention. FIG. 5 is an equivalent circuit diagram of a shift register circuit, and FIG. 6 is a timing chart of clocks. In the drawing, reference numerals A0 to A9 ... Address buffers L10, L20, L30, L40 ... Control signals ..., Transfer gates or transistors.

Front Page Continuation (72) Inventor Takashi Inui 2355 Mihara-mura, Kihara, Inashiki-gun, Ibaraki Japan Textile Instruments Co., Ltd. (56) References JP-A-53-94835 (JP, A) JP-A-54-148439 (JP, A)

Claims (1)

[Claims] 1. 2 ⁿ data registers and 2 ⁿ receiving data output from said data registers
And pieces of output terminals, said being connected 1 early in life each of the respective 2 ⁿ pieces of data register the 2 ⁿ pieces of output terminals, one of its own among the 2 ⁿ pieces of data register defining the 2 ⁿ pieces of selector means for selectively electrically connecting the output terminals being connected, the connection relationship between the 2 ⁿ pieces of data registers and said 2 ⁿ pieces of output terminals address buffer means for holding n-bit selection data, and 2 ⁿ pieces of data corresponding to the n-bit selection data
A decoder means for providing a decode output for controlling a one-to-one electrical connection between the register and the 2 ⁿ output terminals, each selector means each of the 2 ⁿ data registers. and includes the 2 ⁿ transfer gates are provided between the output terminal itself is connected, among the 2 ⁿ pieces of transfer gates in each of the selector means in response to said decoded output said 2 ⁿ pieces of output terminals and the 2 ⁿ pieces of data register by one conductive are electrically connected in one-to-one, the 2 ⁿ by sequentially switching the value of the selected data
A first data output mode in which the data of the 2 ⁿ data registers are sequentially and successively output to each of the 2 output terminals, and the 2 ⁿ And a second data output mode in which the data of the 2 ⁿ data registers are output in parallel to the output terminals of the data selection circuit.