JP4303671B2 - Serial access memory device, display device, and semiconductor memory device - Google Patents

Description

  The present invention relates to a serial access memory having a plurality of output ports.

  In recent years, a serial access memory (two-port memory) having a plurality of output ports has been used for removing screen noise and correcting screen movement (time axis correction) such as digital television and digital VTR.

  In particular, in a current TV system (called an interlace method) in which one display screen is composed of a screen composed of odd lines and a screen composed of even lines, in order to remove noise generated on the screen. A filtering technique is used in which a line in which noise is generated is replaced with lines before and after the line.

  In general, these techniques are realized by a field delay and a line delay. A serial access memory that realizes this field delay is called a field memory, and a serial access memory that realizes this line delay is called a line memory.

  Such serial access memories are disclosed in, for example, Japanese Patent Application Publication No. 64-59694 published on March 7, 1989 and Japanese Patent Application Publication No. 2-187789 published on July 24, 1990 in Japan. It is described in.

JP-A 64-59694 Japanese Patent Laid-Open No. 2-187989

  Generally, when image data is processed as in the filtering technique described above, the processing is realized by using a plurality of serial access memories as disclosed in the above publication.

  Use of a plurality of serial access memories in this way increases the mounting area and the cost.

In order to solve the above-described problems, a serial access memory device according to a representative invention of the present application includes a first serial access memory unit, a second serial access memory unit, and the first and second serial access memories. is connected between the parts, it is provided with a delay circuit for providing the data so slow cast from the first serial access memory section to the second serial access memory portion.

  According to the present invention, since the delay circuit is arranged between the first serial access memory unit and the second serial access memory unit, it is equivalent to a function conventionally realized by a plurality of serial access memories. A serial access memory device having various functions can be easily made into one chip.

The present invention provides a read data bus provided in a first serial access memory unit, an output circuit connected to the read data bus, a write data bus provided in a second serial access memory unit, and the first serial access. A memory unit, comprising: a first word line; a first bit line pair disposed so as to intersect the first word line; the first word line and the first bit line pair; Output register connected to the read data bus and connected to the first bit line pair and connected to the read data bus. And a first switch circuit connected between the first bit line pair and the output register, and in response to a first control signal, between the first bit line pair and the output register. Conduction between The first switch circuit for transferring the first data to the output register, and a first transfer circuit connected between the output register and the read data bus, wherein the first column signal The first serial access memory unit comprising the first transfer circuit for transferring the first data to the read data bus in response to the first serial access memory unit, and the second serial access memory unit, A second word line, a second bit line pair arranged to intersect the second word line, and an intersection of the second word line and the second bit line pair; A second memory cell for storing two data, an input register connected between the second bit line pair and the write data bus, to which the first data is input, and the second bit Line pair and the input register A second switch circuit connected between the first bit line pair and the input register in response to a second control signal, wherein the first data is transferred to the second register circuit. A second transfer circuit connected to the second bit line pair; and a second transfer circuit connected between the input register and the write data bus, the second transfer circuit being connected together with the first column signal. The second serial access memory unit comprising: the second transfer circuit that transfers the first data on the write data bus to the input register in response to a column signal of 2; A Y decoder circuit that applies the first column signal to a transfer circuit and supplies the second column signal to the second transfer circuit; and a delay circuit connected to the read data bus and the write data bus, Lee A serial access memory having a function equivalent to a function conventionally realized by a plurality of serial access memories, by providing the delay circuit for delaying the first data on the shared data bus and applying the delayed data to the write data bus Realization of one-chip system.

  In the following, the preferred embodiments of the present invention will be described with reference to the drawings. In each embodiment, common parts are denoted by the same reference numerals. In each embodiment, a memory control signal generation circuit and the like that are not directly related to the basic operation of the present invention are omitted for easy understanding of the description.

  First, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the serial access memory according to the first embodiment of the present invention.

  The serial access memory of this embodiment has a memory cell array 101. The memory cell array 101 includes a plurality of word lines WLi (i = 1 to n) and a plurality of complementary bit line pairs BLk and bars BLk (k = 1 to m) crossing them. Memory cells Qki (k = 1 to m, i = 1 to n) composed of transistors and capacitors are respectively connected at intersections between the word line WLi and the bit line pair BLk and bar BLk. Is arranged. Each bit line pair BLk, bar BLk is connected to a sense amplifier SAk (k = 1 to m).

  An X address decoder 103 is connected to the memory cell array 101. The X address decoder 103 is connected to the word line and has a function of selecting an arbitrary column of the memory cell array 101 in accordance with an X address given from the outside.

  The input circuit 105 is a circuit that inputs write data input from the input terminal Din to the memory cell array 101 via the write data bus pair WDB and the bar WDB.

  The Y address decoder (for writing) 107 has a function of decoding an externally applied Y address and selecting an arbitrary row of the memory cell array 101 by an address signal YWi. Data on the write data bus pair WDB and bar WDB is input to the memory cells in the selected row.

  The transfer circuit 109 includes a plurality of transistor pairs 109k and bars 109k. These transistors are N-channel MOS transistors (NMOS). The transistor pair 109k and bar 109k are connected between the write data bus pair WDB and bar WDB and the flip-flop WFk of the write register 111, and an arbitrary pair is selected by the output YWk of the Y address decoder 107. The transfer circuit 109 has a function of transferring write data on the write data bus pair WDB and bar WDB to the write register 111.

  The write register 111 includes a flip-flop WFk (k = 1 to m) connected to the transistor pair 109k and the bar 109k of the transfer circuit 109. The flip-flop WFk is composed of two inverters WINnk and WINnk connected in antiparallel. The write register 111 has a function of storing write data (Write Data).

  The transfer circuit 113 is connected between the memory cell array 101 and the write register 111 and includes a plurality of transistor pairs 113k and bars 113k. These transistors are N-channel MOS transistors (NMOS). The transistor pair 113k and bar 113k are connected between the flip-flop WFk and the bit line pair BLk and bar BLk. The transfer circuit 113 has a function of transferring write data stored in the write register 111 to the memory cell array 101 in response to a write control signal PWT.

  The memory cell array 101 is further connected with a transfer circuit 115 that transfers the read data (Read Data) to the read register 117. The transfer circuit 115 includes a plurality of transistor pairs 115k and a bar 115k. These transistors are N-channel MOS transistors (NMOS). The transistor pair 115k and bar 115k are connected between the bit line pair BL and bar BL and the flip-flop RFk of the first read register 117, and the data read from the memory cell array 101 is subjected to the first read control. Transfer in response to the signal PRT1.

  The first read register 117 includes a flip-flop RFk (k = 1 to m) connected to the transistor pair 115k and the bar 115k of the transfer circuit 115. The flip-flop RFk is composed of two inverters RIink and RRink connected in antiparallel. The first read register 117 has a function of storing read data (ReadData) for one column transferred by the read transfer circuit 115.

  The transfer circuit 119 is connected between the first read data bus pair RD1, bar RD1 and the first read register 117, and includes a plurality of transistor pairs 119k, bar 119k. These transistors are N-channel MOS transistors (NMOS). The transistor pair 119k and bar 119k are connected between the flip-flop RFk and the first read data bus pair RD1 and bar RD1. The transfer circuit 119 transfers the read data stored in the first read register 117 to the first read data bus pair RD1 and bar RD1 in response to the address signal YR1k from the first Y address decoder (Read) 121. To do.

  A first output circuit 123 is connected to the first read data bus pair RD1 and bar RD1. The first output circuit 123 outputs the read data transferred from the first read register 117 to the first output terminal DOUT1.

  Furthermore, in the serial access memory of the present invention, the transfer circuit 125 is connected to the first read register 117. The transfer circuit 125 has a function of transferring data read from the memory cell array 101 in response to the second read control signal PRT2 to the second read register 127 via the first read register 117. Have. The transfer circuit 125 includes a plurality of transistor pairs 125k and a bar 125k. These transistors are N-channel MOS transistors (NMOS). The transistor pair 125k and the bar 125k are connected between the flip-flop RFk of the first read register 117 and the flip-flop RF′k of the second read register 127, and read from the memory cell Qki of the memory cell array 101. The issued data is transferred in response to the second read control signal PRT2.

  The second read register 127 includes a flip-flop RF′k (k = 1 to m) connected to the transistor pair 125 k and the bar 125 k of the transfer circuit 125. The flip-flop RF′k is composed of two inverters RIn′k and RIn′k connected in antiparallel. The second read register 127 has a function of storing read data (Read Data) for one column transferred by the read transfer circuit 125.

  The transfer circuit 129 is connected between the second read data bus pair RD2, bar RD2 and the second read register 127, and includes a plurality of transistor pairs 129k, bar 129k. These transistors are N-channel MOS transistors (NMOS). The transistor pair 129k and bar 129k are connected between the flip-flop RF'k and the second read data bus pair RD2 and bar RD2. The transfer circuit 129 transfers the read data stored in the second read register 127 to the second read data bus pair RD2 and bar RD2 in response to the address signal YR2k from the second Y address decoder (Read) 131. To do.

  A second output circuit 133 is connected to the second read data bus pair RD2 and bar RD2. The second output circuit 133 outputs the read data transferred from the second read register 127 to the second output terminal DOUT2.

  Next, to further facilitate the understanding of the present invention, the features of the present invention will be described with reference to FIG. In this case, the same parts as those in the serial access memory shown in FIG.

  As shown in FIG. 2, in the serial access memory of the present invention, a first read register 117 and a second read register 127 are connected in series. In this serial access memory, when data is input to the second read register 127, as shown in FIG. 2A, the transfer circuit 115 is turned on in response to the first read control signal PRT1, In response to the second read control signal PRT2, the transfer circuit 125 is turned on, and the data read from the memory cell array 101 is transferred to the second read register 127 via the first read register 117. . On the other hand, when data is input to the first read register 117, the transfer circuit 115 is turned on in response to the first read control signal PRT1, as shown in FIG. In response to the control signal PRT2, the transfer circuit 125 is turned OFF, and the data read from the memory cell array 101 is transferred to the first read register 117.

  Next, the detailed operation of the serial access memory of this embodiment will be described with reference to the timing charts of FIGS. In this case, in order to facilitate understanding of the description, the write operation and the read operation will be described separately. The write operation is described with reference to the timing chart of FIG. 3, and the read operation is described with reference to the timing chart of FIG. By operating the write operation and the read operation independently of each other, the serial access memory can be operated simultaneously. Such an operation can be easily understood by referring to the following description. The explanation is divided into periods for easy understanding.

  This serial access memory operates in response to a clock signal CLK. This clock signal CLK is output by a clock signal generation circuit 500 as shown in FIG. The clock signal generation circuit 500 includes an inverter unit 501 to which a plurality of odd-numbered inverters 5011 to 501j (j: odd number of j ≧ 3) are connected in series, an inverter 503, and a gate circuit 505. The output of the inverter 501j is connected to the input of the inverter 5011 and the input of the inverter 503. An output Po of the inverter 503 is connected to one input of the gate circuit 505. The other input of the gate circuit 505 is supplied with a clock control signal CLE.

A simple operation of the clock signal generation circuit 500 is shown in the timing chart of FIG. As shown in this timing chart, while the logic level of the clock control signal CLE is HIGH LEVEL (hereinafter referred to as “H”) (during the period t A to t B ), the clock signal is generated from the clock signal generation circuit 500. CLK is output.

  First, the operation when data is input from the outside will be described with reference to FIG.

<Period t1>
Write data (Write Data) d1 is input to the input circuit 105 from the input terminal DIN. The write data d1 is applied from the input circuit 105 to the write data bus pair WDB and bar WDB. At this time, since the address signal YW1 from the Y address decoder (Write) 107 is "H", the transistor pair 1091 and the bar 1091 of the transfer circuit 109 are turned on, and the write data d1 is the flip-flop of the write register 111. Input to WF1.

<Period t2>
Similarly, write data d2 is applied from the input circuit 105 to the write data bus WDB and bar WDB. At this time, since the address signal YW2 is “H”, the transistor pair 1092 and the bar 1092 of the transfer circuit 109 are turned ON, and the write data d2 is input to the flip-flop WF2 of the write register 111.

<Period t3>
Similarly, write data d3 is applied from the input circuit 105 to the write data bus WDB and bar WDB. At this time, since the address signal YW3 is “H”, the transistor pair 1093 and the bar 1093 of the transfer circuit 109 are turned ON, and the write data d3 is input to the flip-flop WF3 of the write register 111.

<Period t4>
Thereafter, in the same manner, the write data dm is given from the input circuit 105 to the write data bus WDB and the bar WDB. At this time, since the address signal YWm is “H”, the transistor pair 109m and the bar 109m of the transfer circuit 109 are turned ON, and the write data dm is input to the flip-flop WFm of the write register 111.

<Period t5>
A desired word line WLa (1 ≦ a ≦ n) is selected by the X address decoder 103. In this case, the potential level of the word line WLa becomes “H”. At the same time, the logic level of the write control signal PWT becomes “H” level, and the transistor pair 1131, the bars 1131 to 113m, and the bar 113m of the transfer circuit 113 are turned on. As a result, the write data d1 to dm stored in the write register 111 is written to the memory cells Q1, a to Qm, a connected to the word line WLa.

  As described above, the write data is written into the memory cell in the memory cell array 101.

  Next, the read operation of the serial access memory of this embodiment will be described with reference to FIG. In this case, an operation in which read data is output from the first and second output terminals DOUT1 and DOUT2 is shown.

<Period t1>
A desired word line WLa (1 ≦ a ≦ n) is selected by the X address decoder 103. In this case, the potential of the word line WLa becomes “H”. The word line WLa is connected to a memory cell group in which read data to be read from the second output terminal DOUT2 is stored.

  At this time, data stored in the memory cells C1, a to Cm, a connected to the word line WLa is read out to the bit line pairs BL1, bars BL1 to BLm, bar BLm connected to the respective memory cells. The data on the bit line pair is amplified by the sense amplifiers SA1 to SAm.

<Period t2>
Next, the logic levels of the first and second read control signals PRT1 and PRT2 become “H”. Accordingly, the transistor pair 1151, the bars 1151 to 115m, and the bar 115m of the transfer circuit 115 are turned on, and the transistor pair 1251 and the bars 1251 to 125m and 125m of the transfer circuit 125 are turned on.

  As a result, the data on the bit line pair BL1, the bars BL1 to BLm, and the bar BLm amplified by the sense amplifiers SA1 to SAm in the period t1 is transferred to the first read register 117 at a stretch. Further, the data is input to the second read register 127 via the first read register 117.

<Period t3>
Next, a desired word line WLb (1 ≦ b ≦ n) is selected by the X address decoder 103. In this case, the potential of the word line WLb becomes “H”. The word line WLb is connected to a memory cell group in which read data to be read from the first output terminal DOUT1 is stored.

  At this time, data stored in the memory cells C1, b to Cm, b connected to the word line WLb is read out to the bit line pairs BL1, bars BL1 to BLm, bar BLm connected to the respective memory cells. The data on the bit line pair is amplified by the sense amplifiers SA1 to SAm.

<Period t4>
Next, the logic level of the first read control signal PRT1 becomes “H”, and the logic level of the second read control signal PRT2 becomes “L”. Accordingly, the transistor pair 1151, the bars 1151 to 115m, and the bar 115m of the transfer circuit 115 are turned ON, and the transistor pair 1251 and the bars 1251 to 125m and 125m of the transfer circuit 125 are turned OFF.

  As a result, the data on the bit line pair BL1, the bars BL1 to BLm, and the bar BLm amplified by the sense amplifiers SA1 to SAm in the period t1 are input to the first read register 117 at a time.

<Period t5>
Next, the address signal YR11 from the first Y address decoder (Read) 121 becomes “H”, and the transistor pair 1191 and the bar 1191 of the transfer circuit 119 are turned ON. Accordingly, the read data stored in the flip-flop RF1 of the first read register 117 is transferred to the output circuit 123 via the first read data bus pair RD1 and the bar RD1. Then, the data D1 is output from the output circuit 123 to the output terminal DOUT1.

  Similarly, the address signal YR21 from the second Y address decoder (Read) 131 becomes “H”, and the transistor pair 1291 and the bar 1291 of the transfer circuit 129 are turned ON. Accordingly, the read data stored in the flip-flop RF′1 of the second read register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and the bar RD2. Then, the data D1 'is output from the output circuit 133 to the output terminal DOUT2.

<Period t6>
Next, the address signal YR12 from the first Y address decoder (Read) 121 becomes "H", and the transistor pair 1192 and bar 1192 of the transfer circuit 119 are turned ON. Therefore, the read data stored in the flip-flop RF2 of the first read register 117 is transferred to the output circuit 123 via the first read data bus pair RD1 and the bar RD1. Then, the data D2 is output from the output circuit 123 to the first output terminal DOUT1.

  Similarly, the address signal YR22 from the second Y address decoder (Read) 131 becomes “H”, and the transistor pair 1292 and bar 1292 of the transfer circuit 129 are turned ON. Accordingly, the read data stored in the flip-flop RF′2 of the second read register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and the bar RD2. Then, the data D2 'is output from the output circuit 133 to the second output terminal DOUT2.

  Thereafter, as shown in the periods t7 and t8, the data D3, D4... Dm are output from the first output terminal DOUT1, and the data D3 ′, D4 are output from the second output terminal DOUT2 in the same manner as described above. “... Dm” is sequentially output.

  As described above, data read from the memory cell array is sequentially output from the two output terminals.

  Here, generally, the following is considered as a serial access memory (referred to as a 2-port memory) from which data read from the memory cell array is read from two output terminals.

  First, memory cells of the same address are selected by selecting memory cells of the same address in the same two serial access memories that are arranged close to each other and each write data bus is connected to a common input circuit. This is a serial access memory that reads out data stored in memory cells at different addresses from independent output circuits by means of independent read operations after data is written into the memory cell.

  The second is a serial access memory in which two read registers are connected in parallel to a bit line pair of a memory cell array via a transfer circuit and alternately output read data.

  When comparing the serial access memory according to the first embodiment of the present invention with the first serial access memory described above, the first serial access memory realizes a two-port memory by two serial access memories. Since the serial access memory of the first embodiment of the present invention can realize a two-port memory by a single serial access memory, the serial access memory of the first embodiment of the present invention has the first serial access memory. The occupied area is much smaller than that of the memory. In addition, since the occupied area is reduced, the wiring length of each signal line is shortened, and an increase in operation speed can be expected. Furthermore, according to the serial access memory of the first embodiment of the present invention, since the 2-port memory is realized by a single serial access memory, the power consumption can be greatly reduced.

  In addition, since wiring and transfer circuits are densely arranged in the peripheral portion of the read register, as the integration of the memory cells progresses, the degree of design freedom in the peripheral portion accordingly decreases. However, since the read registers are arranged in parallel in the second serial access memory, the length of the wiring connecting them becomes long, so that the wiring design in the peripheral portion becomes difficult as the integration progresses. Alternatively, the pitch between the memory cells must be expanded in the column direction (direction parallel to the Y address decoder) in order to ensure the degree of design freedom in the peripheral portion. This hinders the integration of the semiconductor memory device. On the other hand, since the serial access memory according to the first embodiment of the present invention has a configuration in which two read registers are connected in series, the wiring connected to each of them is significantly shorter than the second serial access memory. . Therefore, the degree of freedom of design in the peripheral portion of the read register is ensured, and integration of the peripheral portion can be achieved according to the integration of the memory cells.

  As described above, according to the serial access memory of the first embodiment of the present invention, the same function as that realized by a plurality of serial access memories can be realized by a single serial access memory, and the degree of integration is also increased. Therefore, a low-cost serial access memory can be provided.

  Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the serial access memory according to the second embodiment of the present invention. In this case, the same reference numerals are given to the same elements as those in the serial access memory of the first embodiment, and the description thereof is omitted.

  The configuration of the serial access memory of the second embodiment is basically the same as that of the serial access memory of the first embodiment. The difference from the serial access memory of the first embodiment is that the first and second read Y address decoders 121 and 131 of the first embodiment are replaced with a common Y address decoder (Read) 601. It is. The configuration and function of this Y address decoder (Read) 601 are the same as those of the first and second Y address decoders 121 and 131.

  In other words, in the serial access memory of this embodiment, the address signal YRk (1 ≦ k ≦ m) output from the Y address decoder (Read) 601 is the transistor pair 119k of the transfer circuit 119, the gate electrode of the bar 119k, and the transfer circuit. 129 transistor pairs are supplied to the gate electrode of 129k and bar 129k.

  Next, the read operation of the serial access memory of this embodiment will be described with reference to the timing chart of FIG. In this case, an operation in which read data is output from the first and second output terminals DOUT1 and DOUT2 is shown. In this case, the operation of the serial access memory of this embodiment can be easily understood by referring to the description of the operation of the serial access memory of the first embodiment shown in the time chart of FIG. Therefore, the description of the periods t1 to t4 is omitted by referring to the description of FIG. 4, and the operation after the period t5 is described here.

<Period t5>
The address signal YR1 from the Y address decoder (Read) 601 becomes “H”, and the transistor pair 1191 and bar 1191 of the transfer circuit 119 and the transistor pair 1291 and bar 1291 of the transfer circuit 129 are turned ON. Accordingly, the read data stored in the flip-flop RF1 of the first read register 117 is transferred to the output circuit 123 via the first read data bus pair RD1 and the bar RD1, and the second read. Read data stored in the flip-flop RF′1 of the register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and the bar RD2. Then, the data D1 is output from the output circuit 123 to the output terminal DOUT1, and the data D1 ′ is output from the output circuit 133 to the output terminal DOUT2.

<Period t6>
Next, the address signal YR2 from the Y address decoder (Read) 601 becomes "H", the transistor pair 1192 and bar 1192 of the transfer circuit 119 are turned on, and the transistor pair 1292 and bar 1292 of the transfer circuit 129 are turned on. Accordingly, the read data stored in the flip-flop RF2 of the first read register 117 is transferred to the output circuit 123 via the first read data bus pair RD1 and the bar RD1, and the second read. Read data stored in the flip-flop RF′2 of the register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and the bar RD2. The data D2 is output from the output circuit 123 to the first output terminal DOUT1, and the data D2 ′ is output from the output circuit 133 to the second output terminal DOUT2.

  Thereafter, as shown in the periods t7 and t8, the data D3, D4... Dm are output from the first output terminal DOUT1, and the data D3 ′, D4 are output from the second output terminal DOUT2 in the same manner as described above. “... Dm” is sequentially output.

  As described above, data read from the memory cell array is sequentially output from the two output terminals.

By the serial access memory of the second embodiment lever, in addition to the effects of the serial access memory according to the first embodiment described above, further, because of the sharing Y address decoder for reading, small serial access memory footprint realized it can. As a field to which the serial access memory of the second embodiment is applied, it is not always necessary to correct the time axis, and low-quality TVs, VTRs and the like that can be accessed by the same Y address are conceivable.

  Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the serial access memory according to the third embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  The configuration of the serial access memory of the third embodiment is basically the same as that of the serial access memory of the second embodiment. The difference from the serial access memory of the second embodiment is that a first delay circuit 800 is connected between the first read data bus pair RD1, bar RD1 and the first output circuit 123. . The delay circuit 800 has a function of delaying the transfer for a predetermined period when transferring the data read on the read data bus. The delay circuit 800 may be arranged between the second read data bus pair RD2 and the bar RD2 and the second output circuit 133 instead of the arrangement as described above. That is, this delay circuit only needs to be connected between one of the read data bus pair and the output circuit.

  As shown in FIG. 9, in the delay circuit 800, flip-flops FF1 to FFx are connected in series so that read data can be delayed by a predetermined bit. When x = 2, a 2-bit delay occurs, and when x = 3, a 3-bit delay occurs. The delay circuit 800 operates in synchronization with the clock signal CLK.

  Next, the read operation of the serial access memory of this embodiment will be described with reference to the timing chart of FIG. In this case, an operation in which read data is output from the first and second output terminals DOUT1 and DOUT2 when a 3-bit delay occurs (X = 3) is shown. In this case, the operation of the serial access memory of this embodiment can be easily understood by referring to the description of the operation of the serial access memory of the first and second embodiments shown in the time charts of FIGS. it can. Accordingly, the description of the periods t1 to t4 is omitted by referring to the description of FIGS. 4 and 7, and the operation after the period t5 is described here.

<Period t5>
The address signal YR1 from the Y address decoder (Read) 601 becomes “H”, and the transistor pair 1191 and bar 1191 of the transfer circuit 119 and the transistor pair 1291 and bar 1291 of the transfer circuit 129 are turned ON. Accordingly, the read data stored in the flip-flop RF1 of the first read register 117 is transferred to the delay circuit 800 via the first read data bus pair RD1 and the bar RD1. Then, the data is stored in the flip-flop FF1. At the same time, the read data stored in the flip-flop RF′1 of the second read register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and the bar RD2. Then, the data D1 ′ is output from the output circuit 133 to the output terminal DOUT2.

<Period t6>
Next, the address signal YR2 from the Y address decoder (Read) 601 becomes "H", the transistor pair 1192 and bar 1192 of the transfer circuit 119 are turned on, and the transistor pair 1292 and bar 1292 of the transfer circuit 129 are turned on. Therefore, the read data stored in the flip-flop RF2 of the first read register 117 is transferred to the delay circuit 800 via the first read data bus pair RD1 and the bar RD1. At this time, the data stored in the flip-flop FF1 is input to the flip-flop FF2 in synchronization with the clock signal, and the data read from the flip-flop RF2 is input to the flip-flop FF1. At the same time, the read data stored in the flip-flop RF′2 of the second read register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and the bar RD2. Then, the data D2 ′ is output from the output circuit 133 to the second output terminal DOUT2.

<Period t7>
Next, the address signal YR3 from the Y address decoder (Read) 601 becomes "H", the transistor pair 1193 and the bar 1193 of the transfer circuit 119 are turned on, and the transistor pair 1293 and the bar 1293 of the transfer circuit 129 are turned on. Accordingly, the read data stored in the flip-flop RF3 of the first read register 117 is transferred to the delay circuit 800 via the first read data bus pair RD1 and the bar RD1. At this time, the data stored in the flip-flop FF1 is input to the flip-flop FF2 in synchronization with the clock signal, and the data stored in the flip-flop FF2 is input to the flip-flop FF3 in synchronization with the clock signal. The At the same time, the data read from the flip-flop RF3 is input to the flip-flop FF1. At the same time, the read data stored in the flip-flop RF′3 of the second read register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and bar RD2. Then, the data D3 ′ is output from the output circuit 133 to the second output terminal DOUT2.

<Period t8>
Next, the address signal YR4 from the Y address decoder (Read) 601 becomes "H", the transistor pair 1194 and bar 1194 of the transfer circuit 119 are turned on, and the transistor pair 1294 and bar 1294 of the transfer circuit 129 are turned on. Therefore, the read data stored in the flip-flop RF4 of the first read register 117 is transferred to the delay circuit 800 via the first read data bus pair RD1 and the bar RD1. At this time, the data stored in the flip-flop FF1 is input to the flip-flop FF2 in synchronization with the clock signal, and the data stored in the flip-flop FF2 is input to the flip-flop FF3 in synchronization with the clock signal. The data stored in the flip-flop FF3 is transferred to the output circuit 123. At the same time, the data read from the flip-flop RF4 is input to the flip-flop FF1. At the same time, the read data stored in the flip-flop RF′4 of the second read register 127 is transferred to the output circuit 133 via the second read data bus pair RD2 and bar RD2. Data D1 is output from the output circuit 123 to the first output terminal DOUT1, and data D4 ′ is output from the output circuit 133 to the second output terminal DOUT2.

  Thereafter, as shown in the periods t9, t10,..., Data D2, D3,... Dm-3 are output from the first output terminal DOUT1, and the second output terminal DOUT2 is output in the same manner as described above. Data D5 ′, D6 ′... Dm ′ are sequentially output. In this manner, data delayed by 3 bits from the data output from the second output terminal DOUT2 is output from the first output terminal DOUT1.

  As described above, data read from the memory cell array is sequentially output from the two output terminals.

  According to the present embodiment, in addition to the effects of the first and second embodiments described above, the data from one of the output terminals can be delayed, so that variations in data output are increased and the options for the user are expanded.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a block diagram showing the configuration of the serial access memory according to the fourth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of the fourth embodiment, a delay bypass circuit 1100 is connected to the delay circuit 800 of the serial access memory of the third embodiment.

  The delay bypass circuit 1100 includes transistors 1101, 1102, and 1103 and an inverter 1104 as shown in FIG. These transistors are N-type MOS transistors. The transistor 1101 is connected between the first read bus pair RD and bar RD and the first output circuit 123 in parallel with the delay circuit 800. The transistor 1102 is connected between the flip-flop FF1 and the first read bus pair RD1, bar RD1. The transistor 1103 is connected between the flip-flop FFx and the first output circuit 123. A delayed bypass signal PBP is applied to the control electrode of the transistor 1101. The delayed bypass signal PBP is supplied to both control electrodes of the transistors 1102 and 1103 via the inverter 1104. The delay bypass circuit 1100 has a function of controlling the delay of data transfer in response to the delay bypass signal PBP.

  In the serial access memory according to the fourth embodiment, when the delay bypass signal PBP becomes “H”, the transistor 1101 is turned on and the transistors T1102 and 1103 are turned off. In this case, the data on the read bus is bypassed through the delay circuit 800 and transferred to the first output circuit 123. That is, the delay effect is lost.

  On the other hand, when the delay bypass signal PBP is LOW LEVEL (hereinafter referred to as “L”), the transistor 1101 is turned off and the transistors 1102 and 1103 are turned on. Therefore, since the read data is transferred through the delay circuit 800, the output of the first output terminal DOUT1 is n bits relative to the output of the second output terminal DOUT2, as described in the third embodiment. Delayed.

  According to the serial access memory of this embodiment, in addition to the effects of the above-described embodiment, the function of the serial access memory of the above-described second or third embodiment can be selected by a delay bypass signal PBP given from the outside. It becomes possible.

  Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a block diagram showing the configuration of the serial access memory according to the fifth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of the fifth embodiment, the delay circuit 800 described in the third and fourth embodiments is added to the second read data bus pair RD2 and the bar RD2 of the serial access memory of the fourth embodiment. 'And a delay bypass circuit 1100' are added. The configurations of the delay circuit 800 ′ and the delay bypass circuit 1100 ′ are the same as those of the delay circuit 800 and the delay bypass circuit 1100. These circuits are controlled by a delayed bypass signal PBP '.

  The operation of the serial access memory of this embodiment can be easily understood with reference to the third and fourth embodiments described above.

  According to the serial access memory of this embodiment, in addition to the effects of the above-described embodiments, read data from the first and second output terminals can be arbitrarily delayed by a signal given from the outside.

  Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a block diagram showing the configuration of the serial access memory according to the sixth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, a delay selection circuit 1400 is connected between the first read data bus pair RD 1 and the bar RD 2 and the first output circuit 123. The delay selection circuit 1400 is composed of a plurality of transistors as shown in FIG. These transistors are arranged between the first read data bus RD1 and the bar RD1 and the first output circuit 123, and between each of the flip-flops FF1 to FFx and the first output circuit 123, respectively. Signals PBP1 to PBPx are provided. Depending on the logic level of each delay selection signal, ON / OFF of the transistor is controlled. These transistors are N-channel MOS transistors.

  According to the serial access memory of this embodiment, in addition to the effects of the above-described embodiments, any delay bit can be selected by the delay selection signals PBP1 to PBPx, so that the data output from the first output terminal can be selected. The delay can be set as appropriate.

  Next, a seventh embodiment of the present invention will be described with reference to FIG. FIG. 16 is a block diagram showing the configuration of the serial access memory according to the seventh embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the present embodiment, in addition to the configuration of the sixth embodiment described above, a delay selection circuit 1400 ′ having the same configuration as the delay selection circuit 1400 of the sixth embodiment described above is provided with a second read data bus pair RD2, It is connected between the bar RD2 and the second output circuit 133. The detailed configuration of the delay selection circuit 1400 'can be easily understood with reference to FIG. These transistors are arranged between the second read data bus RD2, bar RD2 and the second output circuit 133, and between the flip-flops FF1 ′ to FFx ′ and the second output circuit 133, respectively. Delay selection signals PBP1 'to PBPx' are provided. Each transistor is controlled to be turned on or off according to the logic level of each delay selection signal. These transistors are N-channel MOS transistors.

  According to the serial access memory of this embodiment, in addition to the effects of the above-described embodiment, any delay bit can be selected by the delay selection signals PBP1 to PBPx and PBP1 ′ to PBPx ′. The delay of data output from the output terminal can be set as appropriate.

  Next, an eighth embodiment of the present invention will be described with reference to FIG. FIG. 17 is a block diagram showing the configuration of the serial access memory according to the eighth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, a delay control address decoder 1700 for outputting delay selection signals PBP1 to PBPx is provided in the delay selection circuit 1400 of the serial access memory of the sixth embodiment described above. The delay control address decoder 1700 has a function of decoding addresses AA1 to AAx given from the outside in order to control delay bits and outputting delay selection signals PBP1 to PBPx.

  According to the present embodiment, in addition to the effects of the above-described embodiments, the delay selection signal is generated by an external address, so that the number of delay bits can be appropriately set with a small number of external signals.

  Next, a ninth embodiment of the present invention will be described with reference to FIG. FIG. 18 is a block diagram showing the configuration of the serial access memory according to the ninth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, the delay control address decoder outputs the delay selection signals PBP1 to PBPx described in the eighth embodiment to the delay selection circuits 1400 and 1400 ′ of the serial access memory of the seventh embodiment. 1700 and a delay control address decoder 1700 ′ having an equivalent function are provided. The delay control address decoder 1700 'has a function of decoding addresses AA1' to AAx 'given from the outside in order to control delay bits and outputting delay selection signals PBP1' to PBPx '.

  According to the present embodiment, in addition to the effects of the above-described embodiments, the delay selection signal is generated by an external address, so that the number of delay bits can be appropriately set with a small number of external signals.

  Next, a tenth embodiment of the present invention will be described with reference to FIG. FIG. 19 is a partial timing chart showing the operation of the serial access memory according to the tenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the same elements as those described above are denoted by the same reference numerals, and the description thereof is omitted. The basic operation of this embodiment can be easily understood by referring to the operation of the serial access memory of the first embodiment shown in FIG. 4 and the description thereof, so that the description thereof is omitted here.

  In the present embodiment, the timing at which the first read control signal PRT1 and the second read control signal PRT2 are applied is different from that in the first embodiment.

  That is, in the period t2, only the first read control signal PRT1 becomes “H”, and the read data is transferred from the memory cell array 101 to the first read register 117 and stored. Thereafter, in the period t3, only the second read control signal PRT2 becomes “H”, and the read data stored in the first read register 117 is transferred to the second read register 127.

  According to the present embodiment, it is possible to improve the data transfer efficiency and realize a serial access memory having a good operation margin.

  Next, an eleventh embodiment of the present invention will be described. The configuration of the serial access memory of this embodiment is basically the same as that of the first embodiment.

In this embodiment, the flip-flop RFk of the first read register 117 of the serial access memory of the first embodiment, the dimensions of the inverters RInk and RRink constituting the bar RFk, and the flip-flop of the second read register 127 are used. RFk, inverter RIn'k that make up the bar RFk, is de Imenjon of bar RIn'k different.

  That is, the dimensions of the P-channel MOS transistor (PMOS) and the N-channel MOS transistor (NMOS) constituting the inverters RIink and RRink are the same as those of the PMOS and NMOS constituting the inverter RIn'k and the bar RIn'k. Smaller than dimension.

  According to the present embodiment, it is possible to improve the data transfer efficiency and realize a serial access memory having a good operation margin.

  Next, a twelfth embodiment of the present invention will be described with reference to FIG. 20, FIG. 21, and FIG. 20, FIG. 21, and FIG. 22 are configuration block diagrams showing the configuration of the main part of the serial access memory according to the twelfth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, as shown in FIG. 20, resistors R1 and R2 are arranged between the second read register 127 and the power supply line VDD for supplying potential thereto. Further, as shown in FIG. 21, resistors R3 and R4 are provided between the first read register 117 and the power supply line VDD. As shown in FIG. 22, resistors R1, R2, R3, and R4 are provided between the first and second read registers 117 and 127 and the power supply line VDD, respectively.

  According to the present embodiment, it is possible to improve the data transfer efficiency and realize a serial access memory having a good operation margin.

  Next, a thirteenth embodiment of the present invention will be described with reference to FIG. FIG. 23 is a block diagram showing the configuration of the main part of the serial access memory according to the thirteenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, the flip-flops RFk, bars RFk, RF′k, and bar RF′k that constitute the first or second read register 117, 127 are clocked inverters CRInk, bar as shown in FIG. CRInk, CRIn′k bar CRIn′k. These clocked inverters are controlled by control signals φ1 and φ2.

  According to the present embodiment, it is possible to improve the data transfer efficiency and realize a serial access memory having a good operation margin.

  In the foregoing, various embodiments have been described in which a two-port memory is realized by connecting read registers in series. Further, various embodiments in which a two-port memory is realized by connecting a first serial access memory and a second serial access memory via a delay circuit will be described below.

  First, a fourteenth embodiment of the present invention will be described with reference to FIG. FIG. 24 is a block diagram showing the configuration of the main part of the serial access memory according to the fourteenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The serial access memory of this embodiment includes a first serial access memory unit 2400A and a second serial access memory unit 2400B.

  Elements having the same functions as those of the first serial access memory unit 2400A described above are denoted by “A” at the end of the reference numerals, and detailed description thereof is omitted. The detailed configuration of the first serial access memory unit 2400A can be easily understood with reference to FIG.

  In addition, elements having the same functions as the above-described elements of the second serial access memory unit 2400B are denoted by “B” at the end of the above-described reference numerals, and detailed description thereof is omitted. The detailed configuration of the second serial access memory unit 2400B can be easily understood with reference to FIG.

  In the serial access memory of this embodiment, the read data bus pair RDA and bar RDA of the first serial access memory unit 2400A and the write data bus pair WDB ′ and bar WDB ′ of the second serial access memory unit 2400B are between. A delay circuit 2403 is connected.

  The delay circuit 2403 has a function of delaying the data read from the first serial access memory unit 2400A for a predetermined period and transferring it to the write data bus pair WDB ′ and bar WDB ′ of the second serial access memory 2400B. . The necessity of delay by this delay circuit will be described later.

  A specific circuit configuration of the delay circuit 2403 is shown in FIG. The delay circuit 2403 includes a transistor pair 2701 and 2702 connected to the read data bus pair RDA and bar RDA, a transistor pair 2703 and 2704 connected to the write data bus pair WDB ′ and bar WDB ′, and a transistor pair 2701, 2702 is connected between the transistor pair 2703 and 2704 and is composed of an inverter 2705 and an inverter 2706, and an inverter which inverts the logic level of the control signal PY and applies it to the control electrodes of the transistor pair 2703 and 2704 2707. These transistors are N-channel MOS transistors.

  The read / write shared Y address decoder 2401 decodes the external address A0, bars A0 to An, and bar An, and outputs address signals YRA1 to YRAn and address signals YWB1 to YWBn. These address signal YRAk and address signal YWBk are signals of equivalent logic levels. Thereby, a desired transistor pair is turned on from the transistor pair of the transfer circuit 119A, and at the same time, a transistor pair corresponding to the desired transistor pair is turned on from the transistors of the transfer circuit 108B.

  As shown in FIG. 28, the read / write shared Y address decoder 2401 includes P-channel MOS transistors (hereinafter referred to as PMOS) PT1 to PTm to which a precharge signal PR is applied, inverters In1 to Inm, and an external circuit. The address A0, the bar A0An, and a plurality of N-channel MOS transistors (hereinafter referred to as NMOS) connected to terminals to which the bar An is applied. These NMOSs are arbitrarily connected to a terminal to which an external address is applied, and are arranged so that only the logical level of desired address signals YRAk and YWBk among the address signals YRA1 to YRAm is “H”.

  An operation example of the read / write shared Y address decoder 2401 is shown in the timing chart of FIG. In this case, the timing when the address signal YRAk and the address signal YWBk become “H” is shown.

In a period t0, the precharge signal PR changes from “H” to “L”. Thereafter, when the external address period t 1 is inputted, the address signals YRAk, only YWBk becomes "H" level. This is because an “H” signal is output from only the inverter Ink in the column by the combination of NMOS. As a result, the transistor pair 119Ak and bar 119Ak of the transfer circuit 119A and the transistor pair 108Bk and bar 108Bk of the transfer circuit 108B are turned ON. Although only an example of the operation is shown here, the operation when another column is selected can be easily understood with reference to this example.

  Next, the read operation of the serial access memory of this embodiment will be described with reference to FIG. The explanation is divided into periods for easy understanding. Here, the nodes in the flip-flop RF1 of the read register 117A are defined as nodes a and b as shown in FIG. 30, and the nodes in the flip-flop WF2 of the write register 111B are nodes as shown in FIG. c and d. This clock signal is output from the clock signal generation circuit shown in FIG. Here, an example in which data is transferred from the first serial access memory unit 2400A to the second serial access memory unit 2400B is mainly shown. Other operations can be easily understood by referring to the operation of the above-described embodiment.

<Period t1>
A desired word line WLa (1 ≦ a ≦ n) is selected by the X address decoder 103A. In this case, the potential of the word line WLa becomes “H”. The word line WLa is connected to a memory cell group in which read data to be read from the first output terminal DOUT1A is stored.

  At this time, data stored in the memory cells C1, a to Cm, a connected to the word line WLa is read out to the bit line pairs BL1, bars BL1 to BLm, bar BLm connected to the respective memory cells. The data on the bit line pair is amplified by the sense amplifiers SA1 to SAm.

<Period t2>
Next, the logic level of the first read control signal PRTA becomes “H”. Accordingly, the transistor pair 115A1, the bars 115A1 to 115Am, and the bar 115Am of the transfer circuit 115A are turned ON.

  As a result, the data on the bit line pair BL1, bars BL1 to BLm, and bar BLm amplified by the sense amplifiers SA1 to SAm in the period t1 is transferred to the first read register 117A all at once.

<Period t3>
Next, the clock signal CLK rises, and the timing signal φP rises in synchronization therewith. At this time, the read / write shared Y address decoder 2401 outputs the address signals YRA1 and YWB1, so that the transistor pair 119A1 and bar 119A1 of the transfer circuit 119A and the transistor pair 108B1 and bar 108B1 of the transfer circuit 108B are both turned ON. As a result, the data stored in the flip-flop FF1 of the read register 117A is transferred to the read data buses RDA and RDA, and is also transferred to the delay circuit 2403 and stored in the delay circuit 2403.

<Period t4>
When the timing signal φP becomes “L”, the transistor pair 2703 and 2704 of the delay circuit 2403 is turned on, and the data stored in the delay circuit 2403 is transferred to the write data buses WDB ′ and bar WDB ′.

<Period t5>
Next, the clock signal CLK rises, and in synchronization with this, the timing signal φP rises again. At this time, the read / write shared Y address decoder 2401 outputs address signals YRA2 and YWB2. As a result, the transistor pair 119A2 and the bar 119A2 of the transfer circuit 119A are turned on, so that the data stored in the flip-flop FF2 of the read register 117A is transferred to the read data buses RDA and RDA. At this time, since the timing signal φP becomes “H”, the transistor pair 2701 and 2702 of the delay circuit 2403 are turned ON, and the data on the read data bus RDA and the bar RDA is stored in the flip-flop DFF of the delay circuit 2403. At this time, the data transferred onto the write data bus pair WDB ′ and the bar WDB ′ in the period t4 is stored in the flip-flop WF2 of the write register 111B because the transistor pair 108B2 and the bar 108B2 of the transfer circuit 108B are turned on. The

  Thereafter, as shown in the period t6 to t13, the same cycle is repeated, the data is transferred from the first serial access memory unit 2400A to the second serial access memory unit 2400B, and the data is output from the output terminal DOUT1A. Is output. In this case, the data transfer operation from the first serial access memory unit 2400A to the second memory cell unit 2400B has been mainly described. However, referring to the operation of the above-described embodiment, data is output from the output terminal DOUT2B. Can be understood. In this way, the serial access memory of this embodiment realizes a 2-port memory.

According to the present invention, the delay circuit is arranged between the first serial access memory unit and the second serial memory unit, and the data output from the first serial access memory unit is delayed for a predetermined period. Deviation can be prevented within a range of 1-bit shift when data is written.

  Therefore, a function equivalent to the function realized by a plurality of serial access memories can be realized in a single package.

  Furthermore, since a read / write shared address decoder is arranged, further integration can be realized.

  Here, a detailed explanation of the reason why the delay circuit is arranged will be given below.

  In order to integrate a plurality of serial access memories, for example, when two serial access memories are simply connected to form one chip, the following problems occur.

  Now consider the output timing of the first serial memory. If the output operation is started from the rising edge of the nth clock in the period tn, the output is actually output from the first serial memory with a delay time ΔtAC (referred to as access time) from the period tn.

Next, consider the input timing of the second serial register. Assuming that the input operation is started from the rising edge of the mth clock in the period tm, the input signal is actually an input terminal earlier than the time tm by a certain time ΔtH (referred to as hold time) in consideration of the circuit operation margin. If it is not fixed above, correct data will be rewritten after incorrect data is written in the second serial memory section , so that a somewhat longer operating margin is necessary to reliably capture the data to be written. It is necessary to prepare, and high-speed writing with a good operation margin cannot be performed.

However, according to the serial access memory of this embodiment of the present invention, since the delay circuit for adjusting delays the data from the first serial access memory portion in the range of the shift of one bit is provided, writing Control can be performed so that rewriting of data does not occur in the middle, preparation for a long operating margin can be suppressed, and a plurality of serial access memories (two in the above-described embodiment can be easily obtained by using a conventional circuit design technique. Serial access memory) can be made into one chip.

  Next, a fifteenth embodiment of the present invention will be described with reference to FIG. FIG. 33 is a block diagram showing the configuration of the main part of the serial access memory according to the fifteenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of this embodiment, an initialization circuit 3300 is connected to the read data bus RDA and bar RDA of the serial access memory described in the fourteenth embodiment.

  The initialization circuit 3300 includes transistors 3301, 3302, and 3303, and has a function of applying a predetermined potential for initialization to the read data bus RDA and the bar RDA in response to an initialization signal EQ. These transistors are NMOS. The transistor 3301 is connected between the read data bus RDA and a power source having a predetermined potential, the transistor 3302 is connected between the read data bus bar RDA and the power source, and the transistor 3303 is connected to the read data bus RDA and the read data bus bar RDA. Connected between. An initialization signal EQ is applied to the control electrodes of these transistors.

  The operation of this serial access memory is basically the same as the operation described in the fourteenth embodiment described above, but the read data bus RDA, The difference is that RDA is initialized to a predetermined potential.

  Hereinafter, the operation of the serial access memory of this embodiment will be described with reference to the timing chart of FIG. The description will be made after every period as in the above-described embodiment.

<Period t1>
A desired word line WLa (1 ≦ a ≦ n) is selected by the X address decoder 103A. In this case, the potential of the word line WLa becomes “H”. The word line WLa is connected to a memory cell group in which read data to be read from the first output terminal DOUT1A is stored.

  At this time, data stored in the memory cells C1, a to Cm, a connected to the word line WLa is read out to the bit line pairs BL1, bars BL1 to BLm, bar BLm connected to the respective memory cells. The data on the bit line pair is amplified by the sense amplifiers SA1 to SAm.

<Period t2>
Next, the logic level of the first read control signal PRTA becomes “H”. Accordingly, the transistor pair 115A1, the bars 115A1 to 115Am, and the bar 115Am of the transfer circuit 115A are turned ON.

  As a result, the data on the bit line pair BL1, bars BL1 to BLm, and bar BLm amplified by the sense amplifiers SA1 to SAm in the period t1 is transferred to the first read register 117A all at once.

<Period t3>
Next, the clock signal CLK rises, and the timing signal φP rises in synchronization therewith. At this time, the read / write shared Y address decoder 2401 outputs the address signals YRA1 and YWB1, so that the transistor pair 119A1 and bar 119A1 of the transfer circuit 119A and the transistor pair 108B1 and bar 108B1 of the transfer circuit 108B are both turned ON.

  Further, since the initialization signal EQ changes from “H” to “L”, data transfer to the read data bus RDA and the bar RDA becomes possible. Before the period t3, the read data bus RDA and bar RDA are initialized to the power supply potential.

  As a result, the data stored in the flip-flop FF1 of the read register 117A is transferred to the read data buses RDA and RDA, and is also transferred to the delay circuit 2403 and stored in the delay circuit 2403.

<Period t4>
When the timing signal φP becomes “L”, the transistor pair 2703 and 2704 of the delay circuit 2403 is turned on, and the data stored in the flip-flop DFF of the delay circuit 2403 is transferred to the write data buses WDB ′ and bar WDB ′. .

  At the same time, the initialization signal EQ becomes “H”, and the read data bus RDA and bar RDA are initialized to the power supply voltage level.

<Period 5>
The clock signal CLK rises, and the timing signal PY rises again in synchronization therewith. At this time, the read / write shared address decoder 2401 outputs the address signals YRA2 and YWB2 simultaneously.

  As a result, the transistor pair 119A2 and the bar 119A2 of the transfer circuit 119A are turned on, so that the data stored in the flip-flop RF2 of the read register 117A is transferred to the read data buses RDA and RDA.

  Further, since the timing signal φP becomes “H”, the transistor pair 2701 and 2702 of the delay circuit 2403 are turned on, and the data is stored in the flip-flop circuit DFF of the delay circuit 2403.

  Further, the data transferred to the write data buses WDB 'and bar WDB' in the period t4 is stored in the flip-flop WF2 of the write register 111B.

  Thereafter, the same cycle is repeated as shown in the period 5 to the period t13.

  According to the serial access memory of this embodiment, in addition to the effect of the serial access memory of the fourteenth embodiment, the read data bus initialization circuit is provided, so that higher speed access is possible.

Next, a sixteenth embodiment of the present invention will be described with reference to FIG. 35. FIG. 35 is a block diagram showing the configuration of the main part of the serial access memory according to the sixteenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

In the serial access memory of this embodiment, the write registers 111A and 111B and transfer circuits 113A and 113B of the serial access memory of the fourteenth embodiment are not provided, and the transfer circuits 108A and 108B are directly connected to the memory cell arrays 101A and 101B. Yes.

  In this serial access memory, nodes c and d are defined as nodes corresponding to the nodes c and d in the fourteenth embodiment.

  The operation of the serial access memory of this embodiment can be easily understood by referring to the description of the operation of the fifteenth embodiment. In the serial access memory of this embodiment, the data on the write data bus RDA and the bar RDA are directly transferred to the memory cell array 101B.

  According to the serial access memory of this embodiment, in addition to the effect of the fourteenth embodiment, the use of reading data from the second serial access memory does not cause competition with the writing of data in the second serial memory. When this is applied, since a 2-port memory can be realized without providing a write register, the chip size can be greatly reduced.

  Next, a seventeenth embodiment of the present invention will be described with reference to FIG. FIG. 36 is a block diagram showing the configuration of the main part of the serial access memory according to the seventeenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of this embodiment, an initialization circuit 3300 is connected to the read data buses RDA and RDA of the serial access memory of the fifteenth embodiment.

  The operation of the serial access memory of this embodiment can be understood by referring to the description of the operations of the fourteenth to sixteenth embodiments described above.

  According to the serial access memory of the present embodiment, in addition to the effects of the fifteenth embodiment, since the initialization circuit is provided, higher speed access is possible.

  Next, an eighteenth embodiment of the present invention will be described with reference to FIG. FIG. 37 is a block diagram showing the configuration of the main part of the serial access memory according to the eighteenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

The serial access memory according to the present embodiment, the fourteenth embodiment serial access memory with read register 117A transfer circuit 115A and the read register 117 B transferring circuit 115 B is not in the transfer circuit 119A directly, the memory cell array 101A The transfer circuit 119B is directly connected to the memory cell array 101B.

  In this serial access memory, nodes a and b are defined as nodes corresponding to the nodes a and b in the fourteenth embodiment.

  The operation of the serial access memory of this embodiment can be easily understood with reference to the description of the operation of the fourteenth embodiment.

  According to the serial access memory of this embodiment, in addition to the effect of the fourteenth embodiment, there is no conflict between the data write timing of the second serial memory and the data read timing of the first serial memory. When applied to various applications, a two-port memory can be realized without providing a read data data register, so that the chip size can be greatly reduced.

  Next, a nineteenth embodiment of the present invention will be described with reference to FIG. FIG. 38 is a block diagram showing the configuration of the main part of the serial access memory according to the nineteenth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of this embodiment, the initialization circuit 3300 is connected to the read data buses RDA and RDA of the serial access memory of the eighteenth embodiment.

  The operation of the serial access memory of this embodiment can be understood by referring to the description of the operations of the fifteenth to eighteenth embodiments described above.

  According to the serial access memory of this embodiment, in addition to the effect of the embodiment 18, since the initialization circuit is provided, a higher speed access is possible.

  Next, a twentieth embodiment of the present invention will be described with reference to FIG. FIG. 39 is a block diagram showing the configuration of the main part of the serial access memory according to the twentieth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of the present embodiment, the write register 111A and transfer circuit 113A of the first serial access memory of the fourteenth embodiment, the read register 117A and transfer circuit 115A, and the write register of the second serial access memory 111B, transfer circuit 113B, read register 115B and transfer circuit 117B are not provided, transfer circuit 108A and transfer circuit 119A are directly connected to memory cell array 101A, and transfer circuit 108B and transfer circuit 119B are directly connected to memory cell array 101B. ing.

  The operation of the serial access memory of this embodiment can be easily understood with reference to the description of the operation of the fourteenth embodiment. In this case, since there are no write and read registers, data is directly input / output between the write data bus and read data bus and the memory cell arrays 101A and 101B.

  According to the serial access memory of this embodiment, in addition to the effects of the embodiment 14, when it is applied to an application where high speed access is not required, the read data data register and the write data register are not provided. Since a port memory can be realized, the chip size can be greatly reduced and an inexpensive memory can be provided.

  Next, a twenty-first embodiment of the present invention will be described with reference to FIG. FIG. 40 is a block diagram showing the configuration of the main part of the serial access memory according to the 21st embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of this embodiment, an initialization circuit 3300 is connected to the read data buses RDA and RDA of the serial access memory of the twentieth embodiment.

  The operation of the serial access memory of this embodiment can be understood by referring to the description of the operations of the fourteenth, fifteenth and twentieth embodiments described above.

  According to the serial access memory of the present embodiment, in addition to the effects of the twentieth embodiment, since the initialization circuit is provided, higher speed access is possible.

  Next, a twenty-second embodiment of the present invention is described with reference to FIG. FIG. 41 is a block diagram showing the configuration of the main part of the serial access memory according to the twenty-second embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of this embodiment, a storage circuit 4100 is connected to the write data buses WDB 'and bar WDB' of the second serial access memory of the fourteenth embodiment.

  As shown in FIG. 42, the storage circuit 4100 includes two flip-flops MFF and bar MFF, and has a function of holding data on the write data buses WDB ′ and bar WDB ′.

  The operation of the serial access memory of this embodiment can be easily understood with reference to the fifteenth embodiment described above. In this case, the data on the write data buses WDB 'and bar WDB' are held until the next data is transferred.

  According to the serial access memory of this embodiment, in addition to the effect of the fourteenth embodiment, when the memory operation is required to be paused, it is stored in the write data buses WDB ′ and bar WDB ′ of the second serial memory. Since the circuit 4100 is connected, reliable operation is guaranteed.

  Next, a twenty-third embodiment of the present invention is described with reference to FIG. FIG. 43 is a block diagram showing the configuration of the main part of the serial access memory according to the twenty-third embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory of this embodiment, a storage circuit 4100 is connected to the write data buses WDB 'and bar WDB' of the second serial access memory of the fifteenth embodiment.

  The operation of the serial access memory of this embodiment can be easily understood with reference to the above-described fifteenth and sixteenth embodiments. In this case, the data on the write data buses WDB 'and bar WDB' are held until the next data is transferred.

  According to the serial access memory of this embodiment, in addition to the effects of the fifteenth and sixteenth embodiments, when the memory operation is required to be paused, the write data buses WDB ′ and bar WDB ′ of the second serial memory are required. Since the memory circuit 4100 is connected to this, reliable operation is guaranteed.

  Further, similarly to the twenty-second and twenty-third embodiments, if the storage circuit 4100 is connected to the write data buses WDB ′ and bar WDB ′ of the second serial access memory of the sixteenth to twenty-first embodiments, respectively. In addition to the effects of the sixteenth to twenty-first embodiments, when the memory operation is required to be paused, the memory circuit 4100 is connected to the write data buses WDB ′ and WDB ′ of the second serial memory. Therefore, reliable operation is guaranteed.

  Next, an embodiment in which the serial access memory of the above-described embodiment is applied to an apparatus having two banks of memories will be described.

  First, a twenty-fourth embodiment of the present invention will be described with reference to FIG. FIG. 44 is a block diagram showing the configuration of the main part of the serial access memory according to the twenty-fourth embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The serial access memory of this embodiment includes a first serial access memory unit 2400A, a second serial access memory unit 2400B, a third serial access memory unit 2400C, and a fourth serial access memory unit 2400D.

  Elements having the same functions as those of the first serial access memory unit 2400A described above are denoted by “A” at the end of the reference numerals, and detailed description thereof is omitted. The detailed configuration of the first serial access memory unit 2400A can be easily understood with reference to FIG.

  In addition, elements having the same functions as the above-described elements of the second serial access memory unit 2400B are denoted by “B” at the end of the above-described reference numerals, and detailed description thereof is omitted. The detailed configuration of the second serial access memory unit 2400B can be easily understood with reference to FIG.

  Further, elements having the same functions as those of the previously described elements of the third serial access memory unit 2400C are denoted by “C” at the end of the above reference numerals, and detailed description thereof is omitted. The detailed configuration of the third serial access memory unit 2400C can be easily understood with reference to FIGS. The write data bus pair WDB, bar WDB, and read data bus RDA, bar RDA of the third serial access memory unit 2400C are the write data bus pair WDB, bar WDB, and read data bus RDA of the first serial access memory unit 2400A. , Connected to the bar RDA.

  Further, elements having the same functions as those of the fourth serial access memory unit 2400D described above are denoted by “D” at the end of the reference numerals, and detailed description thereof is omitted. The detailed configuration of the fourth serial access memory unit 2400D can be easily understood with reference to FIGS. The write data bus pair WDB ′, bar WDB ′ and the read data bus RDA, bar RDA of the fourth serial access memory unit 2400D are the same as the write data bus pair WDB ′, bar WDB ′ of the second serial access memory unit 2400B. The read data bus RDA and the bar RDA are connected.

  The basic operation of the serial access memory of this embodiment can be understood with reference to the description of the operation of the fourteenth embodiment, and only the characteristic operation will be described here with reference to FIGS. 45 and 46. Is done. 45 and 46 are schematic circuit block diagrams for explaining the characteristic operation of the serial access memory of this embodiment.

  As shown in FIG. 45, for example, the first serial access memory unit 2400A and the second serial access memory unit 2400B transfer processing for writing data (WRITE IN) and transfer processing for reading data (READ OUT). The third serial access memory unit 2400C and the fourth serial access memory unit 2400D can perform an access operation simultaneously. Similarly, as shown in FIG. 46, for example, the third serial access memory unit 2400C and the fourth serial access memory unit 2400D transfer processing for writing data (WRITE IN) and transfer processing for reading data. While (READ OUT) is being performed, the first serial access memory unit 2400A and the second serial access memory unit 2400B can simultaneously perform an access operation. In this case, “a”, “b”, “c”, and “d” in the figure represent arbitrary bits of the register to be accessed, and are shown for easy understanding of the description.

  According to the serial access memory of this embodiment, since it can operate as described above, data can be written and read without interruption, and in addition to the effects of the embodiment 14, a serial that can be applied to a wider range of applications. An access memory can be provided.

  Similarly, 25th to 31st embodiments in which the serial access memory of this embodiment is applied to the serial access memories of the various embodiments described above are shown. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted. A detailed description thereof can be understood with reference to the above-described embodiments.

  In the twenty-fifth embodiment, as shown in FIG. 47, the serial access memory of the fifteenth embodiment is provided with two banks like the serial access memory of the twenty-fourth embodiment.

  In the twenty-sixth embodiment, as shown in FIG. 48, the serial access memory of the sixteenth embodiment is provided with two banks like the serial access memory of the twenty-fourth embodiment.

  In the twenty-seventh embodiment, as shown in FIG. 49, the serial access memory of the seventeenth embodiment is provided with two banks like the serial access memory of the twenty-fourth embodiment.

  In the twenty-eighth embodiment, as shown in FIG. 50, the serial access memory of the eighteenth embodiment is provided with two banks like the serial access memory of the twenty-fourth embodiment.

  In the twenty-ninth embodiment, as shown in FIG. 51, the serial access memory of the nineteenth embodiment is provided with two banks like the serial access memory of the twenty-fourth embodiment.

  In the 30th embodiment, as shown in FIG. 52, the serial access memory of the 22nd embodiment is provided with two banks like the serial access memory of the 24th embodiment.

  In the thirty-first embodiment, as shown in FIG. 53, the serial access memory of the twenty-third embodiment is provided with two banks like the serial access memory of the twenty-fourth embodiment.

  Further, although not shown, the memory circuit 4100 is provided in the write data buses WDB and WDB of the serial access memories of the twenty-second and twenty-third embodiments and the second serial access memories of the sixteenth to twenty-first embodiments. Similarly, the twenty-fourth embodiment can be applied to a serial access memory having a connected configuration to form a two-bank configuration.

  According to the serial access memories of the twenty-fifth to thirty-first embodiments, it is possible to operate as described in the twenty-fourth embodiment, so that data can be written and read without interruption. In addition to the effects, it is possible to provide a serial access memory that can be applied to a wider range of applications.

  Next, a thirty-second embodiment of the present invention is described with reference to FIG. FIG. 54 is a block diagram showing the configuration of the main part of the serial access memory according to the thirty-second embodiment of the present invention. In this case, in order to facilitate understanding of the description of the present embodiment, the above-described elements are appropriately formed into blocks and schematically shown. The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted.

  In the serial access memory according to the present embodiment, an address counter circuit 5400 for providing a common X address to the X address decoders 103A and 103B according to the various embodiments described above is arranged.

  This address counter circuit 5400 has a function of providing X addresses A0X, A1X... AnX in common to the X address decoders 103A and 103B in response to the clock signal CLK and the reset signal Reset. The address counter circuit 5400 includes a plurality of unit address counter circuits CNTR0 to CNTRn.

  As shown in FIG. 55, the unit address counter circuit CNTRi receives a reset signal Reset and an input Bn−1, and outputs an output Bn and an X address AiX. When the reset signal Reset becomes “H”, the output Bn of the unit address counter circuit CNTRi becomes “L”.

  A specific configuration of the unit address counter circuit CNTRi is shown in FIG. The unit address counter circuit CNTRi includes an inverter In1 to which an input Bn-1 is applied to an input terminal, an output of the inverter In1 and a transfer gate TR1 controlled by the input Bn-1, and an output and input Bn- of the inverter In1. The reset signal Reset is input to one input terminal of the transfer gate TR controlled by 1 and the output of the inverter In2 is connected to the other input terminal via the transfer gate TR1 and the X address AiX and the transfer gate TR2. NOR gate, transfer gate TR3 controlled by the output and input Bn-1 of the inverter In1, transfer gate TR4 controlled by the output and input Bn-1 of the inverter In1, and transfer gate TR And an inverter In4 whose input terminal is connected to the output Bn via the transfer gate TR4, an inverter In5 whose input is connected to the output of the inverter In4, and whose output is connected to the output Bn-1 Consists of

  As shown in FIG. 57, a plurality of such unit address counter circuits AiX are connected in series to constitute an address counter circuit 5400. An example of the operation of the address counter circuit 5400 is shown in the partial timing chart of FIG.

  Here, the operation of the serial access memory of this embodiment will be briefly described with reference to FIG.

  When the X address is supplied from the address counter circuit 5400 to the X address decoder 103A and the X address decoder 103B, the memory cell array 101A and the memory cell array 101BA1 respectively use the same address, for example, the word line WL1 of the first memory cell array 101A. The word line WL1 of the second memory cell array 101B is selected.

  In this case, the word line WL1 of the memory cell array 101A rises, and data is transferred from the first serial access memory 101A to the first read register 117A ((A) in the figure), and then delayed by 1 bit by the delay circuit. Then, the data is written into the second write register 111B ((B) in the figure). Thereafter, the word line WL0 of the memory cell array 101B rises, and the contents of the second write register 111B are transferred to a memory cell connected to the word line WL0 once ((C) in the figure).

  That is, data in the memory cell connected to the word line of the first memory cell array 101A selected by the common X address is transferred to the first read register 117A, and the first output is made in response to the clock signal CLK. The signal is output from the terminal DOUT1 and is written to the write register 111B after being delayed for a predetermined period. Thereafter, after the writing to the write register 111B is completed, data is written into the memory cell connected to the word line of the second memory cell array 101B selected by the common X address.

  According to the serial access memory of this embodiment, in addition to the effects of the above-described various embodiments, an address counter circuit is provided to provide a common address to the first and second X address decoders. The number of circuits can be reduced, and as a result, the chip area can be reduced.

  As described above with reference to various embodiments, according to the present invention, a serial access memory device having a function equivalent to a function conventionally realized by a plurality of serial access memories can be easily obtained by one chip. Can be realized.

  The serial access memory of the present invention described above is applied to a display device 6000 as shown in FIG.

  The display device 6000 includes a serial access memory 6001 according to the present invention, a D / A converter 6002 that receives the output of the serial access memory 6001, performs digital-analog conversion, and outputs data, and the serial access memory 6001 and the D / A A controller 6003 that controls the A converter 6002 and a display unit 6004 that displays data from the D / A conversion circuit 6002 as display data.

  In addition, the serial access memory of the present invention can be applied to various fields.

  While this invention has been described using illustrative embodiments, this description should not be taken in a limiting sense. Various modifications of this illustrative embodiment, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this description. It is therefore contemplated that the following claims will cover all such modifications or embodiments as included within the true scope of the invention.

1 is a circuit block diagram showing a configuration of a main part of a serial access memory according to a first embodiment of the present invention. It is a schematic diagram explaining the characteristic part of the serial access memory of a 1st Example. 3 is a partial timing chart showing a data write operation of the serial access memory according to the first embodiment. 3 is a partial timing chart showing a data read operation of the serial access memory according to the first embodiment. 2 is a circuit block diagram showing a configuration of a clock signal generation circuit of the serial access memory of the first embodiment and a partial timing chart showing the operation thereof. FIG. FIG. 5 is a circuit block diagram showing a configuration of a main part of a serial access memory according to a second embodiment of the present invention. 12 is a partial timing chart showing a data read operation of the serial access memory according to the second embodiment. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 3rd Example of this invention. It is a circuit block diagram which shows the structure of the delay circuit of a 3rd Example. It is a partial timing chart which shows the read-out operation | movement of the data of the serial access memory of a 3rd Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 4th Example of this invention. It is a circuit block diagram which shows the structure of the delay bypass circuit of a 4th Example. FIG. 10 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a fifth example of the present invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 6th Example of this invention. It is a circuit block diagram which shows the structure of the delay selection circuit of a 6th Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 7th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 8th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 9th Example of this invention. It is a partial timing chart which shows the read-out operation | movement of the data of the serial access memory of a 10th Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 12th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 12th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 12th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the read register of the serial access memory of 13th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 14th Example of this invention. It is a circuit block diagram which shows the concrete structure of the 1st serial access memory part of 14th Example. It is a circuit block diagram which shows the concrete structure of the 2nd serial access memory part of 14th Example. It is a circuit block diagram which shows the structure of the delay circuit of 14th Example. It is a circuit block diagram showing a specific circuit configuration of a read / write shared Y address decoder 2401 of the fourteenth embodiment. It is a partial timing chart which shows the operation example of the read / write common Y address decoder of 14th Example. It is a circuit block diagram which shows the structure of the principal part of the register | resistor 117A for a read of 14th Example. It is a circuit block diagram which shows the structure of the principal part of the write register 111B of 14th Example. It is a partial timing chart which shows the operation | movement of the serial access memory of 14th Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of 15th Example of this invention. It is a partial timing chart which shows the operation | movement of the serial access memory of a 15th Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 16th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 17th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 18th Example of this invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a nineteenth embodiment of the present invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 20th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 21st Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 22nd Example of this invention. It is a circuit block diagram which shows the structure of the memory circuit of a 22nd Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 23rd Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 24th Example of this invention. It is a typical circuit block diagram explaining operation | movement of the serial access memory of a 24th Example. It is a typical circuit block diagram explaining operation | movement of the serial access memory of a 24th Example. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 25th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 26th Example of this invention. It is a circuit block diagram which shows typically the structure of the principal part of the serial access memory of the 27th Example of this invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a twenty-eighth embodiment of the present invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 29th embodiment of the present invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a thirtieth embodiment of the present invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a thirty-first embodiment of the present invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a thirty-second embodiment of the present invention. FIG. 38 is a circuit block diagram showing a unit address counter circuit according to a thirty-second embodiment. FIG. 38 is a circuit block diagram showing a specific configuration of a unit address counter circuit according to a thirty-second embodiment. It is a circuit block diagram which shows the structure of the address counter circuit of a 32nd Example. It is a partial timing chart which shows the operation | movement of the address counter circuit of a 32nd Example. FIG. 38 is a partial timing chart illustrating the operation of a thirty-second serial access memory. It is a circuit block diagram which shows the example which applied the serial access memory of this invention to the display apparatus.

Explanation of symbols

101 memory cell array 103 X address decoder 105 input circuit 107 Y address decoder (for writing)
109, 113, 115, 119, 125, 129 Transfer circuit 111 Write register 117 Read register 121 First Y address decoder (for write)
123 First output circuit 127 Second read register 131 Second Y address decoder 133 Second output circuit

Claims (8)

A read data bus included in the first serial access memory unit;
An output circuit connected to the read data bus;
A write data bus included in the second serial access memory unit;
In the first serial access memory unit, a first word line, a first bit line pair disposed so as to intersect the first word line, the first word line, and the first word line A first memory cell connected to an intersection with one bit line pair and storing the first data; a first memory cell connected to the first bit line pair; connected to the read data bus; , And a first switch circuit connected between the first bit line pair and the output register, the first bit line pair in response to a first control signal. Between the output register and the read data bus, and the first switch circuit for transferring the first data to the output register, and the first register connected between the output register and the read data bus A transfer circuit comprising a first column signal; Said first serial access memory portion that includes a first transfer circuit for transferring said first data in response to the read data bus,
In the second serial access memory unit, a second word line, a second bit line pair disposed so as to intersect the second word line, the second word line, and the second A second memory cell connected to an intersection of the two bit line pairs and storing second data; and connected between the second bit line pair and the write data bus; And a second switch circuit connected between the second bit line pair and the input register, wherein the second bit line pair is responsive to a second control signal. Between the input register and the write data bus, and the second switch circuit for providing the first data to the second bit line pair. A second transfer circuit, wherein the first column The second serial access memory section comprising: the second transfer circuit for transferring the first data on the write data bus to the input register in response to a second column signal given together with a signal When,
A Y decoder circuit that applies the first column signal to the first transfer circuit and supplies the second column signal to the second transfer circuit;
And a delay circuit connected to the read data bus and the write data bus, the delay circuit delaying the first data on the read data bus and supplying the delayed data to the write data bus. Serial access memory device.   An initialization circuit connected to the read data bus, the initialization circuit having a predetermined potential in the read data bus to which the first data is applied in response to an initialization signal. The serial access memory device according to claim 1.   2. The data storage circuit which is disposed between the delay circuit and the second transfer circuit and stores the first data given from the first transfer circuit. Serial access memory device.   3. The data storage circuit which is disposed between the delay circuit and the second transfer circuit and stores the first data given from the first transfer circuit. Serial access memory device.   A first X decoder circuit for supplying a first selection signal to the first word line; a second X decoder circuit for supplying a second selection signal to the second word line; and the first and second 2. The serial access memory device according to claim 1, further comprising an address counter for giving a common address to said X decoder.   A first X decoder circuit for supplying a first selection signal to the first word line; a second X decoder circuit for supplying a second selection signal to the second word line; and the first and second 5. The serial access memory device according to claim 4, further comprising an address counter for giving a common address to said X decoder.   2. The serial access memory device according to claim 1, a D / A conversion circuit that receives output data from the output circuit of the serial access memory device, converts the output data from a digital value to an analog value, and outputs the data, and the serial A display device comprising: an access memory device; a control circuit that controls the D / A conversion circuit; and a display unit that displays an image on a screen in accordance with an output from the D / A conversion circuit.   A semiconductor memory device, wherein the serial access memory device according to claim 1 is covered with a package resin.

Images