JPH07182856A - Serial access memory and method for transferring data - Google Patents

Abstract

PURPOSE:To reduce an occupancy area and to reduce a cost by realizing a function equivalent to the function which was realized by plural pieces of serial access memories by connecting two transferring registers in series. CONSTITUTION:The registers 117, 127 for read are connected in series. In the serial access memory, when the data are inputted to the register 127, a transfer circuit 115 is turned ON in response to a read control signal PRT1, and the transfer circuit 125 is turned ON in response to the PRT2. Thus, the data read out from a memory cell array 101 are transferred to the register 127 through the register 117. On the other hand, when the data are inputted to the register 117, the circuit 115 is turned ON in response to the PRT1, and the circuit 127 is turned OFF in response to the PRT2, and the data read out from the array 101 are transferred to the register 117. By such a constitution, the memory with a low cost is obtained.

Description

Description: BACKGROUND OF THE INVENTION The present invention has a plurality of output ports.
Serial access memory. 2. Description of the Related Art Recently, serial devices having a plurality of output ports
Access memory (2-port memory) is a digital
Screen noise removal for Levi, digital VTR, etc.
It is used to correct the movement of the (correction of the time axis). In particular, a screen composed of odd lines and
One display screen with a screen composed of even lines
Configured current TV system (called interlaced system
In order to remove the noise generated on the screen,
Replace the noisy line with the lines before and after it
Filtering technology is used. Generally, these techniques are
It is realized by ray and line delay. This file
The serial access memory that realizes the field delay is
Realized this line delay called field memory
Serial access memory is called line memory.
It An example of such a serial access memory is
For example, it was published on March 7, 1989 in Japan.
Patent Publication No. 64-59694 and July 1990
Japanese Patent Publication No. 2-1887989 published on the 24th
Has been described. [0006] In general, the above-mentioned file
When processing image data such as filtering
Serial access memo as shown in the above publication.
The processing is realized by using multiple
It In this way, a plurality of serial access memos
The use of a resin increases the mounting area and costs
Will increase. Means for Solving the Problems The above-mentioned problems are solved.
For this reason, the serial access memory of the representative invention
Is a memory in which multiple memory cells that store data are arranged.
A memory cell array and a first switch in this memory cell array.
First transfer register connected via a switch circuit,
This first transfer register via the second switch circuit
Data transfer with a second transfer register connected to
This is the transmitter, and the first and second switch circuits are ON.
Status, the second transfer register from the memory cell array
Data through the first transfer register to the
The first switch circuit is ON, the second switch circuit is
In the OFF state, for the first transfer from the memory cell array
The data transfer unit for transferring data to the register is provided.
It is a thing. Further, in order to solve the above-mentioned problems,
Another typical invention serial access memory of the invention is
1 clock signal and a second clock signal that follows it
Signal generating circuit for generating the signal and the first clock signal.
The first serial address that outputs data in response to the clock signal.
In response to the access memory section and its second clock signal
Second serial access memory unit to which data is input
And between the first and second serial access memories
Data from the connected, first serial access memory
To the second serial access memory after delaying for a predetermined period
And a delay circuit for giving it. In the serial access memory of the present invention, the above
Because of the configuration like this, multiple serial access
The function equivalent to the function realized by the memory is
It can be realized by connecting two transfer registers in series.
Wear. The serial access according to another invention of the present application.
The memory has the above-mentioned configuration,
Serial access memory can be easily integrated into a single chip.
And are possible. The preferred embodiments of the present invention will be described below with reference to the drawings.
Examples will be described. Same for common parts in each embodiment
Is attached. In each example, the explanation is easy to understand
The basic operation of the present invention is not directly related to
The memory control signal generating circuit and the like are omitted. First, the first embodiment of the present invention is shown in FIG.
While being explained. FIG. 1 shows a first embodiment of the present invention.
In the block diagram showing the configuration of the serial access memory
is there. The serial access memory of this embodiment is a memory
It has a memory cell array 101. Memory cell array
101 is a plurality of word lines WLi (i = 1 to n)
And a plurality of complementary bit line pairs B intersecting them.
Lk and bar BLk (k = 1 to m). Work
Drain WLi and bit line pair BLk and bar BLk
At the intersection of the
Molycell Qki (k = 1 to m, i = 1 to n)
They are connected together and arranged in the row and column directions. Each bit
The line pair BLk and bar BLk are sense amplifiers SAk.
(K = 1 to m), respectively. The memory cell array 101 has an X add
The response decoder 103 is connected. X address deco
The converter 103 is connected to the word line and is supplied from the outside.
The memory cell array 101 depending on the X address
Has the function of selecting the column. The input circuit 105 is input from the input terminal Din.
Write data that has been applied (write data)
Memory data via WDB, WDB
It is a circuit which inputs to the array 101. Y address decoder (for writing) 107
Decodes the Y address given from the outside and
Of the memory cell array 101 by the response signal YWi
It has the function of selecting rows. The selected row's
Write data bus pair WDB, bar WDB on memory cell
Data is entered. The transfer circuit 109 includes a plurality of transistor pairs.
It is composed of 109k and bar 109k. These
The transistor is an N-channel MOS transistor (NM
OS). This transistor pair 109k, bar 10
9k is write data bus pair WDB, bar WDB and write
Between the flip-flop WFk of the register 111
Is connected to the output YWk of the Y address decoder 107.
Therefore, an arbitrary pair is selected. This transfer circuit 109
Data bus vs. WDB, write data on bar WDB
Function to transfer data to the write register 111
It The write register 111 is used in the transfer circuit 10.
9 transistor pair 109k, connected to bar 109k
Flip-flop WFk (k = 1 to m)
Be done. This flip-flop WFk is connected in antiparallel
Consists of two inverters WINk and bar WINk
To be done. This write register 111 is write data
It has a function of storing (Write Data). The transfer circuit 113 includes a memory cell array 1
01 and the write register 111, and a plurality of
It consists of a transistor pair 113k and a bar 113k
Be done. These transistors are N-channel MOS transistors.
It is a transistor (NMOS). This transistor pair 1
13k and bar 113k have flip-flop WFk and
It is connected between the line pair BLk and the bar BLk.
This transfer circuit 113 stores the data in the write register 111.
Write data in response to the write control signal PWT
It has a function of transferring to the memory cell array 101. The memory cell array 101 further includes a read
Read out the read out data (Read Data)
A transfer circuit 115 for transferring to the transistor 117 is connected.
The transfer circuit 115 includes a plurality of transistor pairs 115k,
It consists of a bar 115k. These transistors
N-channel MOS transistor (NMOS)
It This transistor pair 115k and bar 115k are
Line pair BL, bar BL and first read register
It is connected between 117 flip-flop RFk and
The first read of the data read from the re-cell array 101
Transfer in response to the protrusion control signal PRT1. The first read register 117 is used to transfer data.
Connects to transistor pair 115k and bar 115k on path 115
By the following flip-flop RFk (k = 1 to m)
Composed. This flip-flop RFk is connected in antiparallel.
With the two inverters RInk and RInk connected
Consists of The first read register 117 is
Reading one column transferred by the read transfer circuit 115
Function to store data (ReadData)
It The transfer circuit 119 uses the first read data.
Bus pair RD1, bar RD1 and first read register 1
17 and a plurality of transistor pairs 119
k, bar 119k. These transitions
The star is an N-channel MOS transistor (NMOS)
Is. This transistor pair 119k, bar 119k
Is the flip-flop RFk and the first read data bus
It is connected between the pair RD1 and the bar RD1. This transfer times
The path 119 stores the read data stored in the first read register 117.
The read data is the first Y address decoder (Read)
In response to the address signal YR1k from the first 121,
Data pair to the master data bus RD1 and RD1. First read data bus pair RD1, bar R
The first output circuit 123 is connected to D1. This first
Output circuit 123 of the first read register 117
The read data transferred from the first output terminal DOUT
Output to 1. Further, the serial access memory of the present invention
Then, the transfer circuit 125 is added to the first read register 117.
Are connected. This transfer circuit 125 has a second reading
Memory cell array 10 in response to output control signal PRT2
The data read from 1 is the first read register 1
Transfer to the second read register 127 via 17
Have the function of This transfer circuit 125 has a plurality of transitions.
It consists of a star pair 125k and a bar 125k. these
Is a N-channel MOS transistor
(NMOS). This transistor pair 125k,
-125k is the flip-flop of the first read register 117.
Of the flip-flop RFk and the second read register 127.
The memory cell connected between the flip-flop RF'k and the memory cell
The data read from the memory cell Qki of the array 101
Data in response to the second read control signal PRT2
It The second read register 127 is used to transfer data.
Connected to transistor pair 125k and bar 125k on path 125
By the flip-flops RF'k (k = 1 to m) to be continued
Consists of This flip-flop RF'k is anti-parallel
Two inverters RIn'k and a bar RI connected to
n'k. This second read register
127 is 1 transferred by the read transfer circuit 125
Stores read data for columns (Read Data)
Have the function of The transfer circuit 129 uses the second read data.
Bus pair RD2, bar RD2 and second read register 1
27 and a plurality of transistor pairs 129
k, bar 129k. These transitions
The star is an N-channel MOS transistor (NMOS)
Is. This transistor pair 129k, bar 129k
Is the flip-flop RF'k and the second read data buffer.
It is connected between the pair RD2 and the bar RD2. This transfer
The circuit 129 stores in the second read register 127.
The read data is transferred to the second Y address decoder (Rea
d) second in response to the address signal YR2k from 131
Of the read data bus pair RD2 and RD2. Second read data bus pair RD2, bar R
The second output circuit 133 is connected to D2. This second
Output circuit 133 of the second read register 127
Read data transferred from the second output terminal DOUT
Output to 2. Next, the present invention will be made easier to understand.
For the sake of simplicity, refer to FIG. 2 in which the characteristic parts of the present invention are schematically shown.
While being explained. In this case, the Syria shown in Figure 1
The same parts as those of the access memory
Has been. As shown in FIG. 2, the cereal of the present invention
In the access memory, the first read register 117 and
Is connected in series with the second read register 127.
It In this serial access memory, for the second read
When data is input to the register 127, FIG.
As shown in, the first read control signal PRT1
In response, the transfer circuit 115 is turned on, and the second read control is performed.
In response to the signal PRT2, the transfer circuit 127 is turned on,
The data read from the memory cell array 101 is the first
Second read register via read register 117
Data 127. On the other hand, the first read register
When data is input to 115, it is shown in FIG.
In response to the first read control signal PRT1
The transfer circuit 115 is turned on, and the second read control signal PR
In response to T2, the transfer circuit 127 turns off, and the memory
Data read from the memory array 101 is the first read
Is transferred to the register 117 for use. Next, the serial access memory of this embodiment
For the detailed operation of, refer to the timing charts of FIG. 3 and FIG.
Described with reference. In this case, make the explanation easier to understand
Therefore, the write and read operations are described separately.
It For the write operation, refer to the timing chart of FIG.
The read operation is explained in the timing chart of FIG.
Will be described with reference to. Write operation and read operation
Operating independently of each other
It is also possible to operate the process memory at the same time. That
Such operations can be easily performed by considering the following explanation.
I can understand. Description is for ease of understanding
It is divided into periods. This serial access memory has a clock
It operates in response to signal CLK. This clock signal CL
K is the clock signal generation frequency as shown in FIG.
Output by path 500. This clock signal generation circuit
Reference numeral 500 denotes a plurality of odd-numbered inverters 501 1 to 501.
Inverter in which j (j: odd number of j ≧ 3) is connected in series
A part 501, an inverter 503, and a gate circuit 505.
It is composed of The output of the inverter 501j is the inverter
Connected to the input of the data source 501 1 and the input of the inverter 503.
To be done. The output Po of the inverter 503 is the gate circuit 50.
5 is connected to one input. The other side of the gate circuit 505
The clock control signal CLE is applied to the input of. This clock signal generating circuit 500 has a simple
The operation is shown in the timing chart of FIG.
As shown in this timing chart, clock control
The logic level of the control signal CLE is HIGH LEVEL (hereinafter
Below, "H") (period ta-tb),
The clock signal CLK is output from the clock signal generation circuit 500.
Is output. First, data is input from the outside using FIG.
If so, the operation will be described. <Period t1> Write data (Write
Data) d1 is input circuit 105 from input terminal DIN
Entered in. This write data d1 is input to the input circuit 1
From 05 to the data bus pair WD for writing and the bar WD
Be done. At this time, the Y address decoder (Write) 10
The address signal YW1 from 7 is "H".
Then, the transistor pair 1091 and bar 1 of the transfer circuit 109
091 is turned on and the write data d1 is the register for writing.
It is input to the flip-flop WF1 of the data 111. <Period t2> Similarly, write data
d2 is a data bus WDB for writing from the input circuit 105,
Given to bar WDB. At this time, the address signal YW2
Is "H", the transistor pair 10 of the transfer circuit 109 is
92 and bar 1092 are turned on, and write data d2 is written.
Input to the flip-flop WF2 of the register 111 for
Be done. <Period t3> Similarly, write data
d3 is a data bus WDB for writing from the input circuit 105,
Given to bar WDB. At this time, the address signal YW3
Is "H", the transistor pair 10 of the transfer circuit 109 is
93 and bar 1093 are turned on, and write data d3 is written.
Input to flip-flop WF3 of register 111 for
Be done. <Period t4> Thereafter, the writing is sequentially performed in the same manner.
The embedded data dm is transferred from the input circuit 105 to the write data buffer.
It is given to WD and bar WD. At this time, the address signal
Since YWm is "H", the transistor of the transfer circuit 109
Pair 109m, bar 109m turned on, write data d
m is a flip-flop WFm of the write register 111
Entered in. <Period t5> In the X address decoder 103
A desired word line WLa (1 ≦ a ≦ n) is selected.
Be done. In this case, the potential level of the word line WLa
Becomes "H". At the same time, the theory of the write control signal PWT
Logic level becomes "H" level, and the transfer circuit 113
Register pair 1131, bar 1131 to 113m, bar 11
3m turns on. As a result, the write register 111
The write data d1 to dm stored in the
The memory cells Q1, a to Qm connected to the line WLa
Written to a. As described above, the memory cell array 101
Write data is written in the memory cell inside. Next, referring to FIG. 4, the serial address of this embodiment will be described.
The read operation of the access memory is described. in this case,
From the first and second output terminals DOUT1 and DOUT2
The operation of outputting read data is shown. <Period t1> In the X address decoder 103
A desired word line WLa (1 ≦ a ≦ n) is selected.
Be done. In this case, the potential of this word line WLa is "
H ″. This word line WLa will be the second
Read out from the output terminal DOUT2 of
Connected to the memory cell group in which the data is stored. At this time, the memory cell connected to the word line WLa is connected.
Data stored in memory cells C1, a to Cm, a
Is a bit line pair BL to which each memory cell is connected.
1, bars BL1 to BLm, and bar BLm.
The data on the bit line pair is
It is amplified by SA1 to SAm. <Period t2> Next, the first and second reading
Then, the logic level of the control signals PRT1 and PRT2 becomes "H".
Become. Therefore, the transistor pair 115 of the transfer circuit 115 is
1, bar 1151-115m, bar 115m is turned on,
Transistor pair 1251 of transmission circuit 125, bar 1251-
125m and 125m turn on. As a result, in the period t1, the sense amplifier is
Bit line pair BL amplified by the groups SA1 to SAm
1. The data on bars BL1 to BLm and bar BLm are
The data is transferred to the read register 117 of No. 1 at once. Furthermore
Then, the data passes through the first read register 117.
Therefore, it is input to the second read register 127. <Period t3> Next, the X address decoder 1
Desired word line WLb (1 ≦ b ≦ n)
To be selected. In this case, the potential of this word line WLb
Becomes "H". This word line WLb is
Read that is about to be read from the first output terminal DOUT1
Connected to memory cells that store data
It At this time, the memory cell connected to the word line WLb is connected.
Data stored in memory cells C1, b to Cm, b
Is a bit line pair BL to which each memory cell is connected.
1, bars BL1 to BLm, and bar BLm.
The data on the bit line pair is
It is amplified by SA1 to SAm. <Period t4> Next, the first read control signal
No. 2 PRT1 logic level becomes "H"
The logic level of the control signal PRT2 becomes "L". Therefore,
Transistor pair 1151 of transfer circuit 115, bar 1151
~ 115m, the bar 115m is turned on, and the transfer circuit 125
Transistor pair 1251, bar 1251-125m, 12
5m is turned off. As a result, in the period t1, the sense amplifier is
Bit line pair BL amplified by the groups SA1 to SAm
1. The data on bars BL1 to BLm and bar BLm are
It is input to one read register 117 at a time. <Period t5> Next, the first Y address decoding
Address signal YR11 from the reader (Read) 121
Becomes “H”, and the transistor pair 11 of the transfer circuit 119
91 and bar 1191 turn on. Therefore, for the first lead
Stored in flip-flop RF1 of register 117
The read data present is the first read data bus pair R
Transferred to the output circuit 123 via D1 and RD1
It Then, from the output circuit 123 to the output terminal DOUT
The data D1 is output to 1. Similarly, the second Y address decoder (Re
ad) The address signal YR21 from 131 becomes "H".
, The transistor pair 1291 of the transfer circuit 129, bar 1
291 turns on. Therefore, the second read register 1
Readings stored in 27 flip-flops RF'1
The output data is the second read data bus pair RD2,
-Is transferred to the output circuit 133 via RD2. That
From the output circuit 133 to the output terminal DOUT2.
Data D1 'is output. <Period t6> Next, the first Y address decoding
Address signal YR12 from the reader (Read) 121
Becomes “H”, and the transistor pair 11 of the transfer circuit 119
92 and bar 1192 turn on. Therefore, for the first lead
Stored in flip-flop RF2 of register 117
The read data present is the first read data bus pair R
Transferred to the output circuit 123 via D1 and RD1
It Then, from the output circuit 123 to the first output terminal D
Data D2 is output to OUT1. Similarly, the second Y address decoder (Re
ad) The address signal YR22 from 131 becomes "H".
, The transfer circuit 129 transistor pair 1292, bar 1
292 turns on. Therefore, the second read register 1
Readings stored in 27 flip-flops RF'2
The output data is the second read data bus pair RD2,
-Is transferred to the output circuit 133 via RD2. That
From the output circuit 133 to the second output terminal DOUT2.
The data D2 'is output to. Thereafter, as shown in the periods t7 and t8,
Similar to the operation described above, whether the first output terminal DOUT1
Data D3, D4 ... Dm are output from the second output
Data D3 ', D4' ... Dm 'from the terminal DOUT2
Are sequentially output. As described above, from the memory cell array
The read data is sequentially output from the two output terminals
It Here, in general, the data is read from the memory cell array.
The generated data is read out from the two output terminals.
Real access memory (called 2-port memory)
Then, the following can be considered. First, each book is placed in close proximity.
Built-in data bus connected to common input circuit
Two serial access memories have the same address memory.
Memory cell to select the same write data
To each independent read operation.
Data stored in memory cells at different addresses.
Serial output from each independent output circuit
Access memory. Second, the two read registers are memory
Parallel to the bit line pair of the cell array via the transfer circuit
Connected serial output that alternately outputs read data
Access memory. Serial access according to the first embodiment of the present invention
Compare the memory with the first serial access memory described above
Then, in the first serial access memory, two serial
A 2-port memory is realized by the al access memory.
On the other hand, the serial access of the first embodiment of the present invention
Memory has 2 ports with a single serial access memory
Since the memory can be realized, the first embodiment of the present invention can be realized.
The serial access memory of the embodiment is the first serial access memory.
The occupied area is much smaller than the memory. Also,
Since the occupied area is small, the wiring length of each signal line is also short.
Therefore, higher operating speed can also be expected. Furthermore, according to the invention
According to the serial access memory of the first embodiment, 2 ports
Implemented by a single serial access memory
Therefore, the power consumption can be significantly reduced. Wiring is provided in the peripheral portion of the read register.
Since the transfer circuits are densely packed, the integration of memory cells
The more you proceed, the more freedom you have to design around it.
The degree becomes smaller. However, the second serial access memo
This is because the read registers are arranged in parallel in
Since the wiring length connecting each becomes longer, as integration progresses
It becomes difficult to design the wiring in the peripheral portion. Or around
In order to secure design flexibility in
In the column direction (direction parallel to the Y address decoder)
There is no choice but to expand. This means integration of semiconductor memory devices
Will be hindered. On the other hand, the system of the first embodiment of the present invention
The real access memory has two read registers directly
Since the configuration is connected in columns, the wiring connected to each
Is significantly shorter than the second serial access memory
It Therefore, freedom of design around the read register
The degree of reliability is ensured, and the
Integration of the sides can also be achieved. As described above, the Syria of the first embodiment of the present invention
Access memory, multiple serial access
The same function as the function realized by the memory is
It can be realized with an alaccess memory and has a high degree of integration.
And low cost serial access memory
You can Next, a second embodiment of the present invention will be described with reference to FIG.
While being explained. FIG. 6 shows a system according to the second embodiment of the present invention.
FIG. 3 is a configuration block diagram showing a configuration of a real access memory.
It In this case, the serial access memory of the first embodiment
The same reference numerals are given to the same elements as and their explanations are omitted.
Abbreviated. Serial access memo of the second embodiment
The configuration is basically the serial access of the first embodiment.
It is almost the same as the memory. The serial access of the first embodiment
The difference from the process memory is that the first and second embodiments of the first embodiment are different.
Common read Y address decoders 121 and 131
Replaced by Y address decoder (Read) 601
That is the point. This Y address decoder (Read) 60
The configuration of 1 and its function are as follows:
The configuration of the coder 121, 131 is the same. That is, the serial access method of this embodiment is
In memory, from Y address decoder (Read) 601
The output address signal YRk (1 ≦ k ≦ m) is transferred.
Circuit 119 transistor pair 119k, bar 119k
Gate electrode and transistor pair 129 of transfer circuit 129
k, bar 129k applied to the gate electrode. Next, referring to the timing chart of FIG.
An example serial access memory read operation is described.
It In this case, the first and second output terminals DOUT1, D
Operation in which read data is output from OUT2
Is shown. In this case, as shown in the time chart of FIG.
The operation of the serial access memory of the first embodiment
The serial access of this embodiment
The operation of the memory can be easily understood. Therefore, the period t1
The description of t4 is omitted by referring to the description of FIG.
Here, the operation after the period t5 will be described. <Period t5> Y address decoder (Rea
d) The address signal YR1 from 601 becomes "H",
Transistor pair 119 of transfer circuit 119, bar 1191
And transistor pair 1291 of transfer circuit 129, bar 1
291 turns on. Therefore, the first read register 1
Reading stored in the flip-flop RF1 of 17
Data is the first read data bus pair RD1, bar
While being transferred to the output circuit 123 via RD1,
Flip-flop RF ′ of read register 127 of 2
The read data stored in 1 is for the second read.
Output circuit 13 via data bus pair RD2 and bar RD2
3 is transferred. And output from the output circuit 123
Data D1 is output to the terminal DOUT1 and its output circuit
The data D1 'is output from the 133 to the output terminal DOUT2.
Be done. <Period t6> Next, the Y address decoder
(Read) Address signal YR2 from 601 is "H"
The transfer circuit 119 transistor pair 1192,
ー 1192 is turned on, the transistor pair of transfer circuit 129
1292 and bar 1292 turn on. Therefore, the first Lee
Stored in the flip-flop RF2 of the register 117 for read
Read data is the first read data bus
It is transferred to the output circuit 123 via the pair RD1 and the bar RD1.
And flip the second read register 127.
The read data stored in the flop RF'2 is
Via the second read data bus pair RD2 and bar RD2
Are transferred to the output circuit 133. And its output circuit
Data D2 is output from 123 to the first output terminal DOUT1.
Output from the output circuit 133 to the second output terminal DOU
Data D2 'is output to T2. Thereafter, as shown in the periods t7 and t8,
Similar to the operation described above, whether the first output terminal DOUT1
Data D3, D4 ... Dm are output from the second output
Data D3 ', D4' ... Dm 'from the terminal DOUT2
Are sequentially output. As described above, from the memory cell array
The read data is sequentially output from the two output terminals
It In the serial access memory of the second embodiment
According to the serial access method of the first embodiment described above,
In addition to the effect of memory, Y address decoding for read
Because the data is shared, serial access that occupies a small area
Memory can be realized. The serial access of this second embodiment
As a field to which process memory is applied, the time axis is not always
It is not necessary to correct the
Low quality TVs, VTRs, etc. that can be accessed are considered. Next, a third embodiment of the present invention will be described with reference to FIG.
While being explained. FIG. 8 shows the system of the third embodiment of the present invention.
FIG. 3 is a configuration block diagram showing a configuration of a real access memory.
It In this case, in order to facilitate understanding of the description of the present embodiment.
In addition, the above-mentioned elements are appropriately blocked and shown schematically.
Has been. And the same elements as the elements mentioned above are the same
Is attached and the description thereof is omitted. Serial access memo of the third embodiment
The configuration is basically the serial access of the second embodiment.
It is almost the same as the memory. Serial access of the second embodiment
The difference from the access memory is that the first read data bus pair R
D1, the first output circuit 123 between the bar RD1 and the first
The delay circuit 800 is connected. This delay
The circuit 800 uses the data read on the read data bus.
When transferring data, a device that delays the transfer for a predetermined period
Has the ability. This delay circuit 800 has the same structure as described above.
Instead of the arrangement, the second read data bus pair RD2,
Even if it is arranged between the bar RD2 and the second output circuit 133.
Good. In other words, this delay circuit
If it is connected between the data bus pair and the output circuit
Yes. This delay circuit 800 is shown in FIG.
So that the read data can be delayed by a predetermined bit
Flip-flop FF1 to flip-flop FFx
It is connected in series. 2-bit delay when X = 2
Occurs, and when X = 3, there is a 3-bit delay.
Become. This delay circuit 800 is the same as the clock signal CLK.
Works in anticipation. Next, refer to the timing chart of FIG.
Then, the read operation of the serial access memory of this embodiment is performed.
The work is explained. In this case, if a 3-bit delay occurs
When (X = 3), the first and second output terminals DOUT1, D
Operation in which read data is output from OUT2
Is shown. In this case, the time chart of FIG. 4 and FIG.
The serial access methods of the first and second embodiments shown in FIG.
With reference to the description of the operation of the memory,
The operation of the serial access memory can be easily understood. Servant
For the explanation of the periods t1 to t4, refer to the explanation of FIGS. 4 and 7.
It is omitted by considering, and here, after the period t5
The operation is explained. <Period t5> Y address decoder (Rea
d) The address signal YR1 from 601 becomes "H",
Transistor pair 119 of transfer circuit 119, bar 1191
And transistor pair 1291 of transfer circuit 129, bar 1
291 turns on. Therefore, the first read register 1
Reading stored in the flip-flop RF1 of 17
Data is the first read data bus pair RD1, bar
It is transferred to the delay circuit 800 via RD1. And
The data is stored in the flip-flop FF1. same
Sometimes, the flip-flop of the second read register 127 is
The read data stored in the RF'1 is the second
Output via read data bus pair RD2 and bar RD2
It is transferred to the circuit 133. Then, the output circuit 133
The data D1 'is output from the output terminal DOUT2. <Period t6> Next, the Y address decoder
(Read) Address signal YR2 from 601 is "H"
The transfer circuit 119 transistor pair 1192,
ー 1192 is turned on, the transistor pair of transfer circuit 129
1292 and bar 1292 turn on. Therefore, the first Lee
Stored in the flip-flop RF2 of the register 117 for read
Read data is the first read data bus
It is transferred to the delay circuit 800 via the pair RD1 and the bar RD1.
Be done. At this time, it is stored in the flip-flop FF1.
Data is flip-flop F in synchronization with the clock signal.
It is input to F2 and also to flip-flop FF1.
The data read from the lip flop RF2 is input.
Be done. At the same time, the flag of the second read register 127 is
Readout data stored in the lip flop RF'2
The second read data bus pair RD2, bar RD2
Is transferred to the output circuit 133 via the. And that out
Data D from the output circuit 133 to the second output terminal DOUT2
2'is output. <Period t7> Next, the Y address decoder
(Read) Address signal YR3 from 601 is "H"
The transfer circuit 119 transistor pair 1193,
ー 1193 turns on, and the transistor pair of the transfer circuit 129
1293 and bar 1293 turn on. Therefore, the first Lee
Stored in the flip-flop RF3 of the register 117 for read
Read data is the first read data bus
It is transferred to the delay circuit 800 via the pair RD1 and the bar RD1.
Be done. At this time, it is stored in the flip-flop FF1.
Data is flip-flop F in synchronization with the clock signal.
The data is input to F2 and the result is input to the flip-flop FF2.
The stored data flips in synchronization with the clock signal
It is input to the flop FF3. At the same time, flip floppy
The data read from the flip-flop RF3 to the flip-flop FF1.
Data is input. Along with that, the second lead resist
Stored in the flip-flop RF'3 of the data 127
The read data is the second read data bus pair RD.
2, transferred to the output circuit 133 via the bar RD2.
Then, from the output circuit 133 to the second output terminal DOU
Data D3 'is output to T2. <Period t8> Next, the Y address decoder
(Read) Address signal YR4 from 601 is "H"
The transfer circuit 119 transistor pair 1194,
ー 1194 turns on, the transistor pair of transfer circuit 129
1294 and bar 1294 turn on. Therefore, the first Lee
Stored in the flip-flop RF4 of the register 117 for read mode.
Read data is the first read data bus
It is transferred to the delay circuit 800 via the pair RD1 and the bar RD1.
Be done. At this time, it is stored in the flip-flop FF1.
Data is flip-flop F in synchronization with the clock signal.
The data is input to F2 and the result is input to the flip-flop FF2.
The stored data flips in synchronization with the clock signal
It is input to the flop FF3 and is input to the flip flop FF3.
The stored data is transferred to the output circuit 123.
It At the same time, flip-flop FF1 is flip-flop
The data read from the RF4 is input. With that
Both are flip-flops of the second read register 127.
The read data stored in the RF'4 is the second read data.
Output via read data bus pair RD2 and bar RD2
It is transferred to the circuit 133. Then, the output circuit 123
The data D1 from the first output terminal DOUT1
From the output circuit 133 to the second output terminal DOUT2.
Data D4 'is output to. Thereafter, the period t9, t10, ...
As described above, the first output terminal DO
Data D2, D3 ... Dm-3 are output from UT1.
From the second output terminal DOUT2 to the data D5 ', D
6 '... Dm' are sequentially output. like this
The data output from the second output terminal DOUT2.
Data delayed by 3 bits from the first output terminal DO
It is output from UT1. As described above, from the memory cell array
The read data is sequentially output from the two output terminals
It According to this embodiment, the above-mentioned first and second
In addition to the effects of the embodiment, delay the data from one output terminal.
Data output variation
More users and more choices for users. Next, referring to FIG. 11, a fourth embodiment of the present invention will be described.
It is explained while illuminating. FIG. 11 shows a fourth embodiment of the present invention.
Block diagram showing the serial access memory configuration
Is. In this case, it is easy to understand the description of the present embodiment.
Therefore, the above-mentioned elements are appropriately blocked and
It is shown. And, for the same element as the above-mentioned element,
The same reference numerals are given and the description thereof is omitted. Serial access memory according to the fourth embodiment
Then, the delay time of the serial access memory of the third embodiment is
The delay bypass circuit 1100 is connected to the path 800.
It This delay bypass circuit 1100 is shown in FIG.
, Transistors 1101, 1102, 1
It is composed of 103 and an inverter 1104. This
These transistors are N-type MOS transistors.
This transistor 1101 is connected in parallel with the delay circuit 800.
First read bus pair RD, bar RD and first output circuit 1
It is connected between 23 and. In addition, the transistor 1102
Is a flip-flop FF1 and a first read bus pair RD
1, and is connected between the bar RD1. Also, Transis
1103 is a flip-flop FFx and a first output circuit
It is connected to 123. This transistor 1101
The delayed bypass signal PBP is applied to the control electrode of the.
Also, for both control electrodes of the transistors 1102 and 1103,
The delayed bypass signal PBP through the inverter 1104.
Is given. This delay bypass circuit 1100 has a delay
Control the delay of data transfer in response to the bypass signal PBP
It has a function to do. Serial access memo of the fourth embodiment
In this case, when the delayed bypass signal PBP becomes “H”,
The transistor 1101 is turned on and the transistor T1102,
1103 is turned off. In this case, the data on the lead bus
Data is bypassed through the delay circuit 800, and the first output circuit
123 is transferred to. That is, the delay effect disappears. On the other hand, the delayed bypass signal PBP is LOW.
When LEVEL (hereinafter referred to as "L"), the transistor
1101 is turned off, and transistors 1102 and 1103
Turns on. Therefore, the read data is the delay circuit 800.
Since the data is transferred via the Internet, the description of the above-mentioned third embodiment will be omitted.
So that the output of the first output terminal DOUT1 is the second output
The output of the terminal DOUT2 is delayed by n bits. According to the serial access memory of this embodiment,
For example, in addition to the effects of the above-described embodiment, the above-mentioned second or
Is the function of the serial access memory of the third embodiment external?
Selected by the delayed bypass signal PBP given from
And become possible. Next, referring to FIG. 13, a fifth embodiment of the present invention will be described.
It is explained while illuminating. FIG. 13 shows the fifth embodiment of the present invention.
Block diagram showing the serial access memory configuration
Is. In this case, it is easy to understand the description of the present embodiment.
Therefore, the above-mentioned elements are appropriately blocked and
It is shown. And, for the same element as the above-mentioned element,
The same reference numerals are given and the description thereof is omitted. Serial access memo of this fifth embodiment
Is the second of the serial access memory of the fourth embodiment.
The read data bus pair RD2 and the bar RD2 have a third and
And the delay circuit 800 ′ described in the fourth embodiment.
A pass circuit 1100 'is added. This delay times
The configurations of the path 800 ′ and the delay bypass circuit 1100 ′ are
Similar to the delay circuit 800 and the delay bypass circuit 1100.
It is a composition. These circuits use the delayed bypass signal PBP '.
Controlled by. Operation of serial access memory of this embodiment
Is easy with reference to the above-mentioned third and fourth embodiments.
Can understand. According to the serial access memory of this embodiment
Thus, in addition to the effects of the above-described embodiment, the first and second outputs
Read data from the terminal to a signal given from the outside
It becomes possible to delay more arbitrarily. Next, referring to FIG. 14, a sixth embodiment of the present invention will be described.
It is explained while illuminating. FIG. 14 shows a sixth embodiment of the present invention.
Block diagram showing the serial access memory configuration
Is. In this case, it is easy to understand the description of the present embodiment.
Therefore, the above-mentioned elements are appropriately blocked and
It is shown. And, for the same element as the above-mentioned element,
The same reference numerals are given and the description thereof is omitted. In this embodiment, the delay selection circuit 1400 is the first
1 read data bus pair RD1, bar RD2 and first output
It is connected to the force circuit 123. This delay selection times
Path 1400 has multiple transitions, as shown in FIG.
It is composed of a star. These transistors are
1 read data bus RD1, bar RD1 and first output
Between the circuit 123 and each of the flip-flops FF1 to F
It is arranged between Fx and the first output circuit 123, respectively.
The delay selection signals PBP1 to PBPx are given respectively.
Be done. Depending on the logic level of each delay selection signal,
ON / OFF of the resistor is controlled. These tigers
The transistor is an N-channel type MOS transistor.
It According to the serial access memory of this embodiment
For example, in addition to the effects of the above-described embodiment, the delay selection signal PBP
It is possible to select any delay bit from 1 to PBPx
Because it is. The delay of the data output from the first output terminal
It can be set appropriately. Next, a seventh embodiment of the present invention will be described with reference to FIG.
It is explained while illuminating. FIG. 16 shows a seventh embodiment of the present invention.
Block diagram showing the serial access memory configuration
Is. In this case, it is easy to understand the description of the present embodiment.
Therefore, the above-mentioned elements are appropriately blocked and
It is shown. And, for the same element as the above-mentioned element,
The same reference numerals are given and the description thereof is omitted. In this embodiment, the construction of the sixth embodiment described above is used.
In addition, the delay selection circuit 14 of the sixth embodiment described above
The delay selection circuit 1400 ′ having the same configuration as that of the second
Read data bus pair RD2, bar RD2 and second output circuit
It is connected to the path 133. This delay selection circuit 1
The detailed structure of 400 'can be easily understood by referring to FIG.
I can understand. These transistors are the second read data
Of the bus RD2, the bar RD2 and the second output circuit 133.
And between the flip-flops FF1 'to FFx' and the second
And the output circuit 133 of the
Delay selection signals PBP1 'to PBPx' are provided. each
Depending on the logic level of the delay selection signal,
ON or OFF is controlled. These transistors
Is an N-channel MOS transistor. According to the serial access memory of this embodiment,
For example, in addition to the effects of the above-described embodiment, the delay selection signal PBP
1-PBPx and PBP1'-PBPx '
Because it is possible to select the total bit. First and second output
Set the delay of the data output from the terminal appropriately.
Is possible. Next, an eighth embodiment of the present invention will be described with reference to FIG.
It is explained while illuminating. FIG. 17 shows the eighth embodiment of the present invention.
Block diagram showing the serial access memory configuration
Is. In this case, it is easy to understand the description of the present embodiment.
Therefore, the above-mentioned elements are appropriately blocked and
It is shown. And, for the same element as the above-mentioned element,
The same reference numerals are given and the description thereof is omitted. In this embodiment, the system of the sixth embodiment described above is used.
The delay selection circuit 1400 of the real access memory has a delay selection circuit.
Address for delay control that outputs selection signals PBP1 to PBPx
A decoder 1700 is provided. For this delay control
The address decoder 1700 controls the delay bit.
Decode addresses AA1 to AAx given externally for
To output the delay selection signals PBP1 to PBPx
Have. According to this embodiment, the effect of the above-mentioned embodiment
In addition, the delay selection signal is generated by an external address.
Therefore, the number of delay bits can be set appropriately with a small number of external signals.
can do. Next, referring to FIG. 18, a ninth embodiment of the present invention will be described.
It is explained while illuminating. FIG. 18 shows a ninth embodiment of the present invention.
Block diagram showing the serial access memory configuration
Is. In this case, it is easy to understand the description of the present embodiment.
Therefore, the above-mentioned elements are appropriately blocked and
It is shown. And, for the same element as the above-mentioned element,
The same reference numerals are given and the description thereof is omitted. In this embodiment, the system of the seventh embodiment described above is used.
Real access memory delay selection circuits 1400 and 140
0'to the delay selection signal P described in the above eighth embodiment.
Delay control address decoder that outputs BP1 to PBPx
1700 and a delay control adapter having a function equivalent thereto.
A dress decoder 1700 'is provided. This delay
The control address decoder 1700 'controls the delay bit.
Addresses AA1'-A given from the outside to control
Decode Ax 'to obtain delay select signals PBP1'-PBPx'
Has the function of outputting. According to this embodiment, the effect of the above-mentioned embodiment
In addition, the delay selection signal is generated by an external address.
Therefore, the number of delay bits can be set appropriately with few external signals.
can do. Next, a tenth embodiment of the present invention will be described with reference to FIG.
Described with reference. FIG. 19 shows a tenth embodiment of the present invention.
Partial timing showing the operation of the serial access memory of the embodiment
It is a long chart. In this case, understanding the description of the present embodiment
Elements that are identical to
The reference numeral 1 is given and the description thereof is omitted. Real
The basic operation of the embodiment is the same as that of the first embodiment shown in FIG.
See the operation of the serial access memory and its description.
It is easy to understand, so the explanation is omitted here.
It In this embodiment, the first read control signal P
RT1 and the second read control signal PRT2 are given
Is different from that of the first embodiment.
It That is, in the period t2, the first read
Only the control signal PRT1 becomes "H", and the read data
Is the first read register from the memory cell array 101
It is transferred to 117 and stored. And then the period
At t3, only the second read control signal PRT2 is "
H ”and stored in the first read register 117
The read data being read is the second read register 127
Transferred to. According to this embodiment, the data transfer efficiency is improved.
Serial access memory with good operating margin.
Mori can be realized. Next, an eleventh embodiment of the present invention will be described.
It The configuration of the serial access memory of this embodiment is basically
The same as the configuration of the serial access memory of the first embodiment
Is. In this embodiment, the serial address of the first embodiment is used.
Access to the first read register 117 of the access memory.
Inverter R that forms a flip-flop RFk and a bar RFk
Ink, Bar RInk dimensions and second lead
Register 127 flip-flop RFk, bar RF
of the inverter RIn'k and the bar RIn'k that compose k
And the dimension is different. That is, the inverter RInk and the bar RI
P-channel MOS transistor forming nk
(Assuming PMOS) and N-channel MOS transistor
The dimension of the star (which is NMOS) is the inverter
RIn'k, PMOS and N forming RIn'k
It is smaller than the MOS dimension. According to this embodiment, the data transfer efficiency is improved.
Serial access memory with good operating margin.
Mori can be realized. Next, a twelfth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. 21 and 22. Figure 20, Figure
21 and 22 show the serial access device of the twelfth embodiment of the present invention.
It is a configuration block diagram showing a configuration of a main part of a process memory.
In this case, in order to facilitate understanding of the description of the present embodiment,
The above-mentioned elements are appropriately divided into blocks and are shown schematically.
There is. And, the same symbols are attached to the same elements as the above-mentioned elements.
No., and its description is omitted. In this embodiment, as shown in FIG.
Second read register 127 and a power supply for supplying a potential to it.
Resistors R1 and R2 are arranged between the source line VDD and the source line VDD.
In addition, as shown in FIG. 21, the first read register
Resistors R3 and R4 are provided between 117 and the power supply line VDD
Has been. Also, as shown in FIG. 22, the first and the second
2 read registers 117 and 127 and power supply line VDD
And resistors R1, R2, R3, and R4 are provided between
Has been. According to this embodiment, the data transfer efficiency is improved.
Serial access memory with good operating margin.
Mori can be realized. Next, a thirteenth embodiment of the present invention will be described with reference to FIG.
Described with reference. FIG. 23 shows a thirteenth embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. In the present embodiment, the first or second lead record is used.
Flip-flop R forming the transistors 117 and 127
Fk, bar RFk, RF'k, and bar RF'k are shown in FIG.
Clocked inverter CRINK,
-CRInk, CRIn'k Bar CRIn'k
Has been. These clocked inverters have control signals
It is controlled by φ1 and φ2. According to this embodiment, the data transfer efficiency is improved.
Serial access memory with good operating margin.
Mori can be realized. As described above, the read registers can be connected in series.
Various embodiments that realize a 2-port memory by
Revealed In addition, below is the first serial access memo.
And a second serial access memory via a delay circuit.
Various two-port memory realized by connecting
Examples will be described. First, the fourteenth embodiment of the present invention is shown in FIG.
Described with reference. FIG. 24 shows a fourteenth embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. The serial access of this example
The process memory is the first serial access memory unit 240.
0A and the second serial access memory unit 2400B
It consists of The first serial access memory unit
To the element which has the same function as the above-mentioned element of 2400A
Has an "A" at the end of the above code, and its detailed
The description is omitted. This first serial access
See FIG. 25 for the detailed configuration of the memory unit 2400A.
Is easier to understand. Also, the second serial access memory unit 2
To the element which has the same function as the above-mentioned element of 400B
Is added with "B" at the end of the above code, and its detailed
The description is omitted. This second serial access
See FIG. 26 for the detailed configuration of the memory unit 2400B.
Is easier to understand. In the serial access memory of this embodiment,
The read data of the first serial access memory unit 2400A
Databus pair RDA, bar RDA and second serial access
The write data bus pair WDB and bus of the memory section 2400B
-WDB is connected to the delay circuit 2403. This delay circuit 2403 is the first serial
The data read from the access memory unit 2400A
The second serial access memory 24 is delayed for a predetermined period.
00B write data bus pair WDB ', to bar WDB'
It has a transfer function. Need for delay by this delay circuit
The sex will be described later. Specific circuit configuration of the delay circuit 2403
Is shown in FIG. This delay circuit 2403
Transistor connected to data bus pair RDA, bar RDA
Star pair 2701, 2702 and write data bus pair WD
B, a transistor pair 2703 connected to WDB,
2704, a pair of transistors 2701 and 2702 and a transistor
Connected between the pair of transistors 2703 and 2704,
Consists of a burner 2705 and an inverter 2706.
Flip-flop DDF and logic level of control signal PY
To reverse the transistor pair 2703 and 2704
It is composed of an inverter 2707 that supplies the electrodes. This
These transistors are N-channel MOS transistors
It is Read / write shared Y address decoder
2401 is an external address A0, bars A0-An, bars
An is decoded, and address signals YRA1 to YRAn and
The dress signals YWB1 to YWBn are output. These a
Address signal YRAk and address signal YWBk are equivalent
This is a logic level signal. Thereby, the transfer circuit 119A
The desired transistor pair is turned on from the transistor pair
At the same time, from the transistors of the transfer circuit 108B,
The transistor pair corresponding to the desired transistor pair
Turn on. This read / write shared Y address deco
The pre-charger 2401 is precharged as shown in FIG.
P-channel type MOS transistor to which signal PR is given
(Hereinafter referred to as PMOS) PT1 to PTm and the inverter
Data In1 to Inm, external address A0, bar A0A
n, a plurality of N switches connected to the terminals to which An is given.
Channel MOS transistor (hereinafter referred to as NMOS
) And. These NMOS are external address
Address signal Y
Desired address signal YRA from RA1 to YRAm
Arrange so that only the logical levels of k and YWBk become "H".
It is placed. This read / write Y address deco
The operation example of the recorder 2401 is shown in the timing chart of FIG.
It is shown. In this case, the address signal YRAk and
The timing when the dress signal YWBk becomes "H"
It is shown. The precharge signal PR is "H" during the period t0.
To "L". After that, during the period t2, the external address is
Address is input, the address signals YRAk and YWBk
Only goes to "H" level. This is a combination of NMOS
As a result, only the inverter Ink in that column outputs "H".
This is because the signal is output. As a result, the transfer circuit 1
19A transistor pair 119Ak, bar 119Ak and
And transfer transistor 108B transistor pair 108Bk, bar
108Bk is turned on. Here is just one example of how it works
Although shown, other columns could be selected using this example.
The operation when it is performed can be easily understood. Next, referring to FIG. 32, the serial of this embodiment will be described.
The read operation of the access memory is described. The explanation,
It is divided into periods to facilitate understanding. here
Then, as shown in FIG. 30, the read register 117A
Node in the flip-flop RF1 of
Defined and as shown in FIG. 31, write register 1
The node in the flip-flop WF2 of 11B is a node
It is defined as c and d. This clock signal is shown in FIG.
Is output from the clock signal generating circuit. here,
From the first serial access memory unit 2400A to the second
Data is transferred to the serial access memory unit 2400B.
The example of the case where it is performed is mainly shown. For other actions
Can be easily understood by referring to the operation of the above embodiment.
It <Period t1> X address decoder 103A
Selects the desired word line WLa (1≤a≤n)
To be done. In this case, the potential of this word line WLa is "
H ″. This word line WLa is now the first
To read from the output terminal DOUT1A of
Connected to memory cells that store data
It At this time, the memory cell connected to the word line WLa is connected.
Data stored in memory cells C1, a to Cm, a
Is a bit line pair BL to which each memory cell is connected.
1, bars BL1 to BLm, and bar BLm.
The data on the bit line pair is
It is amplified by SA1 to SAm. <Period t2> Next, the first read control signal
The logic level of the PRTA signal becomes "H". Therefore, transfer
Transistor pair 115A1 of circuit 115A, bar 115
A1 to 115Am and bar 115Am turn on. As a result, the sense amplifier during the period t1.
Bit line pair BL amplified by the groups SA1 to SAm
1. The data on bars BL1 to BLm and bar BLm are
The data is transferred to the first read register 117A at once. <Period t3> Next, the clock signal CLK
Rise, the timing signal φP rises in synchronization with this.
Go up. At this time, read / write common Y address deco
Address signals YRA1 and YWB1 are output from the router 2401.
Therefore, the transistor pair 11 of the transfer circuit 119A is
9A1, bar 119A1 and transfer circuit 108B transition
Both the star pair 108B1 and the bar 108B1 are turned on. This
As a result, the flip-flop of the read register 117A is
The data stored in the FF1 is the read data bus R
The delay circuit 240 transfers data to DA and bar RDA.
3 is transferred to the delay circuit 2403 and the data is stored in the delay circuit 2403.
It <Period t4> Timing signal φP is "L"
Then, the transistor pair 270 of the delay circuit 2403
3, 2704 is turned on and stored in the delay circuit 2403.
Existing data to write data bus WDB and bar WDB
Transferred. <Period t5> Next, the clock signal CLK is
The timing signal φP rises again in synchronization with this rise
stand up. At this time, read / write shared Y address
The decoder 2401 outputs the address signals YRA2 and YWB2.
Output. As a result, the transition circuit of the transfer circuit 119A is
Switch 119A2 and bar 119A2 are turned on,
In the flip-flop FF2 of the card register 117A,
The stored data is read data bus RDA, bar R
Transferred to DA. At this time, the timing signal φP is "
Since it becomes H ”, the transistor pair 2 of the delay circuit 2403
701 and 2702 are turned on and read data bus RD
The data on the A and bar RDA is set in the delay circuit 2403.
It is stored in the up-flop DFF. At this time, in period t4
Write data bus pair WDB, transferred to bar WDB
The data is the transistor pair 108B of the transfer circuit 108B.
2. Since the bar 108B2 is turned on, the write register
It is stored in the flip-flop WF2 of 111B. Thereafter, as shown in the periods t6 to t13,
The same cycle is repeated, and the first serial access
From the memory unit 2400A to the second serial access memory
The data is transferred to the section 2400B and the output terminal D
Data is output from OUT1A. In this case, the first
Serial access memory unit 2400A to second memory
The data transfer operation to the cell unit 2400B will be mainly described.
However, referring to the operation of the above embodiment, the output terminal
I can't understand how the data is output from DOUT2B.
It In this way, the serial access memo of this embodiment is
Li realizes a 2-port memory. According to the present invention, the first serial access
A delay circuit is provided between the memory unit and the second serial memory unit.
Is placed and output from the first serial access memory section.
Data is written in as
It is possible to prevent a shift of one bit when the image is captured. Therefore, a plurality of serial access memories
Functions equivalent to those realized by
It is also possible to realize it in Ji. Further, a read / write shared address deco
Since the radar is arranged, further integration can be realized. Here, the reason why the delay circuit is arranged is as follows.
A detailed description is given below. Integrate multiple serial access memories
For example, simply use two serial access memos.
If you connect them to a single chip,
The condition occurs. The output timing of the first serial memory is
Think here. The nth clock in the period tn
If the output operation is started from the rising edge of
In this case, the output has a delay time ΔtAC (act
The first serial memory with a set time)
Will be output. Next, the input type of the second serial register is
Think Ming. M-th clock in period tm
If the input operation is started from the rising edge of
When considering the circuit operation margin, the input signal is
Some time ΔtH from the time tm (called the hold time
If not confirmed on the input terminal early, the second
After writing incorrect data to the memory, correct input
Force will rewrite it, so the operating margin
I can't write at high speed. Therefore, for example, the x-th occurrence in the period tx
Considering the operation according to the th clock signal,
Serial memory of the xth clock in the period t.
When data is output in response to the clock signal, the output Dx is
It is output with a certain delay time tAC. Also, during the same period
In the second serial memory, the write operation is performed.
Be done. At this time, in response to the clock signal generated in the period tx
The data written by the
There is data that was output from the serial memory.
The data to be written is output in the period tx-1.
The data becomes Dx-1. Therefore, the first serial memory and the second serial memory are
Simply connecting the real memory to the second serial
Writing data to the memory is shifted by 1 bit.
Will be lost. This means high speed with good operating margin
It becomes a trouble for writing. However, the serial access device of the present embodiment of the present invention is
According to the setting memory, this 1-bit shift is delayed.
Since a delay circuit for adjusting the
Multiple serial access memos easily using road design technology
(In the above embodiment, two serial access memories
Can be integrated into one chip. Next, a fifteenth embodiment of the present invention will be described with reference to FIG.
Described with reference. FIG. 33 shows a fifteenth embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. The serial access memory of this embodiment is the first
14 of the serial access memory described in the fourteenth embodiment.
Initialization circuit 3300 for data bus RDA and bar RDA
Are connected. This initialization circuit 3300 is a transistor
3301, 3302, 3303, initialization signal
In response to the signal EQ, the read data bus RDA, bar RDA
Has a function of applying a predetermined potential for initialization. this
These transistors are NMOS. Transistor 33
01 indicates a read data bus RDA and an electric signal having a predetermined potential.
Connected to the source, the transistor 3302 is connected to the lead
Connected between the data bus bar RDA and the power supply,
The star 3303 is a read data bus RDA and read data.
It is connected to the bus bar RDA. These transitions
An initialization signal EQ is applied to the control electrode of the star. The operation of this serial access memory is
The operation is basically the same as that described in the fourteenth embodiment described above.
However, the initialization signal EQ is set by the initialization circuit 3300.
Read data buses RDA and RDA are
They are different in that they are initialized to a constant potential. Refer to the timing chart of FIG. 34 below.
However, the operation of the serial access memory of this embodiment is
Explained. The explanation is the same as in the above-mentioned embodiment
It is cut. <Period t1> X address decoder 103A
Selects the desired word line WLa (1≤a≤n)
To be done. In this case, the potential of this word line WLa is "
H ″. This word line WLa is now the first
To read from the output terminal DOUT1A of
Connected to memory cells that store data
It At this time, the memory cell connected to the word line WLa is connected.
Data stored in memory cells C1, a to Cm, a
Is a bit line pair BL to which each memory cell is connected.
1, bars BL1 to BLm, and bar BLm.
The data on the bit line pair is
It is amplified by SA1 to SAm. <Period t2> Next, the first read control signal
The logic level of the PRTA signal becomes "H". Therefore, transfer
Transistor pair 115A1 of circuit 115A, bar 115
A1 to 115Am and bar 115Am turn on. As a result, the sense amplifier in the period t1.
Bit line pair BL amplified by the groups SA1 to SAm
1. The data on bars BL1 to BLm and bar BLm are
The data is transferred to the first read register 117A at once. <Period t3> Next, the clock signal CLK
Rise, the timing signal φP rises in synchronization with this.
Go up. At this time, read / write common Y address deco
Address signals YRA1 and YWB1 are output from the router 2401.
Therefore, the transistor pair 11 of the transfer circuit 119A is
9A1, bar 119A1 and transfer circuit 108B transition
Both the star pair 108B1 and the bar 108B1 are turned on. Also, the initialization signal EQ changes from "H" to "L".
Transition to read data bus RDA, bar RDA
Data can be transferred to. Read before period t3
The data bus RDA and the bar RDA are initialized to the power supply potential.
ing. As a result, the read register 117A
The data stored in the flip-flop FF1 is
In addition to being transferred to the data bus RDA and bar RDA,
The data is transferred to the delay circuit 2403 and is transferred to the delay circuit 2403.
Data is stored. <Period t4> Timing signal φP is "L"
Then, the transistor pair 2703 of the delay circuit 2403,
2704 is turned on, and the delay circuit 2403 flip-flop is turned on.
The data stored in the DFF is the write data bus.
Transferred to WDB, WDB. At the same time, the initialization signal EQ becomes "H", and
The voltage data bus RDA and the bar RDA are set to the power supply voltage level.
It is initialized. <Period 5> When the clock signal CLK rises
Timing signal PY rises again in synchronization with this.
It At this time, the read / write shared address decoder 24
01 outputs address signals YRA2 and YWB2 at the same time.
I will be forced. As a result, the transition of the transfer circuit 119A is
Since the star pair 119A2 and the bar 119A2 are turned on,
In the flip-flop RF2 of the register 117A for the card,
The stored data is read data bus RDA, bar
Transferred to RDA. Further, the timing signal φP becomes "H".
Therefore, the transistor pair 2701 and 2701 of the delay circuit 2403 are
702 turns on, and data flips the delay circuit 2403.
It is stored in the flop circuit DFF. Further, during the period t4, the write data bus WD
B, bar WDB transferred data is write register 1
It is stored in the flip-flop WF2 of 11B. Thereafter, as shown in period 5 to period t13
The same cycle is repeated. According to the serial access memory of this embodiment,
For example, in the effect of the serial access memory of the 14th embodiment
In addition, since the read data bus initialization circuit is provided,
Higher speed access becomes possible. Next, a sixteenth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 35 shows a sixteenth embodiment of the present invention.
A structure showing a main part of the serial access memory of the embodiment
FIG. In this case, understanding the description of the present embodiment
In order to facilitate the
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. In the serial access memory of this embodiment,
The write access of the serial access memory of the fourteenth embodiment
Without the transistor 111B and the transfer circuit 113B, the transfer circuit 10
8B is directly connected to the memory cell array 101B.
It In this serial access memory, the 14th
As the nodes corresponding to the nodes c and d in the embodiment of
Codes c and d are defined. Operation of serial access memory of this embodiment
Can be easily understood by referring to the description of the operation of the fifteenth embodiment.
Understandable. In the serial access memory of this embodiment,
The data on the write data bus RDA and bar RDA is directly
Then, it is transferred to the memory array 101B. According to the serial access memory of this embodiment,
Thus, in addition to the effects of the fourteenth embodiment, the second serial access
Reading the data from the process memory is the second serial memo.
For applications that do not conflict with the writing of data
If applied, 2 ports without writing registers
Since the memory can be realized, the chip size can be significantly reduced.
Wear. Next, the seventeenth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 36 shows the seventeenth aspect of the present invention.
A structure showing a main part of the serial access memory of the embodiment
FIG. In this case, understanding the description of the present embodiment
In order to facilitate the
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. The serial access memory of this embodiment is the first
Read data of the serial access memory according to the fifteenth embodiment
The initialization circuit 3300 is connected to the buses RDA and RDA.
Has been. Operation of serial access memory of this embodiment
Refers to the description of the operation of the above-mentioned fourteenth to sixteenth embodiments.
If you understand. According to the serial access memory of this embodiment,
For example, in addition to the effect of the fifteenth embodiment, an initialization circuit is provided.
Therefore, faster access is possible. Next, the eighteenth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 37 is an eighteenth embodiment of the present invention.
A structure showing a main part of the serial access memory of the embodiment
FIG. In this case, understanding the description of the present embodiment
In order to facilitate the
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. In the serial access memory of this embodiment,
The read register of the serial access memory of the fourteenth embodiment
Register 117A, transfer circuit 115A, and read register
The transfer circuit 119 without the data 115B and the transfer circuit 117B.
A is directly connected to the memory cell array 101A for transfer.
Circuit 119B directly connected to memory cell array 101B
Has been done. In this serial access memory, the 14th
As the nodes corresponding to the nodes a and b in the embodiment of
Do a and b are defined. Operation of serial access memory of this embodiment
Refer to the above description of the operation of the fourteenth embodiment,
Easy to understand. According to the serial access memory of this embodiment,
For example, in addition to the effects of the fourteenth embodiment, the second serial memo
Data writing timing and first serial memo
Read data read timing does not conflict.
When used for such purposes, read data Data
A 2-port memory can be realized without providing registers.
Therefore, the chip size can be significantly reduced. Next, a nineteenth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 38 shows a nineteenth embodiment of the present invention.
A structure showing a main part of the serial access memory of the embodiment
FIG. In this case, understanding the description of the present embodiment
In order to facilitate the
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. The serial access memory of this embodiment is the first
Read data of the serial access memory according to the eighteenth embodiment
The initialization circuit 3300 is connected to the buses RDA and RDA.
Has been. Operation of serial access memory of this embodiment
Refers to the description of the operation of the above-mentioned fifteenth to eighteenth embodiments.
If you understand. According to the serial access memory of this embodiment,
For example, in addition to the effect of the eighteenth embodiment, an initialization circuit is provided.
Therefore, faster access is possible. Next, a twentieth embodiment of the present invention is shown in FIG.
Will be described with reference to. FIG. 39 shows a twentieth embodiment of the present invention.
A structure showing a main part of the serial access memory of the embodiment
FIG. In this case, understanding the description of the present embodiment
In order to facilitate the
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. In the serial access memory of this embodiment,
The line of the first serial access memory of the fourteenth embodiment is
Register 111A and transfer circuit 113A, read register
Transistor 117A, transfer circuit 115A, and second serial port
Access memory write register 111B, transfer circuit 1
13B, read register 115B and transfer circuit 117B
, The transfer circuit 108A and the transfer circuit 119A directly
The transfer circuit 108 is connected to the memory cell array 101A.
B, the transfer circuit 119B is directly connected to the memory cell array 101.
Connected to B. Operation of the serial access memory of this embodiment
Refer to the above description of the operation of the fourteenth embodiment,
Easy to understand. In this case, for writing and reading
Since there are no registers, each write data bus and
Read data bus and memory cell arrays 101A, 101
Data is input / output directly to / from B. According to the serial access memory of this embodiment,
Therefore, in addition to the effect of the fourteenth embodiment, access at such a high speed can be achieved.
If the application is not necessary, read data
Data register and write data register are not provided
Since a 2-port memory can be realized with
The width can be reduced and an inexpensive memory can be provided. Next, a twenty-first embodiment of the present invention will be described with reference to FIG.
Described with reference. FIG. 40 shows the twenty-first embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. The serial access memory of this embodiment is
Read data of serial access memory according to 20th embodiment
The initialization circuit 3300 is connected to the buses RDA and RDA.
Has been. Operation of serial access memory of this embodiment
Describes the operation of the 14th, 15th and 20th embodiments described above.
You can understand if you consider it. According to the serial access memory of this embodiment,
For example, in addition to the effects of Example 20, an initialization circuit is provided.
Therefore, faster access is possible. Next, a twenty-second embodiment of the present invention is shown in FIG.
Will be described with reference to. FIG. 41 shows a twenty-second embodiment of the present invention.
A structure showing a main part of the serial access memory of the embodiment
FIG. In this case, understanding the description of the present embodiment
In order to facilitate the
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. The serial access memory of this embodiment is
Writing to the second serial access memory of the fourteenth embodiment
The memory circuit 4100 is provided in the data bus WDB 'and the bar WDB'
Are connected. This memory circuit 4100 is shown in FIG.
Like two flip-flops MFF and bar MFF
Composed of a write data bus WDB 'and a bar WDB'
It has the function of holding the above data. Operation of serial access memory of this embodiment
Can be easily understood by referring to the fifteenth embodiment described above.
Wear. In this case, the write data bus WDB 'and the bar W
The data on DB 'is until the next data is transferred
Retained. According to the serial access memory of this embodiment,
Thus, in addition to the effects of the fourteenth embodiment, the memory operation is paused.
Is required, the line of the second serial memory is
Storage circuit 410 in the data bus WDB 'and bar WDB'
Since 0 is connected, reliable operation is guaranteed. Next, a twenty-third embodiment of the present invention will be described with reference to FIG.
Described with reference. FIG. 43 shows the 23rd embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. The serial access memory of this embodiment is
Writing to the second serial access memory of the fifteenth embodiment
The memory circuit 4100 is provided on the data bus WDB 'and the bar WDB'.
Are connected. Operation of serial access memory of this embodiment
Can be easily obtained by referring to the fifteenth and sixteenth embodiments described above.
Understandable. In this case, the write data bus WDB ′,
For the data on the bar WDB ', the next data is transferred.
Held until According to the serial access memory of this embodiment,
In addition to the effects of the fifteenth and sixteenth embodiments,
The second serial memory when a pause is required
Write data bus WDB ', bar WDB' storage circuit
As 4100 is connected, reliable operation is guaranteed
It Further, as in the 22nd and 23rd embodiments,
Second serial access memo of 16th to 21st embodiments
Rewrite data bus WDB ', bar WDB' memorized times
If you connect each of the paths 4100,
In addition to the effects of the sixteenth to twenty-first embodiments, the memory operation is
Of the second serial memory
Storage circuit 4 for write data bus WDB 'and bar WDB'
As 100 is connected, reliable operation is guaranteed
It Next, the serial access method of the above-described embodiment is used.
Memory applied to a device with two banks of memory
Examples will be described. First, the twenty-fourth embodiment of the present invention is shown in FIG.
Described with reference. FIG. 44 shows a twenty-fourth embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. The serial access of this example
The process memory is the first serial access memory unit 240.
0A second serial access memory unit 2400B, third
Serial access memory unit 2400C and fourth serial
It is composed of an Al access memory unit 2400D
It The first serial access memory unit
To the element which has the same function as the above-mentioned element of 2400A
Has an "A" at the end of the above code, and its detailed
The description is omitted. This first serial access
See FIG. 25 for the detailed configuration of the memory unit 2400A.
Is easier to understand. Also, the second serial access memory unit 2
To the element which has the same function as the above-mentioned element of 400B
Is added with "B" at the end of the above code, and its detailed
The description is omitted. This second serial access
See FIG. 26 for the detailed configuration of the memory unit 2400B.
Is easier to understand. Further, the third serial access memory unit 2
To the element which has the same function as the above-mentioned element of 400C
Has a "C" at the end of the above code, and its detailed
The description is omitted. This third serial access
The detailed configuration of the memory unit 2400C is shown in FIGS.
It can be easily understood by reference. This third series
Al access memory unit 2400C write data bus pair
WDB, bar WD and read data bus RDA, bar R
DA is the first serial access memory unit 2400A
Write data bus pair WDB, bar WDB and read data
It is connected to Tabas RDA and Bar RDA. Also, the fourth serial access memory unit 2
To the element which has the same function as the above-mentioned element of 400D
Is added with "D" at the end of the above code, and its detailed
The description is omitted. This fourth serial access
The detailed configuration of the memory unit 2400D is shown in FIGS.
It can be easily understood by reference. This fourth series
Al access memory unit 2400D write data bus pair
WDB ', bar WD and read data bus RDA, bar
RDA is the second serial access memory unit 2400B.
Write data bus pair WDB ', bar WDB' and Lee
It is connected to the data bus RDA and bar RDA. Basics of Serial Access Memory of this Embodiment
For the general operation, refer to the description of the operation of the fourteenth embodiment.
Can be understood by referring to FIGS. 45 and 46.
Only characteristic operations are described. 45 and 46 show
The characteristic operation of the serial access memory of this embodiment is explained.
It is a schematic circuit block diagram which shows. As shown in FIG. 45, for example, the first
Serial access memory unit 2400A and second serial port
For writing data in the access memory unit 2400B
Transfer processing (WRITE IN) and data reading
While the transfer processing (READOUT) for
At the same time, the third serial access memory unit 2400C and
And the fourth serial access memory unit 2400D
Set operation becomes possible. Similarly, as shown in FIG.
In addition, for example, the third serial access memory unit 2400
C and the fourth serial access memory unit 2400D
Transfer processing for writing data (WRITE IN) and
And transfer processing for reading data (READ OU
While T) is being performed, at the same time, the first serial access
Small memory unit 2400A and second serial access memo
The access operation can be performed in the memory unit 2400B. This place
In the figure, a, b, c, d in the figure are cashiers accessing
Represents any bit of the star, easy to understand the description
Shown to comb. According to the serial access memory of this embodiment,
You can operate as described above, without interruption.
Data can be written and read, and
In addition to the effects of Example 14, Syria that can be applied to a wider range of purposes
Access memory can be provided. Similarly, the serial address of the various embodiments described above is used.
The serial access memory of this embodiment is suitable for the access memory.
Twenty-fifth to thirty-first embodiments used are shown. in this case,
In order to facilitate understanding of the description of this embodiment, the above-mentioned
The elements are appropriately block-shaped and shown schematically. That
Therefore, the same symbols are attached to the same elements as the elements mentioned above.
And its description is omitted. Detailed about these
The description can be understood by referring to the above-mentioned embodiment. FIG. 47 shows the twenty-fifth embodiment.
The fifteenth embodiment of the serial access memory is the second
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. FIG. 48 shows the twenty-sixth embodiment.
As described above, the serial access memory of the sixteenth embodiment is
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. The twenty-seventh embodiment is shown in FIG.
As described above, the serial access memory according to the seventeenth embodiment is
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. In the 28th embodiment, as shown in FIG.
As described above, the serial access memory of the eighteenth embodiment is
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. The twenty-ninth embodiment is shown in FIG.
The serial access memory according to the nineteenth embodiment is the second
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. In the thirtieth embodiment, as shown in FIG.
As described above, the serial access memory of the 22nd embodiment is
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. In the thirty-first embodiment, as shown in FIG.
As described above, the serial access memory of the 23rd embodiment
2 banks like the serial access memory of the fourth embodiment
What is provided is shown. Further, although not shown, the 22nd and 2nd
Serial access memory of the third embodiment and sixteenth to second
Of the second serial access memory of the first embodiment.
The storage circuit 4100 is installed in the data bus WDB and the bar WDB.
The serial access memory with the configuration connected to each
Similarly, the twenty-fourth embodiment can be applied to form a two-bank configuration.
I can do it. The serial access codes of the twenty-fifth to thirty-first embodiments.
According to Seth Memory, as described in the twenty-fourth embodiment,
It is possible to operate, so write data without interruption
And reading can be performed, and the effect of the fourteenth embodiment is added.
Yes, a serial access memory that can be applied to a wider range of purposes
Can be provided. Next, the 32nd embodiment of the present invention will now be described with reference to FIG.
Described with reference. FIG. 54 shows the 32nd embodiment of the present invention.
Configuration showing the configuration of the main part of the serial access memory of the embodiment
It is a block diagram. In this case, understand the explanation of this embodiment.
For simplicity, the elements listed above have been appropriately blocked.
And is shown schematically. And the same as the element
The same code is attached to one element, and the explanation is omitted.
Has been. In the serial access memory of this embodiment,
The X address decoder 103A of the various embodiments described above,
Address counter that gives a common X address to 103B
A circuit 5400 is arranged. This address counter circuit 5400 is
In response to the lock signal CLK and the reset signal Reset
Common to the X address decoders 103A and 103B.
Has a function to give addresses A0X, A1X ... AnX
To do. This address counter circuit 5400
Is a plurality of unit address counter circuits CNTR0 to CNTR
It consists of TRn. This unit address counter circuit CNTRi
Reset signal Reset, as shown in FIG.
Receives input Bn-1 and outputs Bn and X address Ai
Output X. This reset signal Reset goes to "H"
Then, the output B of the unit address counter circuit CNTRi
n becomes "L". This unit address counter circuit CNTRi
The specific configuration of the above is shown in FIG. This unit address
In the counter circuit CNTRi, the input Bn-1 is an input terminal.
In1 given to the
1 controlled by output and input Bn-1
The output of the inverter gate In1 and this inverter In1
Transfer gate T controlled by input Bn-1
Reset signal Reset is input to R and one input terminal
And transfer gate TR1 to the other input terminal
Via X address AiX and transfer gate TR
NOR to which the output of the inverter In2 is connected via 2
The gate and the output and input Bn-1 of the inverter In1
Controlled transfer gate TR3 and inverter
Data controlled by the output and input Bn-1 of the data input In1.
Transfer gate T4 and transfer gate T
NOR gate output and transfer via R3
The input terminal is connected to the output Bn via the port TR4.
Inverter In4 and its input connected to the output of inverter In4
Inverter I, which is connected and whose output is connected to output Bn-1
n5 and. As shown in FIG. 57, such units
A plurality of address counter circuits AiX are connected in series.
Thus, the address counter circuit 5400 is configured. This
An example of the operation of the address counter circuit 5400 of FIG.
It is shown in the partial timing chart. Here, the serial access memory of the present embodiment
The operation will be briefly described with reference to FIG. X address is added from the address counter circuit 5400.
Address is X address decoder 103A, X address decoder
When applied to the memory 103B, the memory cell array 101A
And memory cell array 101BA1 are the same
Address of the first memory cell array 10
1A word line WL1 and second memory cell array
The word line WL1 of 101B is selected. [0231] In this case, the memory cell array 101A
The word line WL1 rises and the first serial access
From memory 101A to first read register 117A
Data is transferred to ((A) in the figure), and then the delay time
1 bit delayed by the path, the data is for the second write
It is written in the register 111B ((B) in the figure). So
After that, the word line WL0 of the memory cell array 101B
Rises and is connected to the word line WL0.
The contents of the second write register 111B are stored in the memory cell.
It is transferred in a cycle ((C) in the figure). [0232] That is, the first selected by the common X address.
1 is connected to the word line of the memory cell array 101A.
The data in the memory cell is the first read register 11
7A, the first signal is transferred in response to the clock signal CLK.
It is output from the output terminal DOUT1 and is delayed for a predetermined period.
After being delayed, it is written to the write register 111B.
It After that, writing to the write register 111B
Second memo selected with common X address after completion
Memo connected to the word line of the re-cell array 101B
Data is written in the resell. According to the serial access memory of this embodiment,
In addition to the effects of the various embodiments described above,
A first and second X-address decoder provided with a counter circuit
Since a common address is given to
The number of raw circuits can be reduced resulting in chip area
Can be made smaller. As described above, various embodiments have been described.
As described above, according to the serial access of the present invention, a plurality of serial
Functions equivalent to those realized by real access memory
To connect the first and second transfer registers in series
Can be realized by Further, the serial access of another invention of the present application
The memory has the above-mentioned configuration,
Serial access memory can be easily integrated into a single chip.
And are possible. The serial access memo of the present invention described above.
The display device 600 is shown in FIG.
Applied to 0. This display device 6000 is used in the present invention.
Serial access memory 6001 and its serial
Receive the output of the memory access memory 6001
D / A converter that performs analog-to-analog conversion and outputs data
A barter 6002 and a serial access memory 6001
Controller 6 for controlling D / A converter 6002
003 and the data from the D / A conversion circuit 6002 is displayed.
And a display unit 6004 for displaying as data
It Besides this, the serial access memo of the present invention
Li can be applied to various fields. The invention is illustrated by means of illustrative embodiments.
However, this explanation should not be taken in a limited sense.
No Various modifications of this illustrative embodiment, as well as the
Other obvious embodiments will refer to this description for those skilled in the art.
Will become apparent. Therefore, the patent contract
The scope of the request is to identify all such changes or implementations.
Thought to cover as included in the true scope of Ming
It is obtained. According to the serial access of the present invention, multiple access is possible.
Functions that were realized by several serial access memories, etc.
Valuable function connects first and second transfer registers in series
It can be realized by doing. Therefore, the occupied area is small and the cost is low.
A serial access memory can be realized. Further, serial access according to another invention of the present application
According to the memory, the first serial access memory and the second serial access memory
A delay circuit is placed between the serial access memory and
Is implemented with multiple serial access memories.
Serial access memory having a function equivalent to the existing function
Can be easily integrated into a single chip.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram showing a configuration of a main part of a serial access memory according to a first embodiment of the present invention. FIG. 2 is a schematic diagram illustrating a characteristic portion of the serial access memory according to the first embodiment. FIG. 3 is a partial timing chart showing a data write operation of the serial access memory according to the first embodiment. FIG. 4 is a partial timing chart showing a data read operation of the serial access memory according to the first embodiment. FIG. 5 is a circuit block diagram showing a configuration of a clock signal generation circuit of the serial access memory of the first embodiment and a partial timing chart showing its operation. FIG. 6 is a circuit block diagram showing a configuration of a main part of a serial access memory according to a second embodiment of the present invention. FIG. 7 is a partial timing chart showing a data read operation of the serial access memory according to the second embodiment. FIG. 8 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a third embodiment of the present invention. FIG. 9 is a circuit block diagram showing a configuration of a delay circuit according to a third embodiment. FIG. 10 is a partial timing chart showing a data read operation of the serial access memory according to the third embodiment. FIG. 11 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a fourth embodiment of the present invention. FIG. 12 is a circuit block diagram showing a configuration of a delay bypass circuit of a fourth embodiment. FIG. 13 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a fifth embodiment of the present invention. FIG. 14 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a sixth embodiment of the present invention. FIG. 15 is a circuit block diagram showing a configuration of a delay selection circuit according to a sixth embodiment. FIG. 16 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a seventh embodiment of the present invention. FIG. 17 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to an eighth embodiment of the present invention. FIG. 18 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a ninth embodiment of the present invention. FIG. 19 is a partial timing chart showing a data read operation of the serial access memory of the tenth embodiment. FIG. 20 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a twelfth embodiment of the present invention. FIG. 21 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a twelfth embodiment of the present invention. FIG. 22 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a twelfth embodiment of the present invention. FIG. 23 is a circuit block diagram schematically showing a configuration of a main part of a read register of a serial access memory according to a thirteenth embodiment of the present invention. FIG. 24 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a fourteenth embodiment of the present invention. FIG. 25 is a circuit block diagram showing a specific configuration of the first serial access memory unit of the fourteenth embodiment. FIG. 26 is a circuit block diagram showing a specific configuration of a second serial access memory section of the fourteenth embodiment. FIG. 27 is a circuit block diagram showing the structure of the delay circuit of the fourteenth embodiment. FIG. 28 is a circuit block diagram showing a specific circuit configuration of a read / write shared Y address decoder 2401 according to a fourteenth embodiment. FIG. 29 is a partial timing chart showing an operation example of the read / write shared Y address decoder of the fourteenth embodiment. FIG. 30 is a read register 117A of the fourteenth embodiment.
3 is a circuit block diagram showing a configuration of a main part of FIG. FIG. 31 is a write register 111B of the fourteenth embodiment.
3 is a circuit block diagram showing a configuration of a main part of FIG. FIG. 32 is a partial timing chart showing the operation of the serial access memory of the fourteenth embodiment. FIG. 33 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a fifteenth embodiment of the present invention. FIG. 34 is a partial timing chart showing the operation of the serial access memory of the fifteenth embodiment. FIG. 35 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a sixteenth embodiment of the present invention. FIG. 36 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a seventeenth embodiment of the present invention. FIG. 37 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to an eighteenth embodiment of the present invention. FIG. 38 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a nineteenth embodiment of the present invention. FIG. 39 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a twentieth embodiment of the present invention. FIG. 40 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 21st embodiment of the present invention. FIG. 41 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 22nd embodiment of the present invention. FIG. 42 is a circuit block diagram showing the structure of the memory circuit of the twenty-second embodiment. FIG. 43 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 23rd embodiment of the present invention. FIG. 44 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 24th embodiment of the present invention. FIG. 45 is a schematic circuit block diagram illustrating the operation of the serial access memory according to the 24th embodiment. FIG. 46 is a schematic circuit block diagram explaining the operation of the serial access memory according to the 24th embodiment. FIG. 47 is a circuit block diagram schematically showing an arrangement of a main part of a serial access memory according to a 25th embodiment of the present invention. FIG. 48 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 26th embodiment of the present invention. FIG. 49 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 27th embodiment of the present invention. FIG. 50 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 28th embodiment of the present invention. FIG. 51 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 29th embodiment of the present invention. FIG. 52 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 30th embodiment of the present invention. FIG. 53 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 31st embodiment of the present invention. FIG. 54 is a circuit block diagram schematically showing a configuration of a main part of a serial access memory according to a 32nd embodiment of the present invention. FIG. 55 is a circuit block diagram showing a unit address counter circuit of the thirty-second embodiment. FIG. 56 is a circuit block diagram showing a specific configuration of the unit address counter circuit of the thirty-second embodiment. FIG. 57 is a circuit block diagram showing a configuration of an address counter circuit of the 32nd embodiment. FIG. 58 is a partial timing chart showing the operation of the address counter circuit of the 32nd embodiment. FIG. 59 is a partial timing chart explaining the operation of the 32nd serial access memory. FIG. 60 is a circuit block diagram showing an example in which the serial access memory of the present invention is applied to a display device. [Description of Reference Signs] 101 memory cell array 103 X address decoder 105 input circuit 107 Y address decoder (for writing) 109, 113, 115, 119, 125, 129 transfer circuit 111 write register 117 read register 121 first Y address Decoder (for writing) 123 First output circuit 127 Second read register 131 Second Y address decoder 133 Second output circuit

Claims (1)

Claim: What is claimed is: 1. A plurality of word lines, a plurality of bit line pairs arranged so as to intersect the word lines, and a plurality of bit lines are connected to intersections of the word lines and the bit line pairs. A plurality of memory cells for respectively storing data; an X decoder circuit for selecting a desired word line from the plurality of word lines; a plurality of first registers connected to each of the plurality of bit line pairs; A plurality of first switch circuits connected between the bit line pair and the plurality of first registers, between the bit line pair and the first register in response to a first control signal. And a plurality of second switch circuits connected to each of the plurality of first registers.
A register and a plurality of second switch circuits connected between the plurality of first registers and the plurality of second registers.
A plurality of second switch circuits that bring the first register and the second register into a conductive state in response to the control signal, and a first output circuit connected to the plurality of first registers, A first transfer circuit connected between the plurality of first registers and the first output circuit, wherein a desired register is selected from the plurality of first registers in response to a first column signal. And a second output circuit connected to the plurality of second registers, the first transfer circuit transferring the data stored in the selected register to the first output circuit, A second transfer circuit connected between the first register and the first output circuit, selecting a desired register from the plurality of second registers in response to a second column signal. The data stored in the selected register. The second switch circuit for transferring to the second output circuit; and a Y decoder circuit for giving the first and second column signals to the first and second transfer circuits, the first switch circuit Is turned on and the second switch circuit is turned off, the data is input to the first register, the first switch circuit is turned on, the second switch circuit is turned on, and the data is transferred to the first register. A serial access memory, wherein the serial access memory passes through one register and is input to the second register. 2. A first delay circuit, which delays data transferred from the first transfer circuit, is connected between the first transfer circuit and the first output circuit. The serial access memory according to claim 1. 3. A first circuit connected in parallel with the first delay circuit between the first transfer circuit and the first output circuit.
The bypass circuit for transmitting the data transferred from the first transfer circuit in response to the first bypass signal.
3. The serial access memory according to claim 2, further comprising the first bypass circuit which transfers the data to the output circuit. 4. A second delay circuit connected between the second transfer circuit and the second output circuit, for delaying data transferred from the second transfer circuit, and the second delay circuit. A second bypass circuit connected in parallel with the second delay circuit between a transfer circuit and the second output circuit, wherein the second bypass circuit is responsive to a second bypass signal from the second transfer circuit. 4. The serial access memory according to claim 3, further comprising: the second bypass circuit that transfers the transferred data to the second output circuit. 5. A first and a second flip-flop circuit connected in series between the first transfer circuit and the first output circuit, the first transfer circuit and the first output. A first transistor connected in parallel with the first and second flip-flop circuits between the first transfer circuit and the first output circuit in response to a first selection signal; A second transistor connected in parallel to the second flip-flop circuit between the first transistor and the first output circuit, the first transistor being electrically connected to a circuit; A transistor, comprising: the second transistor, which makes a connection between the first flip-flop circuit and the first output circuit in response to a second selection signal. Serial access memo described in item 1 . 6. A third and a fourth flip-flop circuit connected in series between the second transfer circuit and the second output circuit, the second transfer circuit and the second output. A third transistor connected in parallel to the third and fourth flip-flop circuits between the second transfer circuit and the second output circuit in response to a third selection signal. A fourth transistor connected in parallel to the fourth flip-flop circuit between the third transistor and the second output circuit, the third transistor being electrically connected to the circuit; A transistor, comprising: the fourth transistor, which makes a connection between the third flip-flop circuit and the second output circuit in response to a fourth selection signal. Serial access memo of item 5 . 7. The serial access memory according to claim 1, wherein a dimension of a transistor forming the first register is smaller than a dimension of a transistor forming the second register. 8. The serial access memory according to claim 1, wherein a first resistor is connected between the plurality of second registers and a driving power supply. 9. The serial access memory according to claim 8, wherein a second resistor is connected between the plurality of first registers and the driving power supply. 10. The first and second registers are first
Of inverters and a second inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The serial access memory according to claim 1, wherein 11. The serial access memory according to claim 10, wherein the first and second inverters are clocked inverters. 12. A memory cell array in which a plurality of memory cells for storing data are arranged, a first register connected to the memory cell array via a first switch circuit, and a second switch circuit. A second register connected to the first register, wherein when the first switch circuit and the second switch circuit are in an ON state, the first register is transferred from the memory array to the second register. The data is transferred from the memory cell array to the first register when the data is transferred through a register and the first switch circuit is in the ON state and the second switch circuit is in the OFF state. Serial access memory characterized by. 13. The serial access memory according to claim 12, wherein a dimension of a transistor forming the first register is smaller than a dimension of a transistor forming the second register. 14. The first and second registers are first
Of inverters and a second inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. 13. The serial access memory according to claim 12, wherein: 15. The serial access memory according to claim 14, further comprising a first resistor connected between the first and second inverters and a driving power source. 16. The serial access memory according to claim 14, wherein a dimension of a transistor forming an inverter of the first register is smaller than a dimension of a transistor forming an inverter of the second register. 17. The first data read from the memory cell array to the first register in the first transfer period,
In a data transfer method of a serial access memory, wherein the second data read from the memory cell is transferred to a second register in a second transfer period, the second data is stored in the first register. A data transfer method for a serial access memory, characterized in that the data is passed and transferred to the second register. 18. A first memory cell for storing data, a first register connected to the first memory cell via a first transistor, and a second transistor for the first register. A second register connected through the first register, a first control signal supply line for supplying a first control signal having a first or second logic level to the first transistor, and a first or second A second control signal supply line for supplying a second control signal having a logic level to the second transistor, wherein the first control signal is the first control signal.
And the second control signal has the second logic level, the first transistor is
N, the second transistor is turned off, the data is input to the first register, the first control signal has the first logic level, and the second control signal is the When having the first logic level, the first transistor is turned on, the second transistor is turned on, and the data is input to the second register through the first register. Serial access memory characterized by. 19. The serial access memory according to claim 18, wherein a dimension of a transistor forming the first register is smaller than a dimension of a transistor forming the second register. 20. The second register is connected to a driving power supply, and the first register is connected between the second register and the driving power supply.
19. The serial access memory according to claim 18, wherein the resistances are connected. 21. The first register is connected to a driving power supply, and a second resistor is provided between the first register and the driving power supply.
21. The serial access memory according to claim 20, wherein the resistor is connected. 22. The first and second registers are composed of two inverters, the output of one inverter is connected to the input of the other inverter, and the output of the other inverter is connected to the input of the one inverter. 19. The serial access memory according to claim 18, wherein the serial access memory is connected. 23. The serial access memory according to claim 22, wherein a dimension of a transistor forming an inverter of the first register is smaller than a dimension of a transistor forming an inverter of the second register. 24. In a data transfer method of transferring data read from a memory circuit to first and second registers connected in series, when the data is transferred to the first register, A data transfer method of directly transferring data from a memory circuit and transferring the data to the second register, the data being transferred to the second register through the first register. 25. A first serial access memory section, comprising: a first word line, a first bit line pair arranged to intersect the first word line, and the first word. A first memory cell connected to an intersection of a line and the first bit line pair and storing first data, and connected to the first bit line pair, and the first data is input. An output register and a first switch circuit connected between the first bit line pair and the output register, wherein the first switch circuit is connected between the first bit line pair and the output in response to a first control signal. A first switch circuit for bringing a register into a conductive state and transferring the first data to the output register; a data bus connected to the output register; and an output circuit connected to the data bus, The output register and the data bus A first transfer circuit connected between,
A first serial access memory unit including the first transfer circuit that transfers the first data to the data bus in response to a first column signal; and a second serial access memory unit. A second word line, a second bit line pair arranged to intersect with the second word line, the second word line and the second word line.
A second memory cell connected to the intersection of the bit line pair and storing the second data, and connected between the second bit line pair and the data bus to receive the first data. A second switch circuit connected between the second bit line pair and the second bit line pair, the second switch circuit being connected between the second bit line pair and the second bit line pair in response to a second control signal. The first input register is electrically connected to the first input register,
A second transfer circuit connected between the input register and the second data bus, the second switch circuit supplying the second data to the second bit line pair, and being responsive to a second column signal. And a second serial access memory unit including the second transfer circuit for transferring the first data on the data bus to the input register; and the first transfer circuit for the first serial access memory unit. A Y-decoder circuit for giving a column signal and giving the second column signal to the second transfer circuit, and a delay circuit connected between the data bus and the second transfer circuit. A delay circuit for delaying the first data on the bus for a predetermined period and applying the delayed data to the second transfer circuit. 26. An initialization circuit connected to the data bus, comprising the initialization circuit which sets the data bus, to which the first data is applied, to a predetermined potential in response to an initialization signal. 26. The serial access memory device according to claim 25. 27. The first circuit provided between the delay circuit and the second transfer circuit and provided from the transfer circuit.
26. The serial access memory according to claim 25, further comprising a data storage circuit for storing the data of FIG. 28. The first circuit provided between the delay circuit and the second transfer circuit and provided from the transfer circuit.
27. The serial access memory according to claim 26, further comprising a data storage circuit for storing the data of FIG. 29. A first X decoder circuit for applying a first selection signal to the first word line, a second X decoder circuit for applying a second selection signal to the second word line, and 26. An address counter for providing a common address to the first and second X decoders.
Serial access memory as described. 30. A first X decoder circuit for applying a first selection signal to the first word line, a second X decoder circuit for applying a second selection signal to the second word line, and 29. An address counter for providing a common address to the first and second X decoders.
Serial access memory as described. 31. A D / A converter for receiving output data from the serial access memory device according to claim 25 and the output circuit of the serial access memory device, converting the output data from a digital value to an analog value, and outputting the analog value. A circuit, the serial access memory device, and the D
A display device comprising: a control circuit for controlling the A / A conversion circuit; and a display unit for displaying an image on a screen according to the output from the D / A conversion circuit. 32. The serial access memory according to claim 28, wherein the delay of the predetermined period is caused in response to a change in the logic level of the delay control signal. 33. A semiconductor memory device in which the serial access memory device according to claim 25 is covered with a package resin. 34. A clock signal generation circuit for generating a first clock signal and a second clock signal continuous to the first clock signal, and a first serial access memory section for outputting data in response to the first clock signal. A second serial access memory unit to which the data is input in response to the second clock signal; and a second serial access memory unit connected between the first serial access memory and the second serial access memory. And a delay circuit for delaying the data from the first serial access memory for a predetermined period and applying the delayed data to the second serial access memory. 35. A data bus, which is arranged between the first serial access memory unit and the delay circuit and transfers the data, and an initialization circuit connected to the data bus, wherein an initialization signal is provided. 35. The serial access memory device according to claim 34, further comprising the initialization circuit for setting the data bus to which the data is applied in response to the predetermined potential to a predetermined potential. 36. A storage circuit arranged between the delay circuit and the second serial access memory unit, for storing the delayed data output from the delay circuit. 35. The serial access memory according to 35. 37. The serial access memory device according to claim 34, a D / A conversion circuit that receives the data from the serial access memory device, converts the data from a digital value to an analog value, and outputs the data. A display device comprising: a control circuit for controlling the access memory device and the D / A conversion circuit; and a display section for displaying an image on a screen according to an output from the D / A conversion circuit. 38. The serial access memory according to claim 36, wherein the delay of the predetermined period is caused in response to a change in the logic level of the delay control signal. 39. A semiconductor memory device in which the serial access memory device according to claim 34 is covered with a package resin. 40. A step of outputting data from a first serial access memory in response to a first clock signal, and a step of delaying the data for a predetermined period and then continuing the second clock signal to the first clock signal. Providing the data to the second serial access memory in response to a clock signal. 41. Data output from the first serial access memory is applied to a data bus, and immediately after the data is applied to the data bus, the data bus is precharged to a predetermined potential. The data transfer method of a serial access memory according to claim 40. 42. The data transfer method for a serial access memory according to claim 41, wherein the delay of the predetermined period is caused in response to a change in the logic level of the delay control signal. 43. A first memory cell array in which a plurality of memory cells each storing data are arranged, a data bus from which data stored in a desired memory cell among the plurality of memory cells is read, An output circuit connected to the data bus; a second memory cell array to which the data read from the desired memory cell is input; and a second memory cell array connected between the data bus and the second memory cell array, And a delay circuit for delaying the read data for a predetermined period and applying the delayed data to the second memory cell array. 44. An initialization circuit connected to the data bus, comprising the initialization circuit which sets the data bus, to which the data is applied, to a predetermined potential in response to an initialization signal. The serial access memory device according to claim 43. 45. A storage circuit arranged between the delay circuit and the second memory cell array, for storing the delayed data output from the delay circuit. Serial access memory. 46. The serial access memory device according to claim 43, a D / A conversion circuit for receiving the data from the serial access memory device, converting the data from a digital value to an analog value, and outputting the data. A display device comprising: a control circuit for controlling the access memory device and the D / A conversion circuit; and a display section for displaying an image on a screen according to an output from the D / A conversion circuit. 47. The serial access memory according to claim 45, wherein the delay of the predetermined period is caused in response to a change in the logic level of the delay control signal. 48. A semiconductor memory device in which the serial access memory device according to claim 43 is covered with a package resin. 50. A first serial access memory unit for outputting data stored in a memory cell, a second serial access memory unit for receiving the data, the first serial access memory unit, and the first serial access memory unit. A delay circuit connected between the second serial access memory section and the second serial access memory section, delaying the data from the first serial access memory section for a predetermined period, and applying the delayed data to the second serial access memory section. A serial access memory device having a delay circuit. 51. A data bus arranged between the first serial access memory unit and the delay circuit for transferring the data, and an initialization circuit connected to the data bus, wherein an initialization signal is provided. 51. The serial access memory device according to claim 50, further comprising: the initialization circuit for setting the data bus to which the data is applied in response to the data bus to a predetermined potential. 52. A storage circuit arranged between the delay circuit and the second serial access memory unit, for storing the delayed data output from the delay circuit. 51. A serial access memory device according to item 51. 53. The serial access memory device according to claim 50, a D / A conversion circuit for receiving the data from the serial access memory device, converting the data from a digital value to an analog value, and outputting the data. A display device comprising: a control circuit for controlling the access memory device and the D / A conversion circuit; and a display section for displaying an image on a screen according to an output from the D / A conversion circuit. 54. The serial access memory according to claim 52, wherein the delay of the predetermined period is caused in response to a change in the logic level of the delay control signal. 55. A semiconductor memory device in which the serial access memory device according to claim 50 is covered with a package resin.