JP2846782B2 - Video RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port memory of a semiconductor memory device, and more particularly, to a serial access memory (SAM).
mory).

[0002]

2. Description of the Related Art Video RAM (or dual-port dynamic RAM): A dual-port dynamic RAM is used as a memory element of a video RAM, and both terms are often used in this field. Is a RAM having two input / output terminals of a random port and a serial port. Access to a CPU as a central processing unit is random, while access for displaying data on a CRT is serial. It has become. Such a video RAM has a function of serial read transfer and a function of serial write transfer for inputting and outputting serial data. Serial read transmission refers to an operation for transmitting data stored in a random access memory to a serial access memory and reading the data.Serial write transmission refers to an operation for writing data to the serial access memory and then reading the data. Is transmitted to and stored in the random access memory. Among them, the serial write transmission is a very important function in the video RAM, and is a function applied particularly to a place where high-speed data processing such as processing of image data is required.

FIG. 5 is a block diagram showing the concept of a conventional serial write transmission. The block diagram of FIG. 5 shows a serial write transmission widely used in this field at present. A predetermined address is input to an input buffer 10, and an output of the input buffer 10 causes a predetermined block of the serial access memory SAM to be transmitted. Is driven.
The block selection signal generator 20 is connected to the serial access memory SAM, for example, four blocks M '.
Control is performed so that data is written in any one of the blocks 1, 1, M'2, M'3, and M'4. At this time, data is input to the serial access memory SAM from a data input buffer (not shown). This situation is shown in FIG.
Is shown in The block diagram on the left side of FIG. 5 shows a state in which writing has been performed on the block M′1 of the serial access memory SAM. After the writing to the block M'1 is completed, as shown in the block diagram on the right side of FIG.
The data is transmitted by the data transmission gate 1 to the block M1 of the random access memory RAM.

[0006] FIG. 6 shows a process of successively performing serial write transmission to another block of the random access memory RAM. That is, when serial write transmission is continuously performed to the block M2 of the random access memory RAM, data is written to the block M'2 of the serial access memory SAM again under the control of the block selection signal generator 20 again. Thereafter, the random access memory RA is transmitted via the data transmission gate 1.
The data is transmitted to M blocks M2, and a serial write transmission is performed.

As described above, according to the conventional serial write transmission, in order to execute the serial write transmission to the i blocks of the random access memory, data is written to one block of the serial access memory. After that, the data is transmitted to one block of the random access memory, and thereafter, the data is written again to one block of the serial access memory, and then the data is transmitted to one block of the random access memory. Thus, the data writing / transmission process needs to be repeated i times. This becomes a major obstacle when high-speed data processing such as image processing is required, and a next-generation ASIC (application specific IC:
There is a problem to be solved by application specific IC) memories such as a video RAM, a field memory, and a graphic memory.

[0006]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a video RAM which can execute serial write transmission quickly and can process data at a higher speed.

[0007]

In order to achieve such an object, the present invention provides m (m = 1, 2, 3,...) Rows, n
M (M = 1, 2, 3,...) Composed of N (N = 1, 2, 3,...) Memory cell groups in a matrix form of (n = 1, 2, 3,...) Columns …) Random access memory having blocks and a serial access memory having M blocks each composed of a memory cell group in the form of one row and n columns. In a video RAM in which a block is connected to each block of the random access memory, a write energy is transmitted during serial write transmission.
Of the serial access memory according to the activation of the
Enable M blocks at the same time and
After writing data to the network, according to the data transmission signal,
Of the serial access memory selected for transmission
From the block, the corresponding block of the random access memory
The data is transmitted to a lock .

In addition, the block selecting means for performing such control uses a data transmission enable signal as a common control signal, a first input circuit for transmitting a block selection signal and a write enable signal in accordance with the data transmission enable signal, and a second input circuit. A two-input circuit, a first latch circuit and a second latch circuit that latch respective output signals of the first input circuit and the second input circuit, and input signals of the first latch circuit and the second latch circuit, respectively. A first NAND circuit, a second NAND circuit that receives an inverted signal of an output signal of the first latch circuit and an output signal of the second latch circuit, and a first NA
A first transmission circuit and a second transmission circuit for reading output signals of the ND circuit and the second NAND circuit and transmitting the read signals under control of a transmission enable signal; and latching output signals of the first transmission circuit and the second transmission circuit, respectively. Third latch circuit and fourth latch circuit
And a latch circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals are given to the same parts as in the related art, and the overlapping description will be omitted. FIG. 1 is a circuit diagram of an embodiment of a block selecting means provided for performing serial write transmission according to the present invention, and FIG. 2 is an operation timing chart thereof. FIG. 3 is a flowchart showing the concept of serial write transmission according to the present invention.

The block selecting means shown in FIG. 1 has a first and a second input circuit TM to which a data transmission enable signal φDTE is commonly input as a control signal and which transmits a block selection signal BLSC and a write enable signal φWTE, respectively.
1, TM2, first and second latch circuits L1, L2 for latching respective output signals of the first and second input circuits TM1, TM2, and respective outputs of the first and second latch circuits L1, L2. A first NAND gate 37 to which a signal is input, and a second NAND gate 3 to which an inverted signal of an output signal of the first latch circuit L1 and an output signal of the second latch circuit L2 are input.
8, first and second transmission circuits TM3 and TM4 for transmitting the output signals of the first and second NAND gates 37 and 38 under the control of the read transmission enable signal φRTE;
Third and fourth latch circuits L3 and L3 for latching and outputting respective output signals of the second transmission circuits TM3 and TM4.
And 4. Inverters 40 and 43 are provided at the output terminals of the third and fourth latch circuits L3 and L4, respectively.
In order to set the initial values of the output terminals 3 and L4 to logic "low", initial value setting transistors 46 and 47 which are commonly controlled by an initial value setting signal φINT are provided.

When the data transfer enable signal .phi.DTE becomes logic "high", the block select signal BLSC and the write enable signal .phi.WTE pass through the first and second input circuits TM1, TM2, respectively, to the first and second latch circuits L1, L2.
2 is transmitted. The first and second latch circuits L1 and L2 are
Block select signal BLSC and write enable signal φW
And the data transmission enable signal φDTE becomes logic “low”, and the first and second input circuits T
Even if M1 and TM2 are turned off, the initial input state is maintained. Then, the output signals of the first and second latch circuits L1 and L2 are input to the third and fourth transmission circuits TM3 and TM4 via NAND gates 37 and 38.
At this time, when the read transmission enable signal φRTE goes to a “low” state, the third and fourth transmission circuits TM3, TM4
Is turned on, and the output signals of the first and second latch circuits L1 and L2 are transmitted to the third and fourth latch circuits L3 and L4, respectively. Then, the third and fourth latch circuits L3 and L4
Latches the output signals of the first and second latch circuits L1 and L2, respectively, and maintains the initial input state even if the third and fourth transmission circuits TM3 and TM4 are turned off.
The initial value setting transistors 46 and 47 are turned on when the initial value setting signal φINT is at the power supply voltage level, and set the initial state of the output terminals of the third and fourth latch circuits L3 and L4 to logic “low”. Set. The output signals of the third and fourth latch circuits L3 and L4 pass through inverters 40 and 43, and block selection information signals φBS1 and φBS for selecting a block of the serial access memory SAM (FIG. 4).
Output as 2.

In order to execute the serial write transmission as described above, the block selection information signal φBS1 is applied to the blocks M′1, M′3 of the serial access memory SAM (FIG. 4).
To select the block selection information signal φBS.
2 is connected to select blocks M'2 and M'4 (FIG. 4). Further, when the data transmission enable signal φDTE and the write enable signal φWTE are input at a logic “high”, the block selecting means outputs the block selecting signal BL.
All blocks of the serial access memory SAM are selected regardless of the SC.

FIG. 2 is an operation timing chart of the block selecting means of FIG. 1 when performing serial write transmission. Data transmission enable signal φD of each logic “high”
When TE and the write enable signal φWTE are input, the signals passing through the NAND gates 37 and 38 become logic “high” at points A and B, respectively, regardless of the state of the block selection signal BLSC. The signal is further transmitted to the third and fourth transmission circuits TM
The logic goes low at points C and D via the third, fourth and third latch circuits L3, L4. The signals pass through inverters 40 and 43 to become logic "high" block selection information signals .phi.BS1 and .phi.BS2, respectively. As a result, the serial access memory SAM blocks M'1-.
All of M'4 are selected.

The process of transmitting data to a random access memory using such a block selecting means will be described with reference to the flowchart of FIG. After the writing to all the blocks of the serial access memory SAM is completed (24) by the block selecting means of FIG. 1, the block to be transmitted is selected by the block selection signal BLSC (25),
Subsequently, when the data transmission signal φDTP for performing data transmission to the random access memory RAM is enabled (26), the serial access memory SA is accordingly operated.
The data written in M is stored in the random access memory RA.
M is selectively transmitted (27).

FIG. 4 is a block diagram corresponding to FIG. 3 to facilitate understanding of the flowchart of FIG. When the serial writing is started, as described above, all the blocks M 'of the serial access memory SAM are controlled by the block selecting means 200 such as the circuit of FIG.
1, M'2, M'3, M'4 (FIG. 4 shows a video RAM having, for example, four random access memory RAMs), and a data input buffer (not shown) is selected. The data is written to each block via the. Thereafter, data is selectively transmitted to the random access memory RAM according to the data transmission signal φDTP output from the data transmission signal generator 300. In this way, serial write transmission is easily performed.

The embodiment shown in FIG. 1 is an example for realizing the idea of the present invention, and the present invention is not limited to this. Of course, if the same signal processing can be performed, different configurations can be adopted. .

[0017]

As described above, according to the present invention, when serial write transmission is performed, serial write transmission can be performed more quickly by collectively writing data to all blocks of the serial access memory. As a result, the data processing speed is improved. As a result, it is possible to greatly contribute to realization of a demand for faster data processing and a larger amount of data, such as a next-generation ASIC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a block selecting means according to the present invention.

FIG. 2 is an operation timing chart at the time of serial write transmission of the circuit of FIG. 1;

FIG. 3 is a flowchart of serial write transmission according to the present invention.

FIG. 4 is a block diagram illustrating a block selection process of serial write transmission according to the present invention.

FIG. 5 is a block diagram illustrating a block selection process of serial write transmission according to the related art.

FIG. 6 is a block diagram illustrating a block selection process of serial write transmission according to a conventional technique.

[Explanation of symbols]

 φDTE data transmission enable signal φWTE write enable signal BLSC block selection signal φRTE read transmission enable signal φBS1, φBS2 block selection information signal φDTP data transmission signal φINT initial value setting signal TM1 first input circuit TM2 second input circuit L1 first latch circuit L2 Second latch circuit 37 First NAND circuit 38 Second NAND circuit TM3 First transmission circuit TM4 Second transmission circuit L3 Third latch circuit L4 Fourth latch circuit 46, 47 Transistors for initial value setting

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/407

Claims (5)

(57) [Claims] 1. m (m = 1, 2, 3,...) Rows, n (n =
N, (N, N) in the form of a matrix of 1, 2, 3,...
= 1, 2, 3,...) Memory cell groups, each having M (M = 1, 2, 3,...) Blocks, and one row and n columns. And a serial access memory having M blocks each composed of a group of memory cells, wherein each block of the serial access memory is connected to each block of the random access memory.
At the time of serial write transmission, the write enable signal is activated.
According to the M blocks of the serial access memory
Enable data simultaneously and write data to all blocks
After receiving the data, select it for transmission according to the data transmission signal.
From the selected block of the serial access memory
A video RAM adapted to transmit said data to a corresponding block of a random access memory . 2. Block selection of serial access memory
A first input circuit and a second input circuit for transmitting a block select signal and a write enable signal in accordance with the data transmission enable signal , using the data transmission enable signal as a common control signal; A first latch circuit and a second latch circuit for latching each output signal of the circuit and the second input circuit, a first NAND circuit inputting each output signal of the first latch circuit and the second latch circuit, and a first latch 2nd N receiving an inverted signal of the output signal of the circuit and the output signal of the second latch circuit
An AND circuit, a first transmission circuit and a second transmission circuit for reading output signals of the first NAND circuit and the second NAND circuit and transmitting the read signals under control of a transmission enable signal, and respective outputs of the first transmission circuit and the second transmission circuit 2. The video RAM according to claim 1, further comprising a third latch circuit and a fourth latch circuit for latching each signal. 3. The video RAM according to claim 2, wherein the first input circuit, the second input circuit, the first transmission circuit, and the second transmission circuit are constituted by transmission gates. 4. A first latch circuit, a second latch circuit, and a third latch circuit.
3. The video RAM according to claim 2, wherein the latch circuit and the fourth latch circuit are configured by CMOS inverters connected in parallel in opposite directions. 5. The video RAM according to claim 2, wherein the block selecting means includes an initial value setting transistor controlled by an initial value setting signal at each output terminal of the third latch circuit and the fourth latch circuit. .