DE4027051A1 - Multi-gate RAM with direct and series access - has memory cells in lines and columns, each with direct access, and SAM memory elements - Google Patents

Abstract

The memory region (RAM) contains a matrix of memory cells (2) with direct access, and another memory region (SAM) with a number of memory elements (31), which transmit data simultaneously with a line of the memory cells, while affoding a serial access to each memory element. In both memory regions numberous bits may be parallel written, or read-out, with both regions divided into blocks corresp. to the number of width. Between the two memory regions are gates (1; T0-T3) for data transmission. A control (50) responds to the signal, presetting to the data transmission mode and to a signal preventing such data transmission for the gate control. USE/ADVANTAGE - For image processing, with improved multi-gate RAM.

Description

The present invention relates to a multi-port memory with direct or optional access. This store points an input / output port that can be accessed directly can. Furthermore, this memory has an input / Output port with only serial access to.

In the field of image processing or the like, image information already processed or to be processed is displayed on a CRT screen (cathode ray tube screen). For this purpose, a memory is used, which is referred to as "image memory for storing the image information of a frame or section". Such an image memory is commonly called video RAM (VRAM). Referring to Fig. 1, the structure and operation of an image processing system using the video RAM will be briefly described below.

Fig. 1 shows a video signal processing system (image processing system) having a CPU (Central Processing Unit) 100, a CRT controller 102, a video RAM 104, and a CRT screen 106th

The CPU 100 writes desired data into the video RAM 104 and reads out desired data from the video RAM 104 . The CRT screen control unit 102 generates horizontal / vertical synchronizing signals of the CRT screen 106 and an address for reading data from the video RAM 104 and for supplying this data to the video RAM 104 . The video RAM 104 stores image information which is then read under the control of the CRT screen control unit 102 and supplied to the CRT screen 106 . In order to display the data from the video RAM 104 on the screen of the CRT screen 106 sets coming from the video RAM 104 data to parallel or serial. In general, the data coming from video RAM 104 form a plurality of bits. In a digital memory pattern system, each bit corresponds to a point on CRT screen 106 . This is the reason why parallel / serial conversion of the data is required.

The central processing unit (CPU) 100 can directly access the video RAM 104 for reading or writing data. Accordingly, these data write 104 can be on the desired arithmetic operation with the data stored in the video RAM 104 information or data back into the video RAM. The data read from the video RAM 104 are then supplied to the CRT screen 106 and images can be displayed on the CRT screen 106 in accordance with this supplied data.

If a general dynamic random access memory (DRAM) is used as the image buffer, data must be read from the DRAM continuously during the imaging period in order to generate the image to be displayed on the CRT screen 106 . Since a memory cycle of the general DRAM is defined as either a read cycle or a write cycle, the CPU 100 can during the imaging period does not access the DRAM, so that the write or read cycle of the CPU 100 of the video RAM is limited to a period with respect to the does not correspond to the mapping period, ie to a period of the horizontal or vertical blanking interval. As a result, there is a significant latency of the CPU 100 which slows down the speed of the program.

To overcome these disadvantages of a general one used as a frame buffer Balancing DRAM is already a multi-port RAM (a RAM with two gates or ports) has been used as image memory.

In U.S. Patent 4,633,441 to S. Ishimoto is the general one Structure of such a two-port memory disclosed. At According to this state of the art, the data from the RAM port become transmitted to the SAM port and finally serially from the SAM Port read.

The US-PS 46 36 986 discloses a bit mask method according to the data transfer of a desired memory arrangement in one Memory masked with a plurality of memory arrays or is displayed in mask form.  

The multi-port RAM has an input / output port that can be accessed directly from the CPU 100 . The RAM also has a serial input / output port for serial reading of the image data, this being done by controlling the CRT screen control unit 102 . The data is transferred to the CRT screen 106 . If, in the case of the multi-port RAM, data of one line (this corresponds to the data of a horizontal scan) are transferred from a RAM port (directly accessible memory area) to a SAM port (serially accessible memory area), the image data are extracted from the SAM during the imaging phase. Port read while the RAM port can be accessed by the CPU 100 . Accordingly, the waiting time of the CPU 100 can be reduced, which also reduces the speed for executing the program. In the SAM port, the transmitted data of one line is read serially, so that the cycle time in the SAM port is approximately ¼ or ½ that of the RAM port, the RAM port requiring a larger data storage cycle. As a result, images are displayed at high speed.

Fig. 2 shows the basic structure of the image buffer used in the multi-port RAM. A multiplicity of multi-port RAM is generally used in an image buffer. If a multi-port RAM, hereinafter referred to as RAM with two ports, has a 64K × 4 bit RAM port and a 256 × 4 bit SAM port, and if 640 pixels are arranged in the horizontal direction of the screen and one pixel of four bits each exists, a total of four such RAM with two ports are used. If the screen has 1024 × 512 pixels, eight such RAMs with two ports are used. Fig. 2 schematically shows a structure in which four RAM with two ports are used. Physical addresses in a CPU memory area are divided among each of the two-port RAM. A row decoder 6 , a column decoder 7 and an address buffer 8 are provided in common for the RAM memories 2-0, 2-1, 2-2 and 2-3.

The address buffer 8 derives from externally supplied address signals A 0 , A 1 ,. . . , to internal address signals. The row decoder 6 decodes the internal row address signals from the address buffer 8 and thereby selects a corresponding row from the RAM memory areas 2-0 to 2-3. The column decoder 7 decodes internal column address signals from the address buffer 8 and thereby selects a corresponding column from the RAM memory areas 2-0 to 2-3. Each of the RAM memory areas 2-0 to 2-3 has memory cells arranged in rows and columns. A RAM input / output buffer 4 is used for data transfer between the RAM memory areas 2-0 to 2-3 and external devices.

The SAM port has SAM memory areas 3-0, 3-1, 3-2 and 3-3 corresponding to each of the RAM memory areas 2-0 to 2-3. Each of the SAM memory areas 3-0 to 3-3 can simultaneously transmit data with its memory cells connected to a row of the corresponding RAM memory areas 2-0 to 2-3. Each of the SAM memory areas 3-0 to 3-3 transmits serial data SIO₁ to SIO _n via a SAM input / output buffer 5 to the outside and from the outside to the inside. Each of the RAM memory areas 2-0 to 2-3 and the SAM memory areas 3-0 to 3-3 can be accessed bit by bit. If each SAM memory area has a structure that can input or output four bits in parallel, the bit buffer can output or input four bits, eight bits or sixteen bits in parallel, depending on its structure.

Between the respective RAM memory areas and the respective SAM memory areas are used for data transfer between  the RAM memory areas 2-0 to 2-3 and SAM memory areas 3-0 to 3-3 transfer gates 1-0 to 1-3 are provided.

Fig. 3 schematically shows the entire structure of a RAM having two ports. More specifically Fig. 3 shows the structure of a RAM having two ports which can enter in parallel by way of example, four bits or read. A RAM memory cell arrangement 2 has a memory cell arrangement divided into four blocks. The four blocks of the memory cell arrangement correspond to four bit data WIO₀ to WIO₃ of the RAM input / output buffer 4th

The row decoder 6 selects an internal address signal from the address buffer 8 from one line out of the RAM memory cell array. 2 The column decoder 7 selects two columns in each block of the RAM memory cell arrangement in response to an internal column address signal from the address buffer 8 .

The SAM memory area also has a data register 31 . The data register 31 serves to store a row of the memory cell data of the RAM memory cell arrangement 2 . The SAM memory area also includes a serial data switch 32 , which successively connects the data register units of the data register 31 to the SAM input / output buffer 5 in response to a pointer signal from an address pointer 33 .

The address pointer 33 determines a selected bit of the data register 31 in response to the internal column address from the address buffer 8 .

A transfer gate 1 is provided between the RAM memory cell arrangement 2 and the data register 31 for data transfer.

In the SAM memory area too, the data register 31 and the serial data switch 32 are divided into four blocks, so that serial access is possible in blocks.

A control area 40 is provided for generating operating clock signals of the two-port RAM. The control area 40 receives a signal for clocking the row address clock. Furthermore, the control area 40 receives a signal / for indicating the control of the writing per bit operation, which will be described in more detail later and for indicating whether the writing process is possible. The control area also receives a signal / for controlling the data output of the directly accessible memory area and for controlling the data transfer between the data register 31 and the RAM memory cell arrangement 2 . Finally, the control area 40 receives a control signal SC which serves as a clock signal in the serial memory area and a signal for controlling the operation of the SAM memory area. The mode of operation is briefly described below.

In the RAM memory area, the data access to the address signals A 0 to A 7 and the signals, and (/) is controlled as in a conventional DRAM.

The reading of data from the SAM memory area is first carried out by transferring the data of one row from the RAM memory cell arrangement 2 to the data register 31 by means of control of the address signals A 0 to A 7 and the signals, and /. The column address signal stored in response to the signal is loaded into the address pointer 33 . The bit loaded into the address pointer 33 by the column address signal (one bit from each block, a total of four bits) is the first bit which is transferred to the SAM input / output buffer 5 . When the signal SC (serial control) is switched, the content of the address pointer 33 is expanded each time the signal SC takes the value "H", and the content of the data register 31 becomes bit by bit for each block via the serial Data switch 32 transferred to the SAM input / output buffer 5 . With this structure, when the data register 31 is divided into four blocks, one bit from each block is read simultaneously to generate 4-bit parallel data.

Data is written to the SAM memory area in accordance with the read operation described above, but in reverse order. Each time the control signal SC assumes the value "H", the data supplied to the SAM input / output buffer 5 are read into the data register 31 . After the data of one row is written into the data register 31 , the data is read into the row of the RAM memory cell arrangement 2 which is selected by the address signals A 0 to A 7 . This is done by opening the transmission gate 1 to the signals, and / towards. The data transfer function between the RAM memory cell array 2 and the data register 31 is described below.

A read transmission cycle will be described below with reference to FIG. 4. In a read cycle, when the signal / is set to "L", the signal is brought to "L", the signal / to "H" and the signal is brought to an arbitrary level, the signal having the active state ("L" - level) during the reading cycle. When the data reading from the RAM memory cell arrangement 2 has ended, that is to say after the data of the memory cells connected to the selected row in the RAM memory cell arrangement 2 are transferred and fixed on the bit lines (columns), the data is sent to the signal when the signal / Transfer data register 31 . For the data of a row transferred to the data register 31 , the column address stored in the address buffer 8 upon the signal is loaded into the address pointer 33 , whereby the first bit to be output via the serial data switch 32 to the SAM input / output buffer 5 is determined. Reading data from the SAM input / output buffer 5 usually takes place after the data transfer to the data register 31 has ended .

Referring to Fig. 5, a write transfer cycle will be described below. When the signal / is set to the "L" level, the DT / OE signal is given the "L" level and the SE signal is given the "H" level, the signal being activated with the same timing as in the read transmission cycle of the Case is. The content stored in the data register 31 is written to the selected RAM memory cell arrangement 2 upon raising the signal. The write transfer cycle is essentially performed after the data has been written from the SAM input / output buffer 5 into the data register 31 .

If the signal assumes the "H" level and the signal becomes active in the write transfer cycle, a pseudo write transfer cycle takes place. In the pseudo-write transfer cycle, the SAM input / output buffer 5 has not yet been activated and, accordingly, the input data have not yet been written into the data register 31 . In the pseudo-write transfer cycle, the data transfer from the data register 31 to the memory cell arrangement 2 has not yet taken place.

As described above, data is read from the SAM input / output buffer 3 essentially after the data transfer to the data register 31 has been completed. However, there are some cases where the data of the next line must be read from the SAM input / output buffer 5 immediately after the reading of the data from one line is completed. In such a case, the reading of the data from the RAM memory cell arrangement 2 (ie the selection of a line in the RAM memory cell arrangement 2 , the detection and amplification as well as the storage or retention of the memory cell data with respect to the selected line) takes place during the data Read operation of the SAM input / output buffer 5 . The signal / is then brought to the "H" level so that data are transmitted to the data register 31 via the transmission gate 1 as shown in FIG. 6. This data transfer cycle is called a real-time transfer cycle. This real-time transfer cycle enables internal data transmission from the port with direct access to the port with serial access during the period for imaging a horizontal scanning line of an image unit can thus be distributed to a plurality of lines of the memory or assigned to these lines. If the data of the serial port is read at a desired bit position (control function for the address pointer) after an internal data transfer to the serial port using a real-time data transfer cycle, a pixel shift has already occurred in the horizontal direction.

With video RAM, the aim is often to change the value of any bit from the storage data of a word. This is the case, for example, if, for example, the background area of an image is to be retained and a person or the like is to be replaced in the foreground of the image. For this purpose, an operation is provided in the two-port PAM, which is referred to as a bit-wise write operation. In this operation, the writing of data is only possible with respect to one of four bits selected bits, namely with regard to one of the input signals WIO₀ to WIO₃. This writing of data takes place within the data write cycle in the RAM input / output buffer 4 . The bit-wise write operation will be briefly described below with reference to FIG. 7.

An early DRAM write cycle or a "modified" read-write cycle is used as part of the bitwise write operation. The early write cycle is a cycle in which the / signal is activated before the signal is active. The data output terminal is kept safely in the floating state. The read / write cycle is an operation cycle in which selected memory cell data are output to the data output terminal. The input data supplied to the input data terminal is then written into the selected memory cell. In this read / write cycle, if the data supplied to the data input terminal corresponds to the data obtained by modifying the data output to the data output terminal, it is a modified read / write cycle. In this cycle, the signal / becomes active after a sufficient time from the activation of the signal. In such an operation cycle, the signal / level "L", the signal of the bit on which the writing of data from the RAM input / output signals WIO₀ to WIO₃ is not permitted, receives the level "L" and the potentials of the remaining ones Bits become "H" as soon as the RAS signal becomes active. As soon as the signal becomes active, the data are written to the bit for which the input signal at WIO₀ to WIO₃ has the level "H" (ie the data are written into the block of the RAM memory cell arrangement 2 ). When the data to be written to the RAM input / output WI₀ to WI₃ is supplied and the signal is activated, the cycle becomes an early write cycle. If in the meantime the signal / has temporarily reached the level "H" and the signal is activated, and the signal / gets the level "L" again, the cycle becomes the modified read / write cycle.

Some two-port RAM have flash write cycles to clear the screen at high speed in addition to the cycles described above. The flash write cycle is a function mode in which access from the outside is prevented after the data register 31 has been written with the information “0”. Rows of the RAM memory cell arrangement 2 are selected in succession so that the information "0" written in the data register 31 is written into the RAM memory cell arrangement 2 via the transfer gate 1 .

As described above, the two-door RAM the data input as well as data output of data one Memory line at high speed. Hence this RAM very suitable for use as an image buffer in image processing and so far in the field of image processing has been widely used. With a conventional two-door However, RAM is a transfer cycle for switching the Input mode on the output mode of the SAM memory always required.

When a data transfer from the data register area to the RAM memory area takes place, the SAM memory area placed in the input mode to execute the write cycle. When the data transfer from the RAM memory area to the SAM storage area is done, the SAM storage area in an output mode for performing the read cycle spent. The signal is used to control reading or Write in the SAM memory area. If the signal is the Is "H", data is not written to the data register.  

The selection of the input mode or output mode of the SAM memory area is achieved by carrying out the read transfer cycle or the write transfer cycle. For example, if the output mode of the SAM memory area is to be switched to the input mode, the write transfer cycle for transferring data from the SAM memory area to the RAM memory area must be activated. In this case, the bit position in the data register 31 in which the data originating from the SAM input / output buffer 5 are to be written first must be defined in the SAM memory area. This is done by performing the write transfer cycle. At this time, however, the content of the data register 31 is transferred to the RAM memory cell of the row specified by the row address. In order to change the contents of the RAM memory area or to switch the output mode of the SAM memory area to the input mode, the pseudo-write transfer cycle is carried out as shown in FIG. 8. Referring to Fig. 8, the operation mode switching in the SAM memory area is briefly described below.

It should be emphasized here that the SAM has been switched to the output mode and that the output data SIO₀ to SIO₃ have been fed to the SAM input / output buffer 5 within period I. In this case, the data transfer cycle from the RAM memory cell arrangement 2 to the data register 31 and the output data SIO₀ to SIO₃ are supplied to the SAM input / output buffer 5 via the serial data switch 32 .

Then the pseudo-write transfer cycle for switching the output mode of the SAM memory area into the input mode is carried out. In the pseudo write transfer cycle, the control signal becomes "H" as soon as the signal is activated. In this case, the transmission gate 1 is not opened even when the control signal / is activated and is at the "L" level. The data transfer to the RAM memory area, ie from the data register 31 to the RAM memory cell arrangement 2 , is then not completed. The generation of the control signal SC is also prevented in the pseudo-write transmission cycle (cf. FIG. 8 II).

If the signals and both the level "H" and the control signal has the level "L", the serial input data SIO₀ to SIO₃ are stored in the data register 31 in response to the control signal SC. The data stored at that time will be stored in the designated line in the next memory transfer cycle.

A general write cycle then takes place again. As soon as the control signal / level "L" and the control signal have the level "L" and the signal has the level "L", the generation of the control signal SC is interrupted and the transmission of the new input data from the SAM memory area to the RAM memory area carried out. If, on the other hand, the signals and the level are "H" and the SAM memory area is activated, the input data SIO₀ to SIO₃ are stored in the data register 31 via the SAM input / output buffer 5 (cf. FIG. 8 III). The data entered following the pseudo transmission cycle are successively stored in bit positions of the data register predetermined by column addresses. The column addresses come from row and column addresses from the pseudo transmission cycle. Data stored in the data register 31 are written into those rows which are specified by row addresses in the next cycle, ie by row addresses taken from the signals and from the RAM memory cell arrangement 2 .

A masked write transfer operation, in which a similar function to the bit-wise write operation is carried out, and only the data transfer to the mask bit is prevented. This operation is known as another pseudo transmission cycle and serves as an alternative to the transmission cycle shown in FIG. 8.

To perform the operation mode described above is switching the operation mode of the SAM memory area, d. H. switching from the output mode to the input mode, possible without the stored content in the RAM To change the memory cell arrangement area.

However, there is no "pseudo read transfer cycle" here, that is, there is no mode in which data transfer from the RAM memory area to the SAM memory area is prevented, so that when the input mode of the SAM memory area is switched to the output mode data transfer from the RAM memory area (RAM memory cell arrangement 2 ) to the SAM memory area (data register 31 ) is required. As a result, the content of the SAM memory area (data register 31 ) is changed by the data transfer. Namely, it is impossible not to read the data content of the SAM memory area (data register 31 ) from the SAM memory area (data register 31 ) directly via the RAM memory area (RAM memory cell arrangement 2 ).

For example, if it is necessary to determine whether the SAM memory area works properly, can not be easily determine whether in the RAM memory area or in the SAM memory area defective bits exist. This even applies then when data is written to and from the SAM memory area this memory area can be read.  

Testing a storage device generally indicates Steps of writing the same information "0", for example in each bit of the memory device, reading this data from the storage device and comparing it the original data and that read from the storage device Data to determine if the storage device is defective. In this case, the fact that the RAM memory area is defective, determined first and if it is identified as defective , it can be seen that the defective bit in the SAM storage area exists. As a result, it takes a lot of time claim to determine if the two-port RAM is defective.

If there is a defective bit in the DRAM memory area it is also impossible to determine the defective bit if there is also a defective one in the SAM memory area Bit is present.

It is in the field of image processing and the like sometimes required SAM memory areas as shift registers to create a line memory for the delay line to use a horizontal scan line. A such a delay line or delay line is used in the Image processing usually for the detection of a contour, for Correction and generation of interpolating pixels for exemplary pixels or the like are used. Even in in such cases, however, the contents of the RAM memory area once in the SAM memory area of the conventional two-port RAM transferred. Therefore, it is impossible to use the SAM memory area as a delay element without changing what is in it Content to use.

In the field of image processing, an image area is sometimes used formed from a plurality of images and only one  Picture of it should be written again. For example, this is then the case when the background of an image is preserved and only the foreground is changed. In one such cases must be with the conventional multi-port RAM the data of the area to be changed once in the RAM memory area be written so that you can from the SAM memory area can be read again. This prevents image processing at high speed. Beyond that data that should not be changed is also changed here.

The present invention is therefore based on the object Eliminate disadvantages of conventional multi-port RAM. The one SAM area of a multi-port RAM directly from the SAM Memory area data should be readable without first having to be stored in RAM. Furthermore should be able to be determined at high speed whether the SAM memory area of a multi-port RAM is defective. Continue should a SAM port from input mode to output mode without unnecessary data transmission can be switched. After all, the Maintenance capability of a two-port store improved be.

The foregoing object is achieved by the features of the claims 1, 6 and 11 solved.

The multi-port RAM according to the invention has the following features on: a RAM memory array is made up of blocks accordingly the input / output data bits. A SAM storage array is also made up of blocks according to the input / Output data bits and corresponding to the RAM array blocks educated. Gates are used for data bit transmission between the RAM memory array and the SAM memory array. A Control device controls the function of the gates, the Control device on a data transmission signal and a  Data transmission preventing selection signal for prevention the data transfer between blocks according to the the one bit select signal preventing data transmission selected bits in the RAM memory array and in the SAM memory arrangement responds.

The multi-port RAM according to the invention also has means on that to a signal defining the operation mode and to an output signal from the control device for switching the operation mode of the SAM memory area from the input mode address in output mode. The multi-port RAM points furthermore, a second control device, which on the SAM memory area activating signal for controlling the Function of the gates responds in such a way that any data transmission between the RAM memory area and the SAM memory area is prevented.

The method according to the invention for storing data has the following process steps: with a two-port RAM a RAM memory arrangement consisting of with input / Output data bit corresponding blocks, a SAM memory array off with the input / output data bits and the Blocks of the RAM memory arrangement corresponding blocks and a transfer gate for transferring data between the RAM memory arrangement and the SAM memory arrangement to a data transmission signal and to a data transmission preventing, bit-selecting signal only the data transfer between the RAM memory block and the SAM block of memory corresponding to that by which the data transfer preventing, bit determining signal.

The method according to the invention for storing data points furthermore the following method steps: on an operating mode default signal and an output signal from the  The control device becomes the operating mode of the SAM memory arrangement switched from input mode to output mode. In response to a signal activating the SAM memory area the function of the gates is controlled so that any data transmission between the RAM memory array and the SAM Storage arrangement is prevented.

In the present invention is in the read transfer mode of the SAM memory according to the block by which the transfer corresponding, bit-selecting signal corresponding Gate not open. Consequently, data transfer from the RAM memory area to the SAM memory area of this block not happened. At this time, the operation mode of the SAM Memory area switched from input mode to output mode.

As soon as the activating signal of the SAM memory is inactive, becomes the operation mode from the input mode to the output mode switched. This happens on the one that determines the mode of operation Signal out. In response to a transmission signal, all Gates are closed and data is not being removed from the RAM memory area transferred to the SAM memory area.

The masking of any output data bit is corresponding possible.

There are now several ways of teaching the present To design and develop the invention in an advantageous manner. For this, on the one hand, the subordinate claims, on the other hand to the following explanation of Embodiments of the invention with reference to the drawing refer. In conjunction with the explanation of the preferred Embodiments of the invention are based on the drawing  also generally preferred refinements and developments the teaching explained. In the drawing shows

Fig. 1 is a schematic representation of the structure of an image processing system having a multi-port RAM,

Fig. 2 is a schematic representation of the structure of a conventional zweitorigen RAM,

Fig. 3 is a schematic representation of the entire structure of a chip of the conventional zweitorigen RAM,

Fig. 4 a diagram showing the waveform of an operation of a read transfer cycle in zweitorigen RAM,

Fig. 5 a diagram showing the waveform of an operation of a write transfer cycle at a zweitorigen RAM,

Fig. 6 a diagram showing the waveform of an operation of a real-time data transmission in a zweitorigen RAM,

Fig. 7 a diagram showing the waveform of a bitwise write operation in a zweitorigen RAM,

Fig. 8 a diagram showing the waveform of a switching operation from the input mode to the output mode of a SAM-storage area in the RAM zweitorigen,

Fig. 9, the entire structure of a first embodiment of the present invention, namely, a multi-port RAM,

Fig. 10 is a schematic representation of the particular structure of a control circuit used in the multi-port RAM of FIG. 9,

Fig. 11 a diagram showing the waveform of the operation of the circuit shown in Fig. 10,

Fig. 12 is a diagram showing the waveform of the operation of the circuit shown in Fig. 10 and

FIG. 13 shows a further exemplary embodiment of the circuit shown in FIG. 10 in a schematic illustration.

Fig. 9 shows a schematic representation of the entire structure of a multi-port RAM, said structure illustrating an embodiment of the present invention. As an example of a multi-port RAM, FIG. 9 shows a two-port RAM in which a directly accessible input / output port (corresponding to a data buffer 4 ) and a serially accessible port (corresponding to a data buffer 5 ) are provided. The parts corresponding to the conventional two-port RAM shown in FIG. 3 are given the same reference numerals here as in FIG. 3.

The two-port RAM has a four-bit parallel input / output structure. The data buffer 4 used for direct access transmits four bits of input / output data WI 0 to WI 3 in parallel to the outside and inside. The serial access data buffer 5 transmits four bits of input / output data SI 0 to SI 3 to the outside and inside.

According to the four-bit data structure, the transfer gate 1 , the RAM memory cell area 2 , the data register 31 and the serial data switch 32 are divided into four blocks. The transmission gate 1 has four transmission gates T 0 to T 3 . The RAM memory cell area 4 has memory cell blocks M 0 to M 3 . The data register 31 has data registers DR 0 to DR 3 . The serial data switch 32 finally has four serial data switches S 0 to S 3 .

The transfer gate T 0 performs data transfer between the RAM memory cell block M 0 and the data register DR 0 . The transfer gate T 1 performs data transfer between the RAM memory cell block M 1 and the data register DR 1 . The transfer gate T 2 performs data transfer between the RAM memory cell block M 2 and the data register DR 2 . The transfer gate T 3 accordingly carries out data transfer between the RAM memory cell block M 3 and the data register DR 3 . Each of the serial data switches S 0 to S 3 selects corresponding addresses of the data registers DR 0 to DR 3 in accordance with address information from the address pointer 33 .

A control circuit 50 is provided to order the operations of various circuits in the two-port RAM. The control circuit 50 receives various control signals,, /, /, SC and random data WIO _i (i = 0 to 3).

The control circuit 50 generates an internal control signal for controlling various operations of the RAM memory area and the SAM memory area. The control circuit 50 further generates a signal DTWLi (i = 0 to 3) controlling the data transmission for controlling the operation of each of the gates (T 0 to T 3 ) of the transmission gate 1 . Finally, the control circuit 50 generates a signal that defines the input or the output of the data buffer 5 . The signals DTWL 1 to DTWL 3 controlling the data transmission are supplied to the transmission gates T 0 to T 3 . The signal defining the operation mode is fed to the data buffer 5 in order to determine whether the operation mode of the SAM memory area is the serial read mode or the serial write mode. The function is briefly described below.

If the control signals / and both have the level "L" on a falling edge of the control signal in the transition from the level "H" to the level "L", a transmission cycle according to FIGS. 4 and 5 is generally generated. Furthermore, an inner signal DTWL (DTWL 0 to DTWL 3 ) controlling the transmission gate is generated in the form of a single pulse in the region of a rising edge of the control signal / in the transition from level L "to level" H ". Finally, the transmission gates 1 (T 0 to T 3 ) In this phase, data is transferred from the RAM memory cell arrangement 2 to the data register 31 (in the case of the read transfer cycle), when the input or output pin for random data (hereinafter the pin and the signal present there) with the same reference numerals) WIO _i assuming the "H" level in the transmission mode, data is transmitted in the control circuit 50 as shown in Fig. 9 between the blocks associated with the input / output pins, and data transmission in other blocks is prohibited.

If the control signal has the level "H" in the area of the falling edge of the control signal alternating from the level "H" to the level "L", the transmission gates 1 (T 0 to T 3 ) are closed in the control circuit 50 and the data transmission of any bit ( in the directly accessible input / output pin) is prevented.

Fig. 10 shows an embodiment of a circuit for generating the transmission gate control signal DTWLi (i = 0 to 3). This circuit is included in the control circuit 50 as shown in FIG. 9.

Fig. 10 shows that the circuit for generating the control signal Übertragungsgate- DTWLi NOR circuits 200, 210, and NAND circuits 230 and inverter circuits 202, 204, 206 and 232 has. NOR circuit 200 receives the signals and /. The inverter circuits 202, 204 and 206 are cascaded together and form an inversion delay circuit. The NOR circuit 210 receives the signal and an output signal from the NOR circuit 200 and an output signal from the inverter circuit 206 . The NAND gate circuit 230 receives an output signal from the NOR circuit 210 and a data-preventing bit-determining signal that is applied to the directly accessible data input / output pins WIOi. The inverter circuit 232 receives an output signal from the NAND circuit 230 and thus forms the transfer gate control signal DTWLi.

An inverter circuit 212 , p-channel MOS transistors 214, 216 (with insulated gate), n-channel MOS transistors 218, 220 and inverter circuits 222, 224 are provided for determining the operating mode of the SAM memory area (data buffer 5 ). The inverter circuit 212 receives an output signal from the NOR circuit 210 . A line terminal of the p-channel MOS transistor is connected to a supply _potential V _cc . The gate of transistor 214 is connected to an output region of inverter circuit 212 . The p-channel MOS transistor 216 receives the signal WB / WE at its gate. The transistor 216 has a line terminal which is connected to the other line terminal of the p-channel MOS transistor 214 .

The n-channel MOS transistor 218 receives the signal / at its gate and also has a line terminal which is connected to the other line terminal of the p-channel MOS transistor 216 . The n-channel MOS transistor 220 has a line terminal connected to the other line terminal of the n-channel MOS transistor 218 and receives an output signal from the NOR circuit 209 at its gate. This transistor 220 has another line terminal which is connected to the reference potential (ground potential) Vss. The p-channel MOS transistor 216 and n-channel MOS transistor 218 together form an inverter. The p-channel MOS transistor 214 and the n-channel MOS transistor 220 serve to activate the inverter formed by the transistors 216, 218 .

The inverter 222 and the inverter 224 are connected to one another antiparallel and form a blocking circuit. The signal specifying the operating mode is output by the blocking circuit and fed to the data buffer 5 in the SAM memory area. The function of the circuit shown in FIG. 10 is explained below with reference to FIGS. 11 and 12, these FIGS. Showing in diagrams the signal course in the operation in question.

As described above, the transmission cycle is predetermined by bringing the signals / and to the "L" level in the region of the falling edge of the control signal. Whether this is the read transfer cycle or the write transfer cycle is determined at this time depending on the signal /. A signal having the level "H" is output from the NOR circuit 200 while the signals and both are level "L". The inversion delay circuit formed from the inverter circuits 202, 204, 206 delays the output of the NOR circuit 200 by a predetermined time, inverts it and passes it to the input area of the NOR circuit 210 .

The NOR circuit 210 outputs an "H" level signal only when the output of the inverter circuit 206 , the output of the NOR circuit 200 and the signal SE are at the "L" level. As shown in Fig. 11, a single pulse signal is output from the NOR circuit 210 at the "H" level when the signal / level becomes "H". The width of the pulse signal output from the NOR circuit 210 is predetermined by the time delay of the inversion delay circuit having the inverter circuits 202, 204, 206 .

On this occasion, when the data-prohibiting signal WIO _i assumes the level "H", a signal falling to the level "L" is output from the NOR circuit in response to the pulse signal. The inverter circuit 232 inverts the output of the NAND circuit 230 and outputs the control signal DTWLi controlling the transmission gate. Then, the transfer gate of the transfer gate block Ti to which the control signal DTWLi controlling the transfer gate is supplied is opened and the data transfer between the blocks, namely the data transfer from the RAM memory cell block Mi to the data register block DRi, is carried out.

When the signal WIOi (referred to as WIOj in FIG. 11) remains at the "L" level, the output from the NAND circuit 230 is fixed at the "H" level. The control signal DTWLi controlling the transmission gate is not generated and is fixed at the level "L", so that data cannot be transmitted between the blocks defined by the signal WIOj.

When the output of NOR circuit 210 becomes "H" level, p-channel MOS transistor 214 and n-channel MOS transistor 220 become conductive. The signal / inverter circuit (formed from transistors 216, 218 ) is then fed, inverted and fed to inverter circuit 222, 224 . In response to the applied signal, the inverter circuit 222 outputs the signal which specifies the operating mode and stores this signal. If the signal / has the level "H", the signal MODE predetermined for the operating mode also has the level "H", a serial reading mode being defined. When the signal / level is "L", the signal is also at the "L" level, which specifies the serial write mode.

When the signal is at "H" level, the output of NOR circuit 209 is at "L" level. This is the case even if the signal / has the level “L” in the region of the falling edge of the signal as shown in FIG. 12. Therefore, the output of the NAND circuit 230 becomes "H" regardless of the state of the WIOi signal. The signal DTWLi receives the level "L". In this case, the transfer gates 1 are non-conductive for all bits, so that data transfer from the RAM memory cell block 2 into the data register 31 is not carried out. In this case, the signal MODE which specifies the operating mode is kept in a state which it previously had (the inverters formed from the transistors 216, 218 are not activated).

In order to now place the SAM memory area in the read cycle, the control signal is brought to the "L" level, the output of the NOR circuit 210 being given the "H" level. The operation defined by the signal / is then generated as soon as the signal specifying the operation mode and the data buffer 5 have been brought into the input mode or the output mode. As in the prior art discussed above, the signal specifies whether the SAM memory area is active or inactive.

If the signal is not supplied to the NOR circuit 210 , but the inverted signal SE is supplied directly to the NAND circuit 230 as shown in Fig. 10, the signal can be brought into the state dictated by the transmission cycle. This happens regardless of the presence or absence of a data transfer when an instruction for data transfer is generated.

With the structure described above, the SAM memory area can be switched from the input mode to the output mode without performing data transfer from the RAM memory cell arrangement 2 to the data register 31 .

The circuit described above has been discussed as if it directly receives the signals, / and WIOi. With this structure, however, a situation can arise where the states of the signals, / and WIOi erroneously in the area of the falling edge of the signal due to a Time span, parallelogram distortion or due to Signal noise was detected. Likewise, a situation occur where the signal levels of the signals in question the rising or trailing edge of the signal / itself to change.

In order to prevent such possible erroneous operations, a blocking circuit is provided as shown in FIG. 13.

As shown in FIG. 13, a circuit 310 generates a single pulse signal upon falling of the signal to generate a blocking clock. The circuit 310 has three levels of inverters 312, 314, 316 connected in cascade with one another and a NOR gate 318 for receiving an output of the inverter 316 and the signal. The inverter 400 receives an output of the circuit 310 for inversion thereof.

The circuit for the signal has a CMOS (complementary MOS) inverter 350 that responds to the outputs of inverters 400 and circuit 310 . The circuit further has a signal memory 320 consisting of two inverters 322, 324 arranged antiparallel to one another. The inverter 350 has a p-channel MOS transistor 351 that receives the output of the inverter 400 at the gate. Furthermore, the inverter 350 has an n-channel MOS transistor 357 , which receives the output of the circuit 310 at the gate. Finally, the inverter 350 has complementarily connected p-channel and n-channel MOS transistors 353 and 355 , which receive the signal at their gates.

The circuit for the signal / includes an on the outputs of inverters 360 and 310 of the circuit toward responsive inverter 360 and a signal storage 330th The inverter 360 has p-channel MOS transistors 361, 363 and n-channel MOS transistors 365, 367 . The configuration of inverter 360 corresponds to that of inverter 350 . The signal memory 330 has inverters 332, 334 arranged antiparallel to one another.

The circuit for the signal WIOi similarly has an inverter 370 with p-channel MOS transistors 371, 373 and n-channel MOS transistors 375, 377 and a signal memory 340 with inverters 342, 344 arranged antiparallel to one another. The function is now described below.

Circuit 310 generates a single pulse upon falling of the signal. The width of the generated single pulse is determined by the time delay specified by the inverters 312 , 314 and 316 . The generated single pulse causes transistors 351 and 357 , 361 and 367 and 371 and 377 to activate inverters 350, 360 and 370 . Inverters 350, 360 and 370 invert the supplied signals, / and WIOi for transmission to the associated signal memories 320, 330 and 340 . The outputs of the latches 320, 330 and 340 are fed to nodes A, B and C shown in FIG. 10, respectively.

If the single pulse from circuit 310 fails to appear after a predetermined time, inverters 350, 360 and 370 become inactive and the signals stored in latches 320 , 330 and 340 continue to be reliably supplied to nodes A, B and C. The determination of the operation mode and the prevention of data transmission can thus be reliably implemented.

Although above a two-port RAM with the × 4 structure has been described, the same can be done according to the invention Effect with multi-port RAM with other structures, for example a × 1 structure or an × 8 structure or the like realize.

Even if a storage device is a plurality is formed by chip, the same effect can be according to the embodiment described above by Control signal potentials of the chips connected to the respective reach directly accessible input / output pins.

The bit preventing data transmission is used the directly accessible input data / output data pin WIOi  given during the data transfer cycle in the above described embodiment is unnecessary. It however, any other input-output pin can be achieved use the same effect during the data transfer cycle is unnecessary. There are also address input pins, for example in question.

According to the above description, the invention Teach data transfer from the RAM memory area to the SAM memory area in the desired data bit executed when the operation mode of the SAM memory area is switched from input mode to output mode. this happens in that transmission gates on a the data transmission preventing bit can be switched off. Therefore leave the data entered in the SAM input area directly read from the SAM memory area, whereby the function of the SAM Storage area can be checked at high speed can determine whether the SAM memory area is defective.

According to the invention, only a desired bit can be read mask, with a general purpose multi-port RAM can be provided. Furthermore it is possible only a desired image area in the image processing to enroll, creating a storage device with wide Applications for image processing created is.

Furthermore, the data transfer from the RAM Memory area to the SAM memory area when switching from Prevent input mode into the output mode of the SAM memory area, by the temporal link between in the multi-port RAM used control signals is used so that a Multi-port RAM created with a wide range of applications  can be used without additional input / output pins for control to provide.

Although the teaching according to the invention is exemplary and has been explained in detail, the explanations above serve merely the illustration and limit the invention Do not teach. The teaching of the invention is specified solely by the claims.

Claims (11)

1. Multi-port memory with direct or random access, characterized by a memory area (RAM) having a plurality of memory cells ( 2 ) arranged in rows and columns, wherein each of the memory cells ( 2 ) is directly accessible and a number of memory elements ( 31 ) having a memory area (SAM), the memory elements ( 31 ) being able to transmit data simultaneously with a row of the memory cells ( 2 ) of the memory area (RAM) and being able to access each of the memory elements ( 31 ) serially, in the directly accessible memory area and in the serial accessible memory area parallel writing or reading a plurality of bits is possible and wherein the directly accessible memory area and the serially accessible memory area are divided into blocks corresponding to the plurality of bits,
Gate devices ( 1 ; T 0 to T 3 ) for data transmission between the directly accessible memory area and the serially accessible memory area and
a control device ( 50 ) responsive to a signal which specifies the data transmission mode and a signal which prevents the data transmission and which specifies a bit, for preventing data transmission of data from a block of the directly accessible memory area by the gate devices ( 1 ; T 0 to T 3 ) in accordance with the the predetermined data bit preventing the data transmission in the serially accessible memory area. 2. Multi-port memory according to claim 1, characterized in that the control device ( 50 ) has means ( 212, 214, 216, 218, 220, 222, 224 ) which on the signal specifying the data transmission mode and on a signal specifying the operation mode for Creation of a signal (MODE) to determine the mode of operation of the serially accessible memory area. 3. Multi-port memory according to claim 1, characterized in that the control device ( 50 ) has means ( 210, 230 ) which respond to the inactive state of a serial activation signal for activating the serially accessible memory area and that these means ( 210, 230 ) serve to deactivate the gate devices, irrespective of the state of the signal which prevents data transmission and which specifies a bit. 4. Multi-port memory according to claim 2, characterized in that the signal generating means comprise further means ( 214 , 216, 218, 220 ) which respond to the signal specifying the data transmission mode for transmitting the signal specifying the operation mode and that further means ( 222, 224 ) are provided which hold an output signal from the transmitting means and output this held signal, provided that the signal specifying the operating mode is passed to the serial memory area. 5. Multi-port memory according to claim 1, characterized in that the control device ( 50 ) has means ( 200, 202, 204, 206, 210 ), which on a the operation cycle of the directly accessible memory area predetermined first clock signal, the data transmission between the direct accessible memory area and the second accessible clock signal specifying the serially accessible memory area and a third clock signal activating the serially accessible memory area, thereby generating an internal signal specifying the data transmission mode, and in that the control device ( 50 ) has means ( 230, 232 ) for responding to the internal signal which specifies the data transmission mode and the signal which prevents data transmission and which specifies a bit for generating an operation control signal of the transmission gate. 6. Method for operating a multi-port memory with direct access, which has a memory area (RAM), the memory area (RAM) comprising a plurality of row-by-column and column-arranged, directly accessible memory cells ( 2 ) and a memory area (SAM) having a number of memory elements ( 31 ) ), the memory elements ( 31 ) transmitting data simultaneously with a row of the memory cells ( 2 ) of the memory area (RAM) and having serial access to each of the memory elements ( 31 ), with parallel in the directly accessible memory area and in the serial accessible memory area A plurality of bits can be written or read and the directly accessible memory area and the serially accessible memory area are divided into blocks corresponding to the plurality of bits, characterized by the following method steps:
Prevention of a data transfer exclusively from a block of the directly accessible memory area in accordance with the signal specifying a bit preventing the data transfer to a block of the serially accessible memory area in response to a signal specifying the data transfer mode and the signal preventing the data transfer specifying a bit. 7. The method according to claim 6, characterized in that on the signal specifying the data transmission mode and a Operation mode signal indicating the operation mode of the serially accessible memory area defining signal (MODE) is generated.   8. The method according to claim 6, characterized in that the Method step of preventing data transmission Deactivating or switching off all gate devices includes that disabling the inactive state of a serial Activation signal to activate the serial Memory area occurs and that the deactivation regardless of the bit preventing the data transmission Signal occurs. 9. The method according to claim 7, characterized in that the generation of the signal (MODE) the transmission of the ope rations Modus predetermined signal on the data transmission signal specifying the mode as far as holding the transmitted, the operation mode signal and outputting the held signal as the signal specifying the operation mode to the serial memory area. 10. The method according to claim 6, characterized in that the Method step of preventing data transmission - on a first clock signal for determining the operation cycle of the directly accessible memory area - the generation of a second clock signal for specifying a data transmission between the directly accessible memory area and the serial tangible memory area, and - on a third clock signal to activate the serially accessible memory area - generating a data transfer mode setting internal signal and - on the data transfer mode default internal signal and the data transmission preventing a signal indicating a bit - the generation of a comprises the operation of the signal controlling the transmission gate. 11. Multi-port memory with direct or random access, characterized by
a first memory area ( 2 ) having a plurality of memory cells arranged in rows and columns, the memory cells being directly accessible,
a second memory area ( 31 ) having a plurality of memory elements arranged in rows, the line length corresponding to that of the first memory area ( 2 ) and the two memory areas ( 2, 31 ) being subdivided into blocks having columns,
a transmission device for the simultaneous transmission of data between the memory cells of a selected row of the first memory area ( 2 ) and the memory elements of the second memory area ( 31 ),
Means ( 32 ) for serial access to each of the memory elements,
Means ( 50 ) for generating a signal specifying the data transmission mode,
Input means ( 4 ) for inputting a bit-preventing signal and
a control device ( 50 ) for preventing data transmission by the transmission means from a block of the first memory area corresponding to a bit specified by the input means to the second memory area, the control unit ( 50 ) acting on the signal which specifies the data transmission mods and which prevents the data transmission Signal responds.