JPH05225773A - Video ram - Google Patents

Abstract

PURPOSE: To provide a video RAM where data processing speed is improved by executing serial writing transmission more quickly. CONSTITUTION: Data is simultaneously written in all the blocks M'1-M'4 of a serial access memory SAM by the control of a block selecting means 200 which receives a signal from an input buffer 100 at the time of serial writing transmission. After that, the data is selectively transmitted to the blocks M1-M4 of a random access memory RAM, in accordance with a data transmitting signal from a data transmitting signal generating circuit 300.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a dual port memory, and more particularly to a serial access memory (SAM).
mory).

[0002]

2. Description of the Related Art Video RAM (or dual-port dynamic RAM: Dual-port dynamic RAM is used as a memory element of video RAM, and both terms are often mixed in this field. Is a memory having two input / output terminals, a random port and a serial port. Access to the CPU, which is the central processing unit, is random, while access for displaying data on the CRT is serial. Has become. Such a video RAM has functions of serial read transfer and serial write transfer for inputting / outputting serial data. Serial read transmission refers to the operation of transmitting the data stored in the random access memory to the serial access memory and reading the data, and serial write transmission refers to the operation of writing the data to the serial access memory and then writing the data. Is transmitted to and stored in a random access memory. Of these, the serial write transmission is a very important function in the video RAM, and is a function particularly applied to a portion requiring high-speed data processing such as image data processing.

FIG. 5 is a block diagram showing the concept of serial write transmission according to the prior art. The block diagram of FIG. 5 shows serial write transmission, which is widely used in this field, in which a predetermined address is input to the input buffer 10, and the output of the input buffer 10 causes a predetermined block of the serial access memory SAM. The block selection signal generator 20 for selecting is driven.
Then, this block selection signal generator 20 is provided with, for example, four blocks M ′ of the serial access memory SAM.
The control is performed so that the data is written in any one of the blocks 1, 1, M'2, M'3, and M'4. At this time, data is input to the serial access memory SAM from a data input buffer (not shown). This situation is shown in Figure 5.
Is shown in. The block diagram on the left side of FIG. 5 shows a state in which writing is executed in the block M′1 of the serial access memory SAM. After writing to the block M′1, as shown in the block diagram on the right side of FIG.
The data is transmitted by the data transmission gate 1 to the block M1 of the random access memory RAM.

FIG. 6 shows a process of subsequently performing serial write transmission to another block of the random access memory RAM. That is, when the serial write transmission is continuously executed to the block M2 of the random access memory RAM, the data is written to the block M'2 of the serial access memory SAM this time by the control of the block selection signal generator 20 again. Then, through the data transmission gate 1, the random access memory RA
The data is transmitted to the block M2 of M, and the serial write transmission is executed.

As described above, according to the conventional serial write transmission, in order to execute the serial write transmission to the i blocks of the random access memory, the data is written to one block of the serial access memory. After that, the data is transmitted to one block of the random access memory, and then the data is written to one block of the serial access memory again, and then the data is transmitted to one block of the random access memory. Thus, it is necessary to repeat the data writing / transmission process i times. This is a major obstacle when high-speed data processing such as image processing is required, and the next-generation ASIC (application specific IC: which must process a large amount of data at high speed).
This is a problem that must be solved by a special-purpose IC) memory such as a video RAM, a field memory, and a graphic memory.

[0006]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a video RAM capable of executing serial write transmission quickly and processing data at a higher speed.

[0007]

In order to achieve such an object, the present invention provides m (m = 1, 2, 3, ...) Rows, n.
(N = 1, 2, 3, ...) Column-shaped matrix memory cells (N = 1, 2, 3, ...) M (M = 1, 2, 3, ...) …) Random access memory having blocks and M blocks each composed of a memory cell group in the form of one row and n columns, each block being a block of the random access memory. In a video RAM provided with a serial access memory connected thereto, all M blocks of the serial access memory are enabled and written symmetrically by the control of a block selection means for performing block selection control of the serial access memory during serial write transmission. After writing the data to all the blocks, the corresponding blocks of the random access memory are written according to the data transmission signal. It is characterized by being adapted to transmit over data.

Further, the block selection means for performing such control uses the data transmission enable signal as a common control signal, and transmits the block selection signal and the write enable signal respectively according to the data transmission enable signal. A two-input circuit, a first latch circuit and a second latch circuit for latching respective output signals of the first input circuit and the second input circuit, and an output signal of the first latch circuit and the second latch circuit are input. A first NAND circuit, a second NAND circuit which receives an inverted signal of the output signal of the first latch circuit and an output signal of the second latch circuit, and a first NA
The first transmission circuit and the second transmission circuit which read out and output the respective output signals of the ND circuit and the second NAND circuit under the control of the transmission enable signal, and the respective output signals of the first transmission circuit and the second transmission circuit are latched. Third latch circuit and fourth
And a latch circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. The same parts as those of the conventional technique are designated by the same reference numerals, and the duplicated description will be omitted. FIG. 1 shows a circuit diagram of an embodiment of the block selection means provided for serial write transmission according to the present invention, and FIG. 2 shows an operation timing chart thereof. 3 is a flowchart showing the concept of serial write transmission according to the present invention.

In the block selecting means shown in FIG. 1, the data transmission enable signal φDTE is commonly input as a control signal, and the first and second input circuits TM for transmitting the block selection signal BLSC and the write enable signal φWTE, respectively.
1, TM2, first and second latch circuits L1 and L2 for latching respective output signals of the first and second input circuits TM1 and TM2, and outputs of the first and second latch circuits L1 and L2 A first NAND gate 37 that receives a signal, and a second NAND gate 3 that receives the inverted signal of the output signal of the first latch circuit L1 and the output signal of the second latch circuit L2.
8 and the first and second transmission circuits TM3 and TM4 for transmitting the respective output signals of the first and second NAND gates 37 and 38 under the control of the read transmission enable signal φRTE,
Third and fourth latch circuits L3 and L for latching and outputting the output signals of the second transmission circuits TM3 and TM4, respectively.
4 and. Inverters 40 and 43 are provided at the output terminals of the third and fourth latch circuits L3 and L4, respectively, and the third and fourth latch circuits L are also provided.
Initial value setting transistors 46 and 47, which are commonly controlled by the initial value setting signal φINT, are provided to set the initial values of the output terminals of 3 and L4 to logic "low".

When the data transmission enable signal φDTE becomes a logic "high", the block selection signal BLSC and the write enable signal φWTE are passed through the first and second input circuits TM1 and TM2, respectively, to the first and second latch circuits L1 and L.
2 is transmitted. The first and second latch circuits L1 and L2 are
Block select signal BLSC and write enable signal φW
TE and L are respectively latched, the data transmission enable signal φDTE becomes logic "low", and the first and second input circuits T
Even if M1 and TM2 are turned off, the initial input state is continuously maintained. Then, the output signals of the first and second latch circuits L1 and L2 are input to the third and fourth transmission circuits TM3 and TM4 via the NAND gates 37 and 38.
At this time, when the read transmission enable signal φRTE is in the “low” state, the third and fourth transmission circuits TM3 and TM4
Is turned on, and the output signals of the first and second latch circuits L1 and L2 are transmitted to the third and fourth latch circuits L3 and L4, respectively. Then, the third and fourth latch circuits L3 and L4
Latches the output signals of the first and second latch circuits L1 and L2, respectively, and maintains the initial input state even when the third and fourth transmission circuits TM3 and TM4 are turned off.
The initial value setting transistors 46 and 47 are turned "on" when the initial value setting signal φINT is at the power supply voltage level, and the initial states of the output terminals of the third and fourth latch circuits L3 and L4 are set to logical "low". Set. The output signals of the third and fourth latch circuits L3 and L4 pass through inverters 40 and 43 and block selection information signals φBS1 and φBS for selecting a block of the serial access memory SAM (FIG. 4).
It is output as 2.

In order to execute the serial write transmission as described above, the block selection information signal φBS1 is supplied to the blocks M'1 and M'3 of the serial access memory SAM (FIG. 4).
Block selection information signal φBS
2 connects to select blocks M'2, M'4 (FIG. 4). In addition, when the data transmission enable signal φDTE and the write enable signal φWTE are input at the logic “high”, the block selection means is the block selection signal BL.
All blocks of the serial access memory SAM are selected regardless of SC.

FIG. 2 is an operation timing chart of the block selecting means of FIG. 1 when executing the serial write transmission. Data transmission enable signal φD of logic "high" respectively
When TE and the write enable signal φWTE are input, the signals passed through the NAND gates 37 and 38 become logic "high" at points A and B regardless of the state of the block selection signal BLSC. The signal is further transmitted to the third and fourth transmission circuits TM.
It becomes a logic "low" at the points C and D via the third and fourth latch circuits L3 and L4. Then, the signals pass through the inverters 40 and 43 to become block selection information signals φBS1 and φBS2 which are logic "high", respectively, and as a result, the blocks M'1 to M'1 of the serial access memory SAM.
All of M'4 are selected.

A data transmission process to the random access memory using the block selecting means will be described with reference to the flow chart of FIG. After writing (24) to all the blocks of the serial access memory SAM by the block selecting means of FIG. 1, the block to be transmitted is selected (25) by the block selection signal BLSC,
Subsequently, when the data transmission signal φDTP for data transmission to the random access memory RAM is enabled (26), the serial access memory SA is accordingly instructed.
The data written in M is the random access memory RA
It is selectively transmitted (27) to M.

In order to facilitate understanding of the flowchart of FIG. 3, FIG. 4 shows a block diagram corresponding to FIG. When the serial writing is started, as described above, all the blocks M'of the serial access memory SAM are processed by the block selecting means 200 such as the circuit of FIG.
1, M'2, M'3, M'4 (in FIG. 4, a video RAM having four random access memory RAMs, for example) is selected, and a data input buffer (not shown) is selected. Data is written to each block via. Thereafter, the data is selectively transmitted to the random access memory RAM according to the data transmission signal φDTP output from the data transmission signal generator 300. In this way, serial write transmission is easily performed.

The embodiment shown in FIG. 1 is an example for realizing the idea of the present invention, and the present invention is not limited to this, and it goes without saying that different configurations can be made if similar signal processing can be performed. ..

[0017]

As described above, according to the present invention, when the serial write transmission is performed, the data is collectively written in all the blocks of the serial access memory, so that the serial write transmission can be performed more quickly. As a result, the data processing speed is improved. As a result, it can greatly contribute to the realization of the demand for higher-speed, large-volume data processing such as the next-generation ASIC.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a block selecting means according to the present invention.

2 is an operation timing chart of the circuit of FIG. 1 during serial write transmission.

FIG. 3 is a flowchart of serial write transmission according to the present invention.

FIG. 4 is a block diagram illustrating a block selection process of serial write transmission according to the present invention.

FIG. 5 is a block diagram illustrating a block selection process of serial write transmission according to a conventional technique.

FIG. 6 is a block diagram illustrating a block selection process of serial write transmission according to a conventional technique.

[Explanation of symbols]

 φDTE data transmission enable signal φWTE write enable signal BLSC block selection signal φRTE read transmission enable signal φBS1, φBS2 block selection information signal φDTP data transmission signal φINT initial value setting signal TM1 first input circuit TM2 second input circuit L1 first latch circuit L2 Second latch circuit 37 First NAND circuit 38 Second NAND circuit TM3 First transmission circuit TM4 Second transmission circuit L3 Third latch circuit L4 Fourth latch circuit 46, 47 Initial value setting transistor

Claims (5)

[Claims] 1. m (m = 1, 2, 3, ...) Rows, n (n =
N (N) in the form of a matrix of 1, 2, 3, ...
= 1, 2, 3, ...) Random access memory having M (M = 1, 2, 3, ...) Blocks each composed of a memory cell group, and one row and n columns. A video RAM having M blocks each composed of a memory cell group, each block being connected to each block of the random access memory, and a serial access during serial write transmission. After the data is written in all the write symmetrical blocks with all the M blocks of the serial access memory being enabled by the control of the block selecting means for performing the block selection control of the memory, the corresponding block of the random access memory according to the data transmission signal. Video R, characterized in that it is adapted to transmit said data to AM. 2. The block selection means uses a data transmission enable signal as a common control signal, and transmits a block selection signal and a write enable signal respectively according to the data transmission enable signal, and a first input circuit and a second input circuit, A first latch circuit and a second latch circuit for latching respective output signals of the 1-input circuit and the 2nd input circuit;
A first NAND circuit receiving the output signals of the first latch circuit and the second latch circuit as inputs; a second NAND circuit receiving the inverted signal of the output signal of the first latch circuit and the output signal of the second latch circuit; 1 NAND circuit and 2nd NAN
A first transmission circuit and a second transmission circuit for transmitting each output signal of the D circuit under the control of a read transmission enable signal;
The video RAM according to claim 1, further comprising a third latch circuit and a fourth latch circuit for latching respective output signals of the transmission circuit and the second transmission circuit. 3. The video RAM according to claim 2, wherein the first input circuit, the second input circuit, the first transmission circuit, and the second transmission circuit are configured by transmission gates. 4. A first latch circuit, a second latch circuit, and a third latch circuit.
The video RAM according to claim 2, wherein the latch circuit and the fourth latch circuit are constituted by CMOS inverters connected in parallel in opposite directions. 5. The video RAM according to claim 2, wherein the block selection means includes an initial value setting transistor under the control of the initial value setting signal at each output terminal of the third latch circuit and the fourth latch circuit. ..