JPH10210242A - Data sequence conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data sequence conversion circuit capable of being configured at a low cost without using a FIFO circuit. SOLUTION: A data selection circuit 36 provides outputs of skipped data such as 0, 3000, 6000, 9000,... one by one each and the skipped data are stored in skipped address in an SRAM 40, then when all the skipped data are finished for output from the data selection circuit 36, data of 0 to 14999 are stored in consecutive addresses in the SRAM 40 and the consecutive addresses of the SRAM 40 are accessed continuously and the data of 0 to 14999 stored in the addresses are read continuously to convert the parallel data divided by 3000 each are converted into the continuous data of 0 to 14999.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data order conversion circuit used in a copying machine or the like.

[0002]

2. Description of the Related Art In a copying machine, information on an object to be copied is represented by L.
When a line is read by the ED and the CCD, as shown in FIG.
Divided into five areas, five CCDs 11, 12, 13, 1
Read at 4,15. Therefore, assuming that the total number of read data on one line is 15000, FIG.
As shown in FIG.
No. 3000 to 5999 from the second CCD 12,
From the third CCD 13, the 6000th to 8999th, the fourth
No. 9000 to 11999 and the fifth CCD 15 output data of 12000 to 14999. At this time, in detail, first, as shown in FIG. 6, the number 0, 3000, 6000, 9000,
12000 No. 4 data is 1st to 5th CCD
Are output in parallel from 11 to 15, then the first, 3001
No. 4, No. 6001, No. 9001, and No. 12001 are output in parallel from the first to fifth CCDs 11 to 15, and thereafter, the four data are shifted one by one and the four data are output from the first to fifth CCDs 11 to 15. Output in parallel from
Finally 2999, 5999, 8999, 1199
Four data Nos. 9 and 14999 are output in parallel from the first to fifth CCDs 11 to 15.

Therefore, the first to fifth CCDs 11
In order to send the data output from .about.15 to the subsequent processing circuit, the above-mentioned divided parallel data output from the first to fifth CCDs 11 to 15 are converted into information on one line of the copy 16. It is necessary to convert the data into continuous serial data of No. 0 to 14999 corresponding to and transmit the data.

Therefore, a data order conversion circuit is provided, and FIG. 7 shows a conventional data order conversion circuit. This conventional circuit includes first to fifth FIFOs (firsts
t-in first-out) circuits 21, 22, 2
3, 24, and 25, and the first FIFO circuit 21 stores data from the first CCD to the 0th to 2999th data and the second F
No. 3000 to 599 from the second CCD to the IFO circuit 22
The 9th data, the third FIFO circuit 23 stores the third CCD
From 6000 to 8999, 4th FIFO
The circuit 24 is supplied with the 9000th to 1999th data from the fourth CCD, and the fifth FIFO circuit 25 is supplied with the 12000th to 14999th data from the fifth CCD.

[0005] As described above, the conventional circuit is numbered 0 to 299.
The ninth data is stored in the first FIFO circuit 21,
The 5999th data is transferred to the second FIFO circuits 22 and 600
The 0th to 8999th data is transferred to the third FIFO circuit 23,
The 9000th to 11999th data are supplied to a fourth FIFO circuit 24, the 12000th to 14999th data are supplied to a fifth FIFO circuit 25, and these data are temporarily stored in a FIFO memory.
After the data is stored in the O circuits 21 to 25, first, the first FIFO circuit 21 is operated to output the 0th to 2999th data to the common output terminal 26, and then the second FIFO circuit 22 is operated. And outputs the 3000th to 5999th data to the common output terminal 26, and then operates the third FIFO circuit 23 to output the 6000th to 8999th data to the common output terminal 2.
6 and then the fourth FIFO circuit 24 is operated to output the 9000th to 11999th data to the common output terminal 26.
, And then the fifth FIFO circuit 25 is operated to
The 2000th to 14999th data are output to the common output terminal 26
, The numbers 0 to 2999, 3000 to 5999, 6000 to 8999, 9000 to
11999 No., 12000 No. to 14999 No. parallel data
The data is converted into serial data of No. 0 to No. 14999.

[0006]

However, the conventional data sequence conversion circuit as described above has a problem in that it is expensive because a FIFO circuit is used, and the appearance of an inexpensive data sequence conversion circuit is desired. ing.

[0007]

According to the present invention, in order to solve the above-mentioned problems, the present invention repeats the sequential output of discrete data obtained from a plurality of continuous data one by one, and finally, the continuous data is output. A data selection circuit that outputs all of the plurality of data, and the intermittent data output from the data selection circuit are sequentially stored in corresponding intermittent addresses, so that the plurality of continuous Data order conversion comprising: a storage circuit for storing data; and means for continuously accessing an address of the storage circuit and sequentially reading the plurality of continuous data stored on continuous addresses. Circuit. Here, the data selection circuit can be composed of a plurality of flip-flop circuits. The storage circuit is an SRAM (Static Random Access).
Memory)

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a data order conversion circuit according to the present invention; FIG. 1 is a circuit diagram showing an embodiment of a data order conversion circuit according to the present invention. In this figure, reference numeral 36 denotes a data selection circuit, which includes first to fifth flip-flop circuits (hereinafter, referred to as FF circuits) 31, 32, 33, 34, and 35. The first to fifth FF circuits 31, 32,
The clock signal CLK1 is commonly supplied to 33, 34, and 35 from the control circuit 37, and the output enable signals OE31 to OE35 enabling output are individually supplied from the control circuit 37. Also, the first FF circuit 31
Is input from the first CCD 11 in FIG.
5 is input to the second FF circuit 32 from the second CCD 12 in FIG. 5, and the data of No. 3000 to 5999 is input to the third FF circuit 33.
13th to 6000th to 8999th data are stored in the fourth F
The input to the F circuit 34 is from the fourth CCD 14 to 90 in FIG.
The data No. 00 to No. 11999 are stored in the fifth FF circuit 35.
Is input from the fifth CCD 15 in FIG.
The 14999th data is supplied.

On the other hand, the first to fifth FF circuits 31 to 3
5 are commonly connected to each other to provide an SRAM serving as a storage circuit.
40 data input / output terminals DS. This SRA
M40 is a PLD (Programmable Log)
ic Device) upper address counter 4 in 38
1 and the address is specified by the lower address counter 42. The address counters 41 and 42 include the control circuit 3
7 supplies an upper address counter control signal CCU and a lower address count control signal CCL. SRAM4
The control circuit 37 supplies a read / write control signal SRW to 0. The data input / output terminal DS of the SRAM 40 is connected to the input of the output FF circuit 43 in the PLD 38. The clock signal CLK5 is supplied from the control circuit 37 to the address counters 41 and 42 and the output FF circuit 43. The clock signal CLK5 requires a frequency that is equal to or greater than the parallel number of input data (five times in this example) with respect to the clock signal CLK1. Output F
The output of the F circuit 43 is connected to the output terminal DO.

The data order conversion circuit constructed in this manner is provided by the data selection circuit 36 from the 0th, 3000th, and 60th.
The data is output one by one such as No. 00, No. 9000,...
The corresponding discrete addresses on M40 (address 0, 30
00, 6000, 9000,...) At the stage when all the discrete data has been output from the data selection circuit 36.
The 999th data is stored on the corresponding continuous addresses (addresses 0 to 14999) on the SRAM 40, and then the continuous addresses (0
(Addresses to 14999) are successively accessed, and the data of 0 to 14999 stored on this address are continuously read, whereby the addresses of 0 to 2999,
3000th to 5999th, 6000th to 8999th, 9
This is to convert the parallel data divided into Nos. 000 to 11999 and Nos. 12000 to 14999 into continuous serial data of Nos. 0 to 14999.

The operation will be described in detail below. The first to fifth FF circuits 31 to 35 of the data selection circuit 36 are connected to the first to fifth CCDs 11 to 15 of FIG.
First, as shown in FIG.
No. 000, No. 12000 are supplied in parallel, then No. 1, No. 3001, No. 6001, No. 9001,
Four pieces of data No. 12001 are supplied in parallel, and then four pieces of data are supplied in parallel while being shifted one by one. Finally, No. 2999, No. 5999, No. 8999, and No. 11
999 and 14999 data are supplied in parallel.

The first to fifth FF circuits 31 to 35
Means that the output enable signals OE31 to OE35 are changed to the output enable signals OE31, OE32, OE33,
Since the operation levels are sequentially set in the order of OE34 and OE35,
The first, second, third, fourth, and fifth FF circuits 31, 32,
The four parallel data are sequentially output one by one in the order of 33, 34, 35. As a result, from the data selection circuit 36, as shown in FIG.
No. 00, No. 12000, No. 3001,... 89
No. 98, 11998, 14998, 2999, 5
Data is output one by one in the order of 999, 8999, 11999, and 14999.

At this time, in the SRAM 40, discrete addresses are sequentially designated by the combination of the upper address counter 41 and the lower address counter 42 in correspondence with the numbers of the output data. To explain this point in detail, first, the lower address counter 42 for specifying the lower 3 digits of the address is set to “00” as shown in FIG.
In the state of "0", the upper address counter 41 for designating the upper two digits of the address becomes "0", "3", "6", "9", and "12" in order as shown in FIG. As a result, addresses 0, 3000, 6000, 9000, and 12000 are sequentially addressed as shown in FIG. 3C. Next, the lower address counter 4
In a state where 2 is “001”, the upper address counter 41 sequentially counts “0”, “3”, “6”, “9”, and “12”.
Therefore, addresses 1, 3001, 6001, 9
Addresses 001 and 12001 are sequentially addressed. Thereafter, the lower address register 42 is incremented by 1 up to “999”, and each time, the upper address counter 41 repeats “0”, “3”, “6”, “9”, and “12” in order. An intermittent address corresponding to the intermittent data number is further specified, and then the lower address counter 42 returns to “000” and returns to “999” again.
The upper address counter 41 increments by one each time, and this time, the upper address counter 41 sequentially indicates “1”, “4”, “7”, “10”,
By repeatedly changing to "13", intermittent addresses corresponding to intermittent data numbers are further specified, and thereafter, the lower address counter 42 repeats "0".
Returning to "00" and increasing three times to "999" three times, the upper address counter 41 for each value is sequentially changed to "2", "5", "8", "11", and "14" in this order. The intermittent address corresponding to the intermittent data number is repeatedly designated.

Such discrete address designation corresponds to the discrete number of the data output from the data selection circuit 36 as described above. Therefore, the discrete data output from the data selection circuit 36 is: SRA
Stored on the corresponding discrete address on M40,
In the state where all data has been stored, numbers 0 to 1
The data of 4999 is from address 0 of SRAM 40 to 1499
It is stored on consecutive addresses at address 9.

Next is a read cycle. In the read cycle, the contents of the upper address counter 41 are sequentially set to “0”, “1”, “1”, as shown in FIG.
The contents of the lower address counter 42 repeat “000” to “999” as shown in FIG. 4B with each numerical value while “2”, “3”... “13”, “14”. Therefore, the SRAM 40 stores addresses 0 to 14999.
The addresses are addressed sequentially. As a result, SRA
From M40, 0 stored in addresses 0 to 14999
No. to No. 14999 are continuously read out as shown in FIG. 4C, and are further output to the output terminal DO via the output FF circuit 43 as shown in FIG. .

As described above, the numbers 0 to 2999, 3000 to 5999, and 60 supplied to the data selection circuit 36
00th to 8999th, 9000th to 11999th, 12
The 000th to 14999th divided parallel data are converted to the 0th to 14999th continuous serial data.

Since the data order conversion circuit as shown in FIG. 1 is composed of FF, SRAM and PLD,
Compared to the case where a conventional FIFO circuit is used, the cost is lower.

[0018]

As described above, according to the data order conversion circuit of the present invention, the FIFO circuit is not used and the cost is low.
It can be used for various devices including copying machines.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data order conversion circuit according to the present invention.

FIG. 2 is a diagram showing data output from a data selection circuit.

FIG. 3 is a diagram showing a relationship between contents of an address counter and a write address of an SRAM.

FIG. 4 is a diagram showing a relationship between contents of an address counter and read data.

FIG. 5 is a schematic diagram showing a state in which a copy is read by a CCD.

FIG. 6 is a view showing read data from a CCD.

FIG. 7 is a circuit diagram showing a conventional data conversion circuit.

[Explanation of symbols]

 36 data selection circuit 31-35 first through fifth FF circuits 37 control circuit 40 SRAM 41 upper address counter 42 lower address counter

Claims (3)

[Claims] 1. A data selection circuit for repeatedly outputting, one by one, discrete data obtained from a plurality of continuous data, and finally outputting all of the plurality of continuous data; A storage circuit for storing the plurality of continuous data on finally continuous addresses by sequentially storing the discrete data output from the And a means for sequentially reading the plurality of pieces of continuous data stored on continuous addresses. 2. The data order conversion circuit according to claim 1, wherein the data selection circuit comprises a plurality of flip-flop circuits. 3. The data order conversion circuit according to claim 1, wherein the storage circuit is an SRAM (Static Land).
om Access Memory).