JP2012008841A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor capable of freely rearranging image data outputted from a line sensor such as a CCD, a CIS, a CMOS, or the like which is different in output orders of the image data.SOLUTION: The image processor includes: image data input terminals 26 to 29 for dividing image data read by the line sensor into one or more channels to input the image data; a two-port RAM 1 for storing the inputted image data; lookup tables 8 to 11 for indicating a specific memory address of the two-port RAM 1 to write the inputted image data into the memory address; image data writing means for writing the inputted image data into the indicated memory address of the two-port RAM 1; and image data reading means for reading the image data written in the two-port RAM 1 in a memory address order.

Description

  The present invention relates to data processing of image data read by a line sensor such as a CCD, CIS, or CMOS sensor in an image processing apparatus such as a copying machine, a facsimile, or a scanner.

  Conventionally, in order to input image data read by a CCD or CIS (contact image sensor) and perform the data processing, first, the CCD or CIS to be used is determined, a dedicated circuit for these devices is created, and the image is processed. We have designed data reading and sorting circuits. The reason for creating a device-dedicated circuit is that the configuration of a device such as a CCD, CIS, or CMOS sensor changes depending on the manufacturer and the processing speed of the device. For example, when a CCD is used as a reader such as a high-speed copier having a reading performance of 80 sheets / minute, the image data read clock cannot be raised. Therefore, in order to maintain the performance of the CCD, image data from the CCD is used. Needs to be divided and read (for example, divided into four). On the other hand, a reader such as a medium-speed copying machine having a reading performance of 40 sheets / minute generally uses a low-cost CCD that can be read in two divisions because the image data read clock has a margin. . Furthermore, many CMOS sensors capable of high-speed reading have many different read data structures from those of the CCD. Regarding the capacity of the storage device used for rearranging the image data, for example, Patent Document 1 proposes a method of rearranging image data from the image sensor using a storage device having a small capacity.

JP-A-6-189080

  CCD, CIS, CMOS, etc. are used for the line sensor of the reader of the copying machine. However, since the output order of image data differs depending on the type of these line sensors, an image processing circuit for rearranging the image data must be designed for each type of line sensor. A processing circuit is desired. In addition, it is generally difficult to cope with a small change in the specifications of the sensor, and there is a problem that the degree of freedom in design is impaired when the specification of the sensor is changed or when it is replaced with an inexpensive device.

  The present invention has been made under such circumstances, and an image in which image data output from line sensors having different output order of image data such as CCD, CIS, and CMOS can be freely rearranged. The object is to provide a processing apparatus.

  In order to solve the above problems, in the present invention, an image processing apparatus is configured as follows.

  Image data read by the line sensor is divided into one or a plurality of channels and input, and image data storage means for storing the image data input from the image data input terminal; After the input image data is written in the image data storage means, when the image data is read out from the image data storage means in the order of memory addresses, the image data rearranged in the order of the image positions read by the line sensor is read out. The memory address indicating means for instructing the memory address to be written in the image data storing means, and the input image data is written in the memory address of the image data storing means instructed by the memory address indicating means. Image data writing means and the image data storage means By reading the image data incorporated come to order memory address, an image processing apparatus having a, image data reading means for performing the reordering of the image data input from the image data input terminal.

  According to the present invention, the image processing apparatus freely rearranges image data output from line sensors having different output order of image data such as CCD, CIS, and CMOS by changing the control of the lookup table. be able to. Further, the common platform of the ASIC equipped with the circuit of the present invention makes it possible to reduce the development man-hours and standardize the design, and it is easy to cope with changes in the image reading device to be used.

Circuit block diagram of Embodiment 1 Write timing chart of image data of embodiment 1 Image Data Reading Timing Chart of Embodiment 1 The lookup table of Example 1, The figure which shows the data structure of input image data Circuit block diagram of embodiment 2 Example 2 Image Data Writing / Reading Timing Chart Circuit block diagram of embodiment 3 Circuit block diagram of lookup table of embodiment 4 The figure which shows the operating condition of the look-up table of Example 4. The figure which shows the example of data of the look-up table of Example 4. Device block diagram of medium / high speed machine of embodiment 4, structure diagram of input image data The figure which shows the example of data of the look-up table of the medium / high-speed machine of Example Circuit block diagram of lookup table of embodiment 5 Circuit block diagram of embodiment 5 The figure which shows the example of data of the lookup table of Example 5.

  Hereinafter, the form for implementing this invention is demonstrated in detail by an Example.

  FIG. 1 shows a circuit block diagram of the first embodiment. The first embodiment is a circuit that rearranges data when image data divided into four channels as the number of input channels is simultaneously input from an external CCD that is one of line sensors.

  First, the circuit connection relation will be described with reference to FIG. The digital data input terminals 26 to 29 are image data input terminals through which analog data read by the external CCD is AD converted by an analog processor and input as digital data. One digital data is usually composed of 8 to 10 bits. The digital data input terminals 26 to 29 are connected to input terminals of latch circuits 14 to 17 each composed of a flip-flop. The look-up tables 8 to 11 store specific address information of a 2-port RAM (dual port RAM) 1 serving as image data storage means for writing the digital data latched in the latch circuits 14 to 17. The data in the look-up tables 8 to 11 is configured such that address information corresponding to the counter value of the counter 13 is output. The look-up table 8 and the output terminal of the latch circuit 14 are connected to the input terminal of the latch circuit 22 composed of a D-type flip-flop. Similarly, the output terminals of the lookup tables 9 to 11 and the latch circuits 15 to 17 are connected to the input terminals of the latch circuits 23 to 25, respectively. Further, the divide-by-4 output terminal of the frequency division / waveform generation circuit 12 is connected to clock input terminals of the latch circuits 22 to 25 and also to a feedback terminal of the PLL control circuit 21. The VCO output (VCO_OUT) terminal of the PLL control circuit 21 is connected to the clock input terminal of the frequency division / waveform generation circuit 12.

  The look-up tables 8 to 11 can allocate the same RAM to one table, and the same operation is possible with a total of four RAM configurations. However, in the following embodiments, the RAM is configured with one RAM. Will be described. Similarly, the counter 13 can operate even if four counters are individually provided. However, in the following embodiments, the counter 13 is configured as one binary counter. Although a data input terminal for writing data to the lookup tables 8 to 11 and a data writing control terminal are actually provided, they are not shown. When the lookup tables 8 to 11 are ROM, they are written in advance on the mask as bit information, and can be easily rewritten as a mask option if necessary. A WEB (write enable) terminal 30 is connected to the control signal input terminals of the look-up tables 8 to 11.

  The output terminals of the latch circuits 22 to 25 are connected to the input terminals of the selector circuits 4 to 7. The output terminals of the selector circuits 4 to 7 are connected to the bus line 3, and the bus line 3 is connected to the write data input terminal and the write address input terminal of the 2-port RAM 1. The control signal input terminals of the selector circuits 4 to 7 are connected to the A, B, C, and D signal output terminals of the frequency dividing / waveform generating circuit 12, respectively. The write clock input terminal of the 2-port RAM 1 is connected to the VCO output terminal of the PLL control circuit 21. The read address input terminal of the 2-port RAM 1 is connected to the count output terminal of the address counter 2, and the clock input terminal of the address counter 2 and the read clock input terminal of the 2-port RAM 1 are connected to the RCLK input terminal 19. A read enable (READ_ENABLE) input terminal 18 is connected to a count enable input terminal of the address counter 2 and a REB (read enable) terminal of the 2-port RAM 1. The WEB terminal 30 is connected to the WEB input terminal of the 2-port RAM 1 and also to the EN terminal of the counter 13. A CLK terminal 31 is connected to the CLK terminal of the PLL control circuit 21. The read data output terminal of the 2-port RAM 1 is connected to the read data (read_DATA) output terminal 20.

  Next, the operation of this embodiment will be described. FIG. 2 shows a timing chart for explaining the operation. When the CLK waveform signal of FIG. 2 is input from the CLK terminal 31 of the circuit of FIG. 1, the PLL control circuit 21 incorporating the VCO and the frequency division / waveform generation circuit 12 constitute a feedback loop and operate as a PLL. As a result, the phase of the input signal from the CLK terminal 31 and the signal output from the divide-by-4 output terminal of the divider / waveform generating circuit 12 are synchronized, and each of the A, B, C, D, and PLL_OUT terminals is connected to FIG. The signal shown in FIG. Further, as shown in FIG. 4A, the look-up tables 8 to 11 output memory address information of the 2-port RAM 1 corresponding to the counter value of the counter 13 designating the table address to the latch circuits 22 to 25. . In FIG. 4A, odd (odd pixel column) and even (even pixel column) data that are generally used are further divided into two parts, the first half and the second half, and the image data divided into four as a whole is obtained. The data example of the look-up table at the time of using CCD to output is shown.

  The clock input of the counter 13 is synchronized with the data rate input to the digital data input terminals 26 to 29 and is also a clock input to the feed_BACK terminal of the PLL control circuit 21. After the WEB terminal 30 falls from the HIGH level (hereinafter referred to as “H”) to the LOW level (hereinafter referred to as “L”), the counter 13 and the look-up tables 8 to 11 are enabled to operate. Start. Image signals input from the digital data input terminals 26 to 29 are latched by the latch circuits 14 to 17, respectively. Then, the counter 13 is counted up so that address information corresponding to each image data is read from the look-up tables 8-11. The image data latched in the latch circuits 14 to 17 and the memory address instruction data read from the look-up tables 8 to 11 for writing the image data in the 2-port RAM 1 are simultaneously sent to the latch circuits 22 to 25. Latched.

  Next, the memory address instruction data and the image data latched by the latch circuits 22 to 25 are time-divisionally passed through the selector circuits 4 to 7 and the data write memory address input terminal and data input terminal of the 2-port RAM 1. Is input. As a result, the image data is written to the designated memory address of the 2-port RAM 1 at the falling edge of the PLL_OUT signal. After all the image data is written in the 2-port RAM 1, the read enable input terminal 18 changes from H to L, and a clock is input to the address counter 2 from the RCLK input terminal 19. The address counter 2 is enabled, the counter value is counted up sequentially from 0, and the read data output terminal 20 of the 2-port RAM 1 is arranged in the order of the memory address in accordance with the counter value of the address counter 2. Data is output.

  A specific image data writing timing chart is shown in FIG. 2, and an image data reading timing chart is shown in FIG. 2 and 3, it can be seen that the writing operation and the reading operation of the image data to the 2-port RAM 1 are not performed at the same time, and the writing and reading timings are mutually exclusive. The counter 13 is configured so that the count value is always 0 when the WEB terminal 30 is H, and the address counter 2 is configured so that the count value is always 0 when the read enable input terminal 18 is H. ing. An example of input image data read from the CCD in this embodiment is shown in FIG. The data in this table is output from the CCD simultaneously for each column from the top to the bottom of the table in synchronization with the clock at the CLK terminal 31, and via the digital data input terminals DIN1, DIN2, DIN3, and DIN4. Entered. Also, the input image data shown in FIG. 4B is written to the address of the 2-port RAM 1 shown in FIG.

  As described above, the image data from the line sensor divided into 4 channels is written to the address of the 2-port RAM indicated by the lookup table, and the image data is read out in the order of the memory addresses, thereby rearranging the image data. It can be performed.

  FIG. 5 is a circuit block diagram showing the present embodiment. In this embodiment, a 2-port RAM 32, an address counter 33, gate circuits 36 and 37, and a line counter circuit 38 are added to FIG. 1 of the first embodiment. Below, the description of the same part as Example 1 is abbreviate | omitted, and it demonstrates in detail about the added changed part.

  First, the circuit connection relation will be described with reference to FIG. Compared to FIG. 1 of the first embodiment, a two-port RAM 32 is added in FIG. 5, and the write data input terminal and the write address input terminal of the two-port RAM 32 are connected to the bus line 3 as in the two-port RAM 1. Yes. The write clock input terminal of the 2-port RAM 32 is connected to the VCO output terminal of the PLL control circuit 21. The read address input terminal of the 2-port RAM 32 is connected to the count output terminal of the address counter 33, and the clock input terminal of the address counter 33 and the read clock input terminal of the 2-port RAM 32 are connected to the RCLK input terminal 19. The read enable 2 (READ_ENABLE2) terminal 35 is connected to the count enable input terminal of the address counter 33 and the REB terminal of the 2-port RAM 32. The input terminal of the gate circuit 37 is connected to the WEB terminal 30 and the ODD signal output terminal of the line counter circuit 38, and the input terminal of the gate circuit 36 is connected to the WEB terminal 30 and the EVEN signal output terminal of the line counter circuit 38. Has been. The output terminal of the gate circuit 37 is connected to the WEB (write enable) input terminal of the 2-port RAM 1, and the output terminal of the gate circuit 36 is connected to the WEB input terminal of the 2-port RAM 32. The read data output of the 2-port RAM 32 is connected to a read data (read_DATA) output terminal 34. The line counter circuit 38 is connected to a HENABLE terminal 39 and receives a line synchronization signal.

  Next, the operation of this embodiment will be described. The line counter circuit 38 is supplied with a signal indicating the head of a line from the HENABLE terminal 39 at the start of reading one line of image data. When the signal is input an odd number of times, the output of the ODD terminal of the line counter circuit 38 is H and the output of the EVEN terminal is L. When the signal is input even number of times, the output of the ODD terminal is L and the output of the EVEN terminal. Becomes H. Therefore, when the output of the ODD terminal of the line counter circuit 38 is H and the output of the EVEN terminal is L, the circuit of this embodiment operates exactly the same as that of the first embodiment. That is, odd line image data input from the digital data input terminals 26 to 29 is rearranged and written in the 2-port RAM 1. On the other hand, since the output of the EVEN terminal of the line counter circuit 38 is L, the output of the gate circuit 36 is H. As a result, since the WEB of the 2-port RAM 32 is H, the 2-port RAM 32 is not accessed. On the other hand, when even line image data is input, the output of the EVEN terminal of the line counter circuit 38 is H, and the output of the ODD terminal is L. As a result, the output of the gate circuit 37 becomes H, and since the WEB of the 2-port RAM 1 is H, the 2-port RAM 1 is not accessed. On the other hand, the output of the gate circuit 36 becomes L, and the WEB of the 2-port RAM 32 becomes L, so that writing to the 2-port RAM 32 becomes possible, and even-line image data is rearranged and written in the 2-port RAM 32. . Also in this case, the operation itself is only that the writing object is changed from the 2-port RAM 1 to the 2-port RAM 32, and other operations are the same as those in the first embodiment. Thus, in the case of the present embodiment, the input image data read from the CCD is alternately written into the 2-port RAM 1 and the 2-port RAM 32. A timing chart relating to the operation is shown in FIG.

  Although not shown in the circuit block diagram of FIG. 5, in the image processing circuit provided in the subsequent stage of the 2-port RAMs 1 and 32, the data output from the read data output terminals 20 and 34 of the 2-port RAMs 1 and 32 is sometimes used. It becomes possible to process in the division. Specifically, the image processing circuit processes the data output from the read data output terminal 20 when the read enable input terminal 18 is L, and the read data output terminal 34 when the read enable 2 terminal 35 is L. Data output from the port may be processed. Note that, similarly to the address counter 2, the address counter 33 is configured such that the count value is always 0 when the read enable 2 terminal 35 is H.

  As described above, according to the present embodiment, it is possible to add the write / read control circuit for the 2-port RAM to the circuit described in the first embodiment without changing the contents of the lookup table. Two two-port RAMs can be controlled.

  FIG. 7 is a circuit block diagram showing the present embodiment. Compared with FIG. 5 of the second embodiment, the line counter circuit 38 is deleted, and the signal lines connected thereto are also deleted. Further, in this embodiment, compared with the second embodiment, the MSB (most significant bit) of the data corresponding to the lookup tables 8 to 11 is increased by 1 bit, and the MSB read through the selector circuits 4 to 7 is increased. Is connected to the input terminals of the gate circuits 36 and 37. Other circuits and their operations are the same as those in the second embodiment. In the second embodiment, the writing of image data input from the digital data input terminals 26 to 29 to the 2-port RAM 1 or the 2-port RAM 32 is controlled by the output signals of the ODD and EVEN terminals of the line counter circuit 38. . In the present embodiment, the same control can be performed using one bit of the MSB of the lookup tables 8-11. Specifically, the input image data from the digital data input terminals 26 to 29 is stored in the 2-port RAM 1 when the MSB bit value of the lookup table is 1, and is stored in the 2-port RAM 32 when the MSB bit value is 0, respectively. Controlled to be written.

  As described above, according to the present embodiment, the MSB bit is added to the memory address data stored in the lookup table without adding an external counter circuit, and the input image data is determined according to the contents of the MSB bit. RAM to be written can be selected.

  FIG. 8 shows a circuit block diagram of this embodiment. This shows an example of the counter 13 and the lookup table 8. When the look-up tables 8 to 11 of the first embodiment are composed of a plurality of RAMs (or ROMs), an extra address counter and decoder circuit are required. Furthermore, the memory capacity of the look-up table required when simply responding to image data input from various CCD devices is several times the memory capacity originally required. On the other hand, the present invention eliminates these wastes and proposes a look-up table configured with a minimum memory capacity using a single RAM or ROM. In particular, for input image data from 4-input, 2-input, and 1-input CCDs, CIS, and CMOS, the difference in interface is absorbed, and the minimum memory capacity for reading and rearranging image data of the same memory size We propose a method that can handle this.

  First, a circuit connection relationship will be described with reference to FIG. The circuit in FIG. 8 corresponds to the circuit inside A surrounded by a dotted line in FIG. Similarly, in FIG. 5 of the second embodiment, FIG. 7 of the third embodiment, and FIG. 14 of the fifth embodiment described later, the look-up tables 8 to 11 and the counter 13 correspond to this circuit. The memory 6-32 is a core memory part of the look-up table. In this embodiment, the memory 6-32 is a RAM or a ROM having a memory capacity of 1K words with 1 word being 104 bits. The data in the memory 6-32 is distributed and read by eight 3-state buffers 6-9 to 6-16. The memory 6-32 is divided into eight areas having a 13-bit configuration, and is divided into areas A to H from the MSB side to the LSB side. The 13 bits of the A area to the H area are connected to the input terminals of the 3-state buffers 6-9 to 6-16, respectively. An address decoder for selecting a data read word in the memory 6-32 is provided inside the memory 6-32. The count output terminal of the address counter 13 is connected to the input terminal of the decoder. The reset terminal of the address counter 13 is connected to the output terminal of the gate circuit 6-38. The WEB terminal 30 is connected to one input terminal of the gate circuit 6-38. When the WEB terminal 30 is H, the address counter 13 is reset and its count value is always zero. The match result output terminal of the comparator 6-7 is connected to the other input terminal of the gate circuit 6-38.

  Output terminals of the 3-state buffers 6-9 to 6-16 are connected to output terminals 6-24 to 6-31. The output terminals of the 3-state buffers 6-10 to 6-16 are connected to the input terminals of the 3-state buffers 6-17 to 6-23. The output terminal of the 3-state buffer 6-23 is connected to the input terminal of the 3-state buffer 6-22, and the output terminal of the 3-state buffer 6-22 is connected to the input terminal of the 3-state buffer 6-21. Further, the output terminal of the 3-state buffer 6-21 is connected to the input terminal of the 3-state buffer 6-20, and the output terminal of the 3-state buffer 6-20 is connected to the input terminal of the 3-state buffer 6-19. The output terminal of the 3-state buffer 6-19 is connected to the input terminal of the 3-state buffer 6-18, and the output terminal of the 3-state buffer 6-18 is connected to the input terminal of the 3-state buffer 6-17. The circuits 6-1 to 6-7 control the 3-state buffers 6-9 to 6-23. 6-2 is a control circuit for generating the main timing signal, control terminals H01 to H08 of the 3-state buffers 6-9 to 6-16, and control terminals V01 of the 3-state buffers 6-17 to 6-23. A control signal of ~ V07 is generated. The circuits 6-1, 6-3, 6-4, 6-5, and 6-6 are circuits that generate or store a signal serving as a reference for the control circuit 6-2.

  The value of the comparison value α that is the output of the buffer 6-6 is information that the CPU sets in the mode selection circuit 6-1 through the bus 6-37. The output terminal of the mode selection circuit 6-1 is connected to the input terminal of the buffer 6-6, and the comparison value α written in the mode selection circuit 6-1 is set in the buffer 6-6. The coincidence result output terminal of the comparator 6-7 and the CLK input 6-36 are connected to the input terminal of the gate circuit 6-4, and the output terminal of the gate circuit 6-4 is connected to the clock input terminal of the counter 6-5. Has been. The value of the comparison value β set in the mode selection circuit 6-1 through the bus 6-37 is set in the buffer 6-3, and the output terminal of the buffer 6-3 and the output of the counter 6-5 are the control circuit 6-6. 2 control signal input terminals. The WEB terminal 30 is connected to the reset input terminal of the counter 6-5. The address counter 13, the counter 6-5, and the comparator 6-7 are configured by a synchronous circuit having a CLK input 6-36 connected to its clock input terminal. However, the comparator 6-7 is a comparator that performs comparison determination at the falling edge of the clock of the CLK input 6-36. Further, mode information can be set in the mode selection circuit 6-1 by a CPU (not shown) through the bus 6-37. Information necessary for operating the control circuit 6-2 is processed in the mode selection circuit 6-1 and notified to the control circuit 6-2 through the signal line 6-40.

  The look-up table shown in FIG. 8 can be expanded to the case where the read data from the CCD is divided into a maximum of 8 channels and a signal is input. Considering the case where the circuit of FIG. 8 is used for image data input divided into 4 channels from the image reading CCD of the first embodiment, the output terminals 6-24 to 6-31 and the latch circuits 22 to 25 of FIG. The connection may be as follows. That is, the output terminals 6-24, 6-26, 6-28, 6-30 in FIG. 8 are connected to the input terminals of the latch circuits 22, 23, 24, 25 in FIG. 1, and the output terminals 6-25 in FIG. 6-27, 6-29, 6-31 may be left open (unconnected).

  Next, the operation of the lookup table of FIG. 8 configured as described above will be described. Now, it is assumed that the memory 6-32 is composed of a ROM in which data is written in advance. This ROM has a memory capacity of a maximum of 1K words, and has a structure in which one word can read 104 bits of data at a time. If necessary, this memory can be configured by a flash ROM, and data can be partially written by 8 bits by a writing circuit (not shown). A CCD device has different data transfer speeds and structures when reading monochrome and color images. For example, in the case of a color image, there is a configuration in which image data is divided and output according to the reading speed, such as 2 channels simultaneously, 4 channels simultaneously, and 8 channels, which is the maximum number of input channels. However, the number of read words for one line read by the CCD device is the same whether the image data is read by one channel or divided into a plurality of channels. The maximum number of read words of image data for one line is 8192 words, and usually 7000 to 8000 words are sufficient. Therefore, the number of read words of image data per input channel (ch) is 3500 to 4000 words for 2-division (2ch) output, 1750 to 2000 words for 4-division (4ch), and 8-division (8ch). If there are, about 800 to 1000 words are sufficient. This means that the number of read words of image data per channel differs depending on the number of channels simultaneously read from the CCD.

  In FIG. 9, when image data is input with 4 channels (4 ch) (FIG. 9A), when input with 2 channels (2 ch) (FIG. 9B), input with 1 channel (1 ch). It is the figure which showed the operating condition of the look-up table in the case where it is performed (FIG.9 (c)). In the table of FIG. 9, the counter value indicates the counter value of the counter 6-5 of FIG. 8, and the control terminals H01 to H08 and V01 to V07 generated by the control circuit 6-2 corresponding to the counter value. The value of the signal is shown.

(1) In the case of 4ch mode (image data input is 4 channels) First, the operation in the case of FIG. 1 of Embodiment 1 in which image data is simultaneously input from 4 channels will be described. In this case, the operation is performed in the 4ch mode of FIG. 9A, and the CPU writes the 4ch mode setting information to the mode selection circuit 6-1 through the bus 6-37, so that the information is controlled through the signal line 6-40. This is notified to the circuit 6-2. Based on this information, the control circuit 6-2 generates control signals for the control terminals H01 to H08 and the control terminals V01 to V07 according to the counter value of the counter 6-5 as shown in FIG. It is sent to the control terminals of the 3-state buffers 6-9 to 6-23 via -33 and 6-34.

  When the total number of read-out words of the image data is 7416 words, the CPU selects the comparison value α indicating the end address of the look-up table to be read out as 927 (39F in hexadecimal notation) via the bus 6-37. Set to 6-1. At the same time, the CPU sets the value of β, that is, the maximum value 2 of the counter 6-5 in the 4ch mode, to the mode selection circuit 6-1. Since the signal at the WEB terminal 30 is H, the counter 6-5 is set to 0, and the control circuit 6-2 sets the counter value of FIG. 9A to the control terminals H01 to H08 and V01 to V07. Send the corresponding value. As a result, since the signals at the control terminals H01, 03, 05, and 07 are H, the 3-state buffers 6-9, 6-11, 6-13, and 6-15 are turned on, and all of the control terminals V01 to V07 are turned on. Since it is L, all the three-state buffers 6-17 to 6-23 are turned off. Since the signal at the WEB terminal 30 is H, the counter value of the address counter 13 is 0, and the data at address 0 in the A area, C area, E area, and G area is 3-state buffers 6-9 and 6-11. , 6-13, 6-15, and output to the latch circuits 22-25 of FIG.

  Next, when the signal at the WEB terminal 30 changes from H to L, the count value of the address counter 13 is updated by the clock input 6-36 as shown in the time chart of FIG. Then, the data in the look-up table in the A area, C area, E area, and G area indicated by the counter value of the address counter 13 is sequentially output to the latch circuits 22 to 25 in FIG. The address counter 13 is counted up to the comparison value α when the CLK input 6-36 rises. At the falling edge of the clock, the comparator 6-7 compares the comparison value α, which is the output signal of the buffer 6-6, with the counter value, which is the output signal of the address counter 13, and matches L if they do not match. If it does, H is output. That is, the maximum counter value of the address counter 13 is the comparison value α. Then, at the next clock rising timing when the output of the comparator 6-7 becomes H, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 1. Simultaneously with the count-up of the counter 6-5, the control circuit 6-2 sends a control signal corresponding to the counter value of 1 in FIG. 9A to the control terminals H01 to H08 and V01 to V07.

  This time, since the control terminals H02, 04, 06, and 08 become H, the 3-state buffers 6-10, 6-12, 6-14, and 6-16 are turned on. Further, since the control terminals V01, 03, 05, and 07 become H, the three-state buffers 6-17, 6-19, 6-21, and 6-23 are turned on. As a result, the lookup table data in the B region, the D region, the F region, and the H region are respectively output through the output terminals 6-24, 6-26, 6-28, and 6-30, and the latch circuits 22 to 25 in FIG. Is output. Then, the count value of the address counter 13 is updated by the clock input 6-36, and the data in the lookup table of the B area, D area, F area, and H area indicated by the counter value of the address counter 13 is input to the latch circuits 22-25. Read sequentially. When the address counter 13 is updated and the count value matches the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 2. As a result, since the counter value of the counter 6-5 matches the comparison value β set in the buffer 6-3, the H signal is applied to the WEB terminal 30, and the writing to the 2-port RAM 1 is completed. The counter 6-5 is reset.

  FIG. 10A shows an example of a lookup table when the image input terminal is 4ch. In FIG. 10A, the address column indicates the value of the address counter 13, and the numerical value in each column of the A area to H area indicates the memory address (FIG. 1) of the 2-port RAM 1 (FIG. 1) to which the corresponding image data is input. Hexadecimal display). As described above, when the counter 6-5 is 0 in FIG. 8, data in the A area, C area, E area, and G area of the lookup table is output to the latch circuits 22 to 25 in FIG. For example, when the address counter 13 in FIG. 8 is 0, data of 0000, 0001, 1CFE, and 1CFF are output from the lookup table to the latch circuits 22 to 25 as shown in FIG. The Note that 1CFE and 1CFF are hexadecimal numbers, and 7422 and 7423 in decimal numbers, respectively. At the same time, in FIG. 1, the image data from the external CCD is input from the digital data input terminals 26 to 29, and is latched together with the data from the lookup table by the latch circuits 22 to 25. The image data input from the digital data input terminals 26 to 29 in FIG. 1 are written to the memory addresses 0000, 0001, 1CFE, and 1CFF of the 2-port RAM 1, respectively. Similarly, the image data input from the digital data input terminals 26 to 29 is written to the memory address of the 2-port RAM 1 read from the lookup table.

  In FIG. 8, when the counter 6-5 is 1, the data in the B area, D area, F area, and H area of the lookup table is output to the latch circuits 22 to 25 in FIG. For example, when the address counter 13 in FIG. 8 is 0, data of 740, 741, 15BE, and 15BF are output from the lookup table to the latch circuits 22 to 25 as shown in FIG. The In addition, 740, 741, 15BE, and 15BF are hexadecimal numbers, and 1dec, 1857, 5566, and 5567 in decimal numbers, respectively. As described above, the image data input from the digital data input terminal is written to the memory address specified by the lookup table.

(2) In the case of 2ch mode (image data input is 2 channels) Next, the operation of the lookup table when the image reading terminal is 2ch will be described. The image reading terminals in this case are the digital data input terminals 26 and 28 in FIG. The basic operation is the same as that in the above-described 4ch mode. Specifically, as in the 2ch mode table of FIG. 9B, the control circuit 6-2 switches the signals of the control terminals H01 to 08 and V01 to V07 according to the counter value of the counter 6-5. Thus, control of data input in 2ch can be realized.

  When the total number of words of the image read data is 7416 words, the comparison value α indicating the end address of the lookup table to be read is set to 927 (39F in hexadecimal notation), and the CPU selects the mode selection circuit 6-37 through the bus 6-37. Set to 1. At the same time, the CPU sets the value of β, that is, the maximum value 4 of the counter 6-5 in the 2ch mode, in the mode selection circuit 6-1. Since the signal at the WEB terminal 30 is H, 0 is set in the counter 6-5, and the control circuit 6-2 sets the counter value of FIG. 9B to the control terminals H01 to H08 and V01 to V07. Send the corresponding value. As a result, since only the signals at the control terminals H01 and 05 are H, only the 3-state buffers 6-9 and 6-13 are turned on. As a result, the data in the A area and the E area are output to the latch circuits 22 and 24 in FIG. 1 through the 3-state buffers 6-9 and 6-13. When the signal at the WEB terminal 30 changes from H to L, the count value of the address counter 13 is updated, and the data in the lookup tables in the A area and E area are sequentially output to the latch circuits 22 and 24 in FIG. When the count value of the address counter 13 matches the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 1. The control circuit 6-2 sends control signals corresponding to the counter value of 1 in FIG. 9B to the control terminals H01 to H08 and V01 to V07.

  This time, since the control terminals H02 and 06 become H, the 3-state buffers 6-10 and 6-14 are turned on, and the control terminals V01 and 05 become H, so the 3-state buffers 6-17 and 6-21. Is turned on. As a result, the data in the lookup table for the B region and the F region are output to the latch circuits 22 and 24 in FIG. 1 through the output terminals 6-24 and 6-28, respectively. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 2. The control circuit 6-2 sends control signals corresponding to the counter value 2 in FIG. 9B to the control terminals H01 to H08 and V01 to V07.

  Since the control terminals H03 and 07 become H, the 3-state buffers 6-11 and 6-15 are turned on, and the control terminals V01, 02, 05 and 06 become H, so the 3-state buffers 6-17 and 6-18, 6-21, and 6-22 are turned on. As a result, the data in the lookup table for the C region and the G region is output to the latch circuits 22 and 24 in FIG. 1 through the output terminals 6-24 and 6-28, respectively. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 3. The control circuit 6-2 sends control signals corresponding to the counter value 3 in FIG. 9B to the control terminals H01 to H08 and V01 to V07.

  This time, since the control terminals H04 and 08 become H, the 3-state buffers 6-12 and 6-16 are turned on, and the control terminals V01 to 03 and 05-07 become H, so the 3-state buffer 6-17 -6-19 and 6-21 to 6-23 are turned on. As a result, data in the lookup table for the D region and the H region is output to the latch circuits 22 and 24 in FIG. 1 through the output terminals 6-24 and 6-28, respectively. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 4. Since the counter value of the counter 6-5 matches the comparison value β set in the buffer 6-3, the H signal is applied to the WEB terminal 30, the writing to the 2-port RAM 1 is completed, and the counter 6- 5 is reset. FIG. 10B shows an example of a lookup table when the image input terminal is 2ch. Although the memory addresses in the figure are different from those in FIG. 10A, the way of reading the table is the same as that in FIG.

(3) In the case of 1ch mode (image data input is 1 channel) Finally, the operation of the lookup table when the image reading terminal is 1ch will be described. The image reading terminal in this case is the digital data input terminal 26 in FIG. The basic operation is the same as that in the aforementioned 4ch mode and 2ch mode. Specifically, as shown in the table of the 1ch mode in FIG. 9C, the signals of the control terminals H01 to 08 and V01 to V07 are switched in accordance with the counter value of the counter 6-5, so that 1ch is input. Control of image data can be realized.

  When the total number of words of the image read data is 7416 words, the comparison value α indicating the end address of the lookup table to be read is set to 927 (39F in hexadecimal notation), and the CPU selects the mode selection circuit 6-37 through the bus 6-37. Set to 1. At the same time, the CPU sets the value of β, that is, the maximum value 8 of the counter 6-5 in the 1ch mode, to the mode selection circuit 6-1. Since the signal at the WEB terminal 30 is H, the counter 6-5 is set to 0, and the control circuit 6-2 sets the counter value of FIG. 9C to the control terminals H01 to H08 and V01 to V07. Send the corresponding value. Thereby, since only the signal of the control terminal H01 is H, only the 3-state buffer 6-9 is turned on. Since the signal at the WEB terminal 30 is H, the counter value of the address counter 13 is 0, and the data at address 0 in the area A is output to the latch circuit 22 of FIG. 1 through the 3-state buffer 6-9. When the signal at the WEB terminal 30 changes from H to L, the count value of the address counter 13 is updated by the clock input 6-36, and the lookup table data in the area A indicated by the counter value of the address counter 13 is as shown in FIG. Are sequentially output to the latch circuit 22. When the count value of the address counter 13 matches the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 1. Then, the control circuit 6-2 sends control signals corresponding to the counter value of 1 in FIG. 9C to the control terminals H01 to H08 and V01 to V07.

  In this case, since only the signal of the control terminal H02 is H, only the 3-state buffer 6-10 is turned on, and only the control terminal V01 is H, so the 3-state buffer 6-17 is turned on. . As a result, the data in the memory in the area B is output to the latch circuit 22 in FIG. 1 through the output terminal 6-24. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 2. The control circuit 6-2 sends control signals corresponding to the counter value 2 in FIG. 9C to the control terminals H01 to H08 and V01 to V07. As a result, since only the signal of the control terminal H03 is H, only the 3-state buffer 6-11 is turned on, and the control terminals V01 and V02 are H. Therefore, the 3-state buffers 6-17 and 6-18 Is turned on. As a result, the data in the memory in the area C is output to the latch circuit 22 in FIG. 1 through the output terminal 6-24. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 3. The control circuit 6-2 sends control signals corresponding to the counter value 3 in FIG. 9C to the control terminals H01 to H08 and V01 to V07. Thereby, since only the signal of the control terminal H04 is H, only the 3-state buffer 6-12 is turned on, and the control terminals V01 to V03 are H, so the 3-state buffers 6-17 to 6-19. Is turned on. As a result, the data in the memory in the D region is output to the latch circuit 22 in FIG. 1 through the output terminal 6-24. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 4. The control circuit 6-2 sends control signals corresponding to the counter value 4 in FIG. 9C to the control terminals H01 to H08 and V01 to V07.

  This time, since only the signal of the control terminal H05 is H, only the 3-state buffer 6-13 is turned on. Further, since the control terminals V01 to V04 are H, the 3-state buffers 6-17 to 6-20 are turned on. As a result, the data in the memory in the E region is output to the latch circuit 22 in FIG. 1 through the output terminal 6-24. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 5. The control circuit 6-2 sends control signals corresponding to the counter value of 5 in FIG. 9C to the control terminals H01 to H08 and V01 to V07. As a result, since only the signal of the control terminal H06 is H, only the 3-state buffer 6-14 is turned on. Further, since the control terminals V01 to V05 are H, the 3-state buffers 6-17 to 6-21 are turned on. As a result, the data in the memory in the F region is output to the latch circuit 22 in FIG. 1 through the output terminal 6-24. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 6. Then, the control circuit 6-2 sends control signals corresponding to the counter value 6 in FIG. 9C to the control terminals H01 to H08 and V01 to V07. Thereby, since only the signal of the control terminal H07 is H, only the 3-state buffer 6-15 is turned on. Further, since the control terminals V01 to V06 become H, the three-state buffers 6-17 to 6-22 are turned on. As a result, the data in the memory in the G area is output to the latch circuit 22 through the output terminal 6-24. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 7. The control circuit 6-2 sends control signals corresponding to the counter value 7 in FIG. 9C to the control terminals H01 to H08 and V01 to V07.

  This time, since only the signal of the control terminal H08 is H, only the 3-state buffer 6-16 is turned on. Further, since the control terminals V01 to V07 are H, the 3-state buffers 6-17 to 6-23 are turned on. When the address counter 13 is updated and coincides with the comparison value α, the counter 13 is reset, the counter 6-5 is incremented by 1, and the value becomes 8. Since the counter value of the counter 6-5 matches the comparison value β set in the buffer 6-3, the H signal is applied to the WEB terminal 30, the writing to the 2-port RAM 1 is completed, and the counter 6- 5 is reset. FIG. 10C shows an example of a lookup table when the image input terminal is 1ch. The memory addresses in the figure are different from those in FIGS. 10A and 10B, but the way of reading the table is the same as that in FIG.

  As described above, according to the present embodiment, even if the number of image input channels changes, the memory capacity is minimized and the output is output from the line sensor by using a look-up table that can cope with changes in the number of words to be read. The image data can be rearranged freely. The parameter α set in the buffer 6-6 is a parameter determined by the number of effective pixels of the reading device and the configuration of the lookup table. The number of read pixels can be adjusted by this value, and is changed as appropriate from the external CPU. Is a possible parameter. Further, the parameter β set in the buffer 6-3 can be calculated by the CPU and given from the outside of the ASIC, and calculated by the mode setting information set in the control circuit 6-2 through the signal line 6-40. It is also possible to do. Further, information for raising the WEB terminal 30 from L to H on the basis of this value is not shown, but it is also possible to generate the information within the control circuit 6-2 and control the WEB terminal 30.

(4) Application Example to Medium / High-Speed Copying Machine of this Embodiment FIG. 11 shows a block diagram of a copying machine to which this embodiment is applied. This shows an application example in the case where a reader is commonly designed for a medium-speed copying machine and a high-speed copying machine among black-and-white copying machines. In general, the number of medium- and high-speed machines produced is smaller than that of low-cost low-speed copying machines. Therefore, the number of development steps increases unless a common design is used. Therefore, as shown in FIGS. 11A and 11B, it is important to share the design and reduce the design man-hour by using the image processing board 13-3 in common.

  FIG. 11 (a) shows an example of a medium speed machine reader. An image is read using a low-cost monochrome CCD 13-1, and the image data is divided into two even-numbered pixel rows and odd-numbered pixel rows by the CCD, and is output to the analog processor 13-2 via two buses. The The analog processor AD converts the image data signal and transmits the converted digital data to the ASIC 13-4 equipped with the circuit of the present invention. In the ASIC, the received image data is rearranged, and the subsequent image processing circuit In this configuration, common data processing is performed. In this case, although not shown in part, the 20 MHz clock of the transmitter 13-5 is supplied to the clock of the monochrome CCD 13-1, the analog processor 13-2, and the CLK signal of the ASIC 13-4. It is configured. Further, the data readout transmitter of the transmitter 13-6 is connected to the RCLK terminal of the ASIC 13-4, and the data rearranged by the clock (40 MHz) is read out, and the image processing circuit in the subsequent stage also has the same clock rate. Image processing is configured. FIG. 11C shows the read image position of the CCD and the order of the output images in the medium speed machine reader. Here, the image data for one line read by the CCD is composed of 0500th to 7499th 7500 pixels, and is divided into two channels of an odd pixel column and an even pixel column. The numbers in each column of FIG. 11C indicate image positions, and image data is output from the CCD simultaneously from the left end in two channels of even pixels and odd pixels.

  Next, an example of a high-speed device reader is shown in FIG. First, an image is read using a monochrome CCD 13-11 that is high-cost but capable of high-speed reading. The image data is divided into two even-numbered pixel rows and odd-numbered pixel rows by the CCD, and each pixel row is further divided into two parts, the first half and the second half, and is sent to the analog processor 13-2. Then, the analog processor performs AD conversion on the image data signal and transmits the converted digital data to the ASIC 13-4 equipped with the circuit of the present invention. The ASIC rearranges the received image data and performs subsequent image processing. The circuit is configured to perform common data processing. In this case, although not shown in part, the 20 MHz clock of the transmitter 13-5 is supplied to the black and white CCD 13-11, the clock of the analog processor 13-12, and the CLK signal of the ASIC 13-4. It is configured. Further, the data readout transmitter of the transmitter 13-16 is connected to the RCLK terminal of the ASIC 13-4, and the data rearranged by the clock (80 MHz) is read out, and the image processing circuit in the subsequent stage also has the same clock rate. The image processing is performed. FIG. 11D shows the CCD read image position and output image order in the high-speed reader. Here, the image data for one line read out by the CCD is composed of 0500th to 7499th 7500 pixels, and in addition to two channels of the odd pixel column and even pixel column, it is further divided into two parts, the first half and the second half. ing. In FIG. 11C, the even and odd pixel columns on the upper side indicate the first half, and the lower even and odd pixel columns indicate the second half. The numbers in each column indicate image positions. Image data is output from the CCD simultaneously from the left end in the order of increasing image position numbers in the first half and in the order of decreasing image position numbers in the second half. The

  Depending on the model used, the image processing board 13-3 switches the clock of the transmitters 13-6 (40 MHz) and 13-16 (80 MHz), and the CPU (not shown) switches between the 2ch mode and the 4ch mode inside the ASIC. I do. Accordingly, the image processing board 13-3 can be used as a common module in both the medium speed machine reader of FIG. 11A and the high speed machine reader of FIG. 11B. In addition, by mounting a PLL in the ASIC 13-4 and multiplying the input clock from the transmitter 13-5, it becomes possible to switch the clock inside the ASIC 13-4 by an instruction from the CPU, and the transmitter 13-6. And the clock switching of the transmitter 13-16 becomes unnecessary.

  By the way, in the case of the medium speed machine reader of FIG. 11A, the lookup table uses the 2ch simultaneous readout lookup table of FIG. 12A, and the high speed machine reader of FIG. In this case, the lookup table for 4ch simultaneous reading shown in FIG. The look-up table in FIG. 12 is specialized to use only two regions in the case of 2ch and only four regions in the case of 4ch. This is different from a lookup table that uses 8 regions. Further, the control of the lookup table specialized in this way can be dealt with by using the control values in the table of FIG. 9 showing the operating conditions of the lookup table by changing the parameters α and β. For example, considering the case of a medium speed machine, each column of the MSB side 13 bits and the LSB side 13 bits of the lookup table in the case of 2ch in FIG. 12A is the lookup table in FIG. Corresponds to the A and E regions. Then, by setting EA5 (3749 in decimal notation) to parameter α and 1 to parameter β, the control value when the counter value in the 2ch mode shown in FIG. 9B is 0 is used. It is possible to control the medium speed machine reader. Similarly, when considering the case of a high-speed machine, the MSB side 13 bits to the LSB side 13 bits of the lookup table in the case of 4ch in FIG. 12B are the A area of the lookup table in FIG. , C region, E region, and G region. The parameter α is set to 752 (1874 in decimal notation), and the parameter β is set to 1, so that the control value when the counter value in the 4ch mode shown in FIG. 9A is 0 is used. The high speed reader can be controlled.

  Next, the rearrangement operation of the image data from the CCD in the medium speed machine in FIG. 11A will be described with reference to FIG. 1, FIG. 11C, and FIG. The image data from the CCD is composed of 7500 pixels as shown in FIG. 11 (c), and is divided into two channels, an even pixel column and an odd pixel column, which are respectively input from the digital data input terminals 26 and 28 in FIG. The Then, according to the memory address read from the look-up table of FIG. 12A, the data of the even-numbered pixel column of FIG. 11C is the memory address 0, 2,... Of the 2-port RAM 1 of FIG. 1D4A (7498 in decimal notation) is written. Similarly, the data of the odd-numbered pixel column in FIG. 11C is written to the memory addresses 1, 3,..., 1D4B (7499 in decimal number display) of the 2-port RAM 1 in FIG. When the reading of the image data for 7500 pixels from the CCD is completed, the reading of the image data from the 2-port RAM 1 in FIG. As a result, the image data divided and input into the two channels is rearranged.

  Subsequently, the rearrangement operation of the image data from the CCD in the high speed machine shown in FIG. 11B will be described with reference to FIGS. 1, 11D, and 12B. The image data from the CCD is composed of 7500 pixels as shown in FIG. 11 (d), and is divided into a total of four channels: an even-numbered pixel row in the first half, an odd-numbered pixel row, an even-numbered pixel row in the second half, and an odd-numbered pixel row. 1 are input from the digital data input terminals 26, 27, 28, and 29 of FIG. Then, according to the memory address read from the lookup table of FIG. 12B, the data of the even-numbered pixel column in the first half of FIG. 11D is stored in the memory addresses 0, 2,. .., written in EA4 (3748 in decimal notation). Similarly, the odd-numbered pixel column data in the first half of FIG. 11D is written to memory addresses 1, 3,... EA5 (3749 in decimal notation) of the 2-port RAM 1 of FIG. On the other hand, the data of the even-numbered pixel columns in the latter half of FIG. 11 (d) follows the memory addresses read from the lookup table of FIG. 12 (b), and the memory addresses 1D4A, 1D48,. .. written to EA6 Note that 1D4A, 1D48, and EA6 in hexadecimal notation are 7498, 7496, and 3750 in decimal notation. Similarly, the odd-numbered pixel column data in the latter half of FIG. 11D is written to the memory addresses 1D4B, 1D49,..., EA7 of the 2-port RAM 1 of FIG. Note that 1D4B, 1D49, and EA7 in hexadecimal notation are 7499, 7497, and 3751 in decimal notation. When the reading of the image data for 7500 pixels from the CCD is completed, the reading of the image data from the 2-port RAM 1 in FIG. Thereby, rearrangement of the image data divided and inputted to the four channels is performed.

  As described above, according to this embodiment, according to the circuit configuration of this embodiment, the image processing board 13- 3 can be used in common. As a result, common design and standardization can be realized, and the total cost can be reduced.

  FIG. 13 is a circuit block diagram of the present embodiment, and shows an example of a lookup table that is substantially the same as that of FIG. 8 of the fourth embodiment. The difference from FIG. 8 is that the data in each of the areas A to H of the memory constituting the lookup table is expanded from 13 bits to 15 bits. The added 2 bits are added to the MSB side of the data of each of the A to H areas, and the point of designating the RAM in which the data is stored is specified by the value of the 2 bits. Different from 8.

  FIG. 14 shows a circuit block diagram that operates using the lookup table of this embodiment. The circuits 11-1 to 11-5 are added to the circuit shown in FIG. 7 of the third embodiment, and the gate circuits 36 and 37 are changed so that data can be written in three different 2-port RAMs. has been edited. First, the circuit connection relation will be described with reference to FIG. The write clock input terminal of the added 2-port RAM 11-1 is connected to the VCO output terminal of the PLL control circuit 21. The read address input terminal of the 2-port RAM 11-1 is connected to the count output terminal of the address counter 11-3. The clock input terminal of the address counter 11-3 and the read clock input terminal of the 2-port RAM 11-1 are RCLK input terminals 19. It is connected to the. The read enable 3 input terminal 11-4 is connected to the count enable input terminal of the address counter 11-3 and the REB terminal of the 2-port RAM 11-1. The input terminal of the gate circuit 11-2 is connected to the WEB terminal 30 and the MSB side upper 2 bits of data read from the lookup tables 8 to 11 of the bus line 3. Furthermore, the output terminal of the gate circuit 11-2 is connected to the WEB input terminal of the 2-port RAM 11-1. The read data output of the 2-port RAM 11-1 is connected to the read data 3 (read_DATA3) output terminal 11-5. The gate circuits 36 and 37 are changed from the MSB side upper 1 bit connection of the bus line 3 shown in FIG. 7 of the third embodiment to the MSB side upper 2 bit connection, and the logic function of the gate circuit is also changed. .

  In this embodiment, when the MSB side upper 2 bits of the bus line 3 are 00, if the WEB terminal 30 is L, the gate circuit 37 is turned on (the output of the gate circuit 37 is changed from H to L), 2 ports Data is written to the RAM 1. When the MSB side upper 2 bits of the bus line 3 are 01, if the WEB terminal 30 is L, the gate circuit 36 is turned on (the output of the gate circuit 36 changes from H to L), and the data is transferred to the 2-port RAM 32. It is configured to be writable. Similarly, when the MSB side upper 2 bits of the bus line 3 are 10, if the WEB terminal 30 is L, the gate circuit 11-2 is turned on (the output of the gate circuit 11-2 changes from H to L). Data is written to the 2-port RAM 11-1.

  In the present embodiment, the number of writable RAMs is increased by one as compared with the third embodiment, and the specific circuit operation is the same as that of the third embodiment. Therefore, the description of other operations is omitted. Using the lookup table shown in FIG. 13, the RAM for writing data with 2 bits on the MSB side can be divided into three. Thus, when R, G, and B image data are input using the same readout signal line, as in the case of readout data by CIS, the R, G, and B image data are classified and written into three RAMs. Thus, the data can be rearranged while classifying information by color.

  FIG. 15 shows an example of lookup table data in this case. For example, data (A area) whose address of the lookup table is 0 is written in address 0 of the 2-port RAM 1 because the most significant 2 bits are 0. Since the most significant 2 bits of data at address 1 is 1 (the 14th bit is 1), the most significant 2 bits of data is 2 at the address 2 of the 2-port RAM 32 (the 15th bit is 1) Therefore, data is written to address 0 of the 2-port RAM 11-1. The subsequent address data is similarly priced to the most significant 2 bits. As a result, data that comes in the order of R, G, B is rearranged and written into the 2-port RAM 1 for R data, the 2-port RAM 32 for G data, and the 2-port RAM 11-2 for B data. The image data can be rearranged while being separated by color. Note that the data example in FIG. 15 is data when all data is input in one channel, and can be used in place of the data shown in FIG. However, in this case, when the counter value of the counter 6-5 reaches 4, the control for changing the WEB terminal 30 from L to H may be performed. As for the data read control, the read enable 3 signal 11-4 is changed from L to H at the desired read timing in the same manner as the data read of the 2-port RAMs 1 and 32 of the third embodiment. Image data can be sequentially read from address 0.

  As described above, according to the present embodiment, line sensors such as CIS to which image data is input for each color are also written for each color by MSB bits added to the memory address data stored in the lookup table. The RAM to be selected can be selected. As a result, the image data can be classified by color and the image data can be rearranged.

1, 11-1, 32 2-port RAM (equivalent to image data storage means)
2, 11-3, 33 Address counter 6-32 Memory 8, 9, 10, 11 Look-up table (corresponding to memory address instruction means)
13 Counter 26, 27, 28, 29 Digital data input terminal (equivalent to image data input terminal)

Claims (8)

An image data input terminal for inputting image data read by the line sensor by being divided into one or a plurality of channels;
Image data storage means for storing the image data input from the image data input terminal;
After the input image data is written in the image data storage means, when the image data is read from the image data storage means in the order of memory addresses, the image data rearranged in the order of the image positions read by the line sensor are Memory address indicating means for indicating a memory address to be written to the image data storage means so as to be read;
Image data writing means for writing the input image data to a memory address of the image data storage means, designated by the memory address instruction means;
Image data reading means for rearranging the image data input from the image data input terminal by reading the image data written in the image data storage means in the order of memory addresses;
An image processing apparatus comprising: The image data storage means has one or a plurality of memory devices,
The image processing apparatus according to claim 1, wherein the input image data is written to a memory device designated for each image data. In the case where the image data storage means has a plurality of memory devices,
As to which of the memory devices the input image data is to be written to, the memory device to be written is designated by the upper bits of the memory address indicated by the memory address indicating means. The image processing apparatus according to claim 2.   The image data storage means includes a dual port RAM in which the image data writing timing by the image data writing means and the image data reading timing by the image data reading means are mutually exclusive. The image processing apparatus according to any one of claims 1 to 3.   The image processing apparatus according to claim 1, wherein the memory address instruction unit includes one or more ROMs or flash ROMs. Further comprising a control means;
The memory address instructed by the memory address instruction means is a value read from the memory address instruction means with the counter value of the counter whose maximum counter value is controlled by the control means as a memory address. The image processing apparatus according to claim 1.   7. The control unit according to claim 6, wherein the control unit matches the number of memory addresses specified at one time by the memory address instruction unit with the number of channels of image data input from the image data input terminal. Image processing device.   8. The image processing apparatus according to claim 1, wherein the maximum number of channels of image data corresponding to the image data input terminal is eight.

Images