JP2000242486A - Bus interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the change of setting data outputted to a bus while operating a system. SOLUTION: This circuit is composed of a serial/parallel(s/p) converting part 1, a counter 2, a ROM 3, a selector 4, a selector 5, flip-flops 6 and 7 and a CPU bus 8, etc. The selector 4 replaces the setting data inputted through the S/P converting part 1 with one part of standard setting data from the ROM 3. The standard setting data from the ROM 3 are ordinarily outputted from the selector 5 through the flip-flop 7 to the CPU bus 8. By changing the selecting state of the selector 5, the setting data from the selector 4 are sent to the CPU bus 8. Thus, the setting data to be outputted to equipment or the like connected to the CPU bus 8 are changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit, and more particularly to a bus interface circuit for supplying operation setting data and the like to circuits and devices connected to a bus via the bus. It is.

[0002]

2. Description of the Related Art For example, in an ATM device (asynchronous transmission device), setting of an operation mode in a signal processing circuit or device is performed based on setting data input via a CPU bus to which the circuit is connected. Is adopted. These setting data are generally stored in ROM
(Read-only memory), and is output from the ROM to the above-described circuit via a CPU bus or the like.

[0003] By the way, the storage contents of the ROM are determined in the manufacturing process, and the storage contents cannot be changed. Therefore, for example, in the above case, when setting data other than those stored in the ROM is supplied to a circuit or the like via the CPU bus, for example, Japanese Patent Application Laid-Open No.
It is conceivable to use the technique described in Japanese Patent Publication No. 2 (JP-A) No. 2 (1994).

In this prior art, as shown in FIG.
CPU 41, standard ROM 43, detachable optional ROM 45, and R for accessing one of these ROM 43 and ROM 45 based on predetermined selection information.
An OM area access switching mechanism 42 is provided. When the ROM 45 is not mounted in the slot 4,
The CPU 41 accesses the ROM 43 by the ROM area access switching mechanism 42. On the other hand, slot 4
When the OM5 is mounted, the CPU 1
The ROM access switching mechanism 2 is controlled based on the selection information stored in the ROM 6 to select access to the ROM 3 or the ROM 5. According to this configuration, by replacing the ROM 5, the RO can be replaced without replacing the ROM 5.
The contents of the M area can be changed relatively easily.

[0005]

However, in the above-mentioned prior art, when changing the setting contents, it is necessary to replace an optional ROM, so that it takes time to change the contents. Furthermore, since the optional ROM needs to be attached or detached or replaced, it is necessary to bring down the system to change the contents, and the contents cannot be changed while the system is operating, that is, with the power turned on. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interface circuit which can change setting data output to a bus while the system is operating, without replacing the ROM or shutting down the system.

[0007]

A bus interface circuit according to the present invention is a bus interface circuit for outputting predetermined information to a predetermined circuit or device connected to the bus via a bus. Storage means in which is stored, and selection means for selecting one of the first information output from the storage means and second information different from the first information and outputting the selected information to the bus, It is characterized by having.

In the bus interface circuit according to the present invention, the second information is obtained by replacing at least a part of the first information with another information.

Further, the bus interface circuit according to the present invention further comprises a replacing means for replacing at least a part of the first information output from the storage means with other information and outputting it as the second information. It is characterized by becoming.

In the bus interface circuit according to the present invention, the first information, the second information, and the other information are each configured by combining a plurality of data,
A plurality of the second information obtained by replacing at least a part of the plurality of data constituting the first information with data having different other information are input to the replacing means. Outputs one of a plurality of pieces of second information to the selection circuit.

Further, the bus interface circuit of the present invention further comprises a conversion means for supplying the other information as serial data, converting the other information from serial data to parallel data, and outputting the parallel information to the replacement means. It is characterized by becoming.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a bus interface circuit according to an embodiment of the present invention will be described. In FIG. 1, a bus interface circuit includes a serial-parallel conversion unit 1, a counter 2 forming an address generation unit, a ROM 3 forming a storage unit, a selector 4 forming a conversion unit,
It is composed of a selector 5 constituting the selection means, flip-flops (FF) 6 and 7 constituting the retiming means, a CPU bus 8 and the like. Note that devices and circuits (not shown) to which setting data described below are input are connected to the CPU bus 8, and these devices and circuits are set in operation modes and the like by the setting data. Settings are changed.

The serial-parallel converter 1 parallel-develops other information transmitted serially from an external circuit (not shown), ie, third setting data (Ds). Note that F
P is a set frame pulse. The ROM 3 stores standard setting data to be output to a CPU bus 8 (not shown). The ROM 3 has an input terminal on the right side and an output terminal on the left side in FIG.

The counter 2 has an output terminal on the upper side in FIG. 1, generates an address to be given to the ROM 3, and outputs the address from these output terminals. In FIG. 1, the selector 4 has a data input terminal from the ROM 3 on the upper left side and a setting data 1 from the serial-parallel converter 1 on the lower left side.
To s (s is an arbitrary positive integer), and output terminals on the right side. The selector 4 sequentially selects setting data to be output to the CPU bus 8 from the setting data according to the output of the counter 2 and outputs the setting data from an output terminal.

In FIG. 1, the selector 5 has input terminals for setting data output from the selector 4 at the upper right side, input terminals for standard setting data output from the ROM 3 at the center on the right side, and lower terminals. Each has an input terminal for an external setting switching signal. And selector 5
Is the ROM 1 as setting data to be output to the CPU bus 8
To use only the standard setting data stored in the selector 4 or to use the data including the setting data input from the selector 4 and externally input.

The flip-flop 6 has an input terminal for an address signal output from the ROM 3 on the right side in FIG. The flip-flop 7 has an input terminal for data selected by the selector 5 on the right side in FIG. Then, the flip-flops 6 and 7 retime the address signals and data in accordance with the CPU clock and output the signals to the CPU bus 8.

The operation of this embodiment having the above configuration will now be described. First, setting data input as serial data from an external circuit (not shown) is parallel-developed in the serial-parallel converter 1 into parallel data, that is, setting data 1 to s. The setting data 1 to s that have been developed in parallel are input to the selector 4. Further, standard setting data from the ROM 3 is further input to the selector 4.

Here, in the selector 4, the input setting data 1 to s are respectively replaced with a part of the standard input data which is also input. This setting data 1
Which of the standard setting data is to be replaced with .about.s is determined based on, for example, which bit of which address of the CPU bus 8 the setting data 1 to s is assigned to.

On the other hand, in a normal state, the selector 5 outputs standard setting data from the ROM 3 input to the input terminal to the flip-flop 7, and the standard data is output to the CPU bus 8. When setting data other than the standard setting data is desired to flow to the CPU bus, an external setting switching signal input to the selector 5 is operated from outside the selector 5 to change the selection state of the selector 5. . As a result, the externally input setting data 1 to
The setting data from the selector 4 including s is sent to the CPU bus 8.

As described above, according to the bus interface circuit of the embodiment shown in FIG. 1, the externally input setting data is replaced with the standard setting data from the ROM 3 via the CPU bus 8 and output to the CPU bus 8. can do.

Here, in the case of the prior art shown in FIG. 4, when a change is made to the standard setting data, the option ROM 45 is rewritten and the option ROM 45 is mounted on the option socket 44. However, in this case, it takes time to change the setting, and the setting cannot be changed while monitoring the state of the system in real time while the power is on. On the other hand, in the case of the above embodiment of the present invention, since the setting data to be changed is input as a signal, the setting can be easily changed while the system is operating.

FIG. 2 shows another embodiment of the present invention. The bus interface circuit according to this embodiment includes:
As in the above embodiment, the serial-parallel converter 1, the counter 2, the ROM 3, the selector 4, the selector 5,
It comprises flip-flops 6 and 7, a CPU bus 8, and the like. The serial-parallel conversion unit 1 is configured by combining eight shift registers 111 to 118, eight flip-flops 121 to 128 and 13, and the like. The counter 2 is configured by combining a first counter section 21 and a second counter section 22. In FIG. 2, shift registers 113 to 11
7, illustration of the flip-flops 123 to 127 is omitted.

In the embodiment shown in FIG. 2, the number of addresses of the CPU bus 8 is six in total from addresses 0 to 5, and therefore, there are 64 addresses from "000000" to "111111". Each of these 64 addresses is configured so that one bit at a time can be set by setting data input serially from the outside.

That is, setting data (data from setting 1 to setting 64) is externally input to the serial-parallel converter 1 at the timing shown in FIG. The externally input setting data is developed in parallel by the shift registers 111 to 118 and the flip-flops 2 to 9 on the signal lines of the settings 1 to 64. External setting data (1 bit in the example shown) from this signal line,
The 8-bit data obtained by combining the data bits of each address constituting the standard setting data output from the ROM 3 with the bits not set by the external setting data (7 bits in the illustrated example) is used as the selector 4. Respectively.

The selector 4 has eight input terminal groups each having eight input terminals, and the above-mentioned 8-bit data is input to each of these input terminal groups. The positions of the external setting data in the 8-bit data input to each input terminal group are sequentially different as shown in the figure. Then, the selector 4 reads the ROM 3
, One of the input 8-bit data is selected, and the selected data is output to the selector 5. On the other hand, the selector 5 selects the data output from the selector 4 and the data output from the ROM 3 by an external setting switching signal.

The data selected by the selector 5 is
The flip-flops 6 and 7 are retimed by the CPU clock together with the address signal from the ROM 3 and output to the CPU bus 8. Here, the CPU bus 8
, The data output from the ROM 3 is output as it is. Further, by controlling the external setting switching signal in the selector 5, the selector 5
, Data output from the ROM 3 can be selected, and control by setting data externally input via the selector 4 can be invalidated.

In the embodiment shown in FIG. 2, one bit of externally input setting data for each address and the ROM
8 bits consisting of 7 bits of data output from 3 are input as one set, whereby only one bit of each address can be changed by external setting data. Here, 2 to 7 bits of the 8 bits can be used as the external setting data. Alternatively, all the 8 bits, that is, all the inputs to the selector 4 can be external setting data. This makes it possible to change external settings for all data at all addresses of the CPU bus 8 by setting data serially input from the outside.

[0028]

As described above, according to the interface circuit of the present invention, information different from the information from the storage means such as the ROM is selected by the selection means and outputted to the bus. And the setting data output to the bus can be changed without bringing down the system.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an interface circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a bus interface circuit according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a format of setting data input externally in the interface circuit of FIG. 2;

FIG. 4 is an explanatory diagram of a conventional bus interface circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial-parallel converter 2 Counter 3 ROM 4 Selector 5 Selector 6 Flip-flop 7 Flip-flop

Claims (5)

[Claims] 1. A bus interface circuit for outputting predetermined information to a predetermined circuit or device connected to the bus via a bus, wherein: a storage unit in which first information is stored; Selecting means for selecting one of the first information to be output and second information different from the first information, and outputting the selected information to the bus. circuit. 2. The bus interface circuit according to claim 1, wherein the second information is obtained by replacing at least a part of the first information with another information. 3. The information processing apparatus according to claim 1, further comprising a replacement unit that replaces at least a part of the first information output from the storage unit with another information and outputs the second information as the second information. Item 2. The bus interface circuit according to item 1. 4. The first information, the second information, and the other information are each configured by combining a plurality of data, and the replacement unit includes a plurality of data configuring the first information. A plurality of pieces of second information obtained by replacing at least a part of the second information with data having different pieces of other information, and the replacing unit outputs one of the plurality of pieces of second information to the selection circuit. The bus interface circuit according to claim 3, wherein 5. The information processing apparatus according to claim 1, wherein said other information is supplied as serial data, and further comprising conversion means for converting said other information from serial data to parallel data and outputting it to said replacement means. The bus interface circuit according to 3 or 4.