JP6501561B2 - DATA PROCESSING APPARATUS, CONTROL METHOD THEREOF, AND PROGRAM - Google Patents

Description

  The present invention relates to a data processing apparatus having a look-up table and a control method thereof.

  In recent years, scanners, digital cameras, digital video cameras, etc. have become widespread as input devices for color images. On the other hand, as a color image output device, various color printers using an inkjet or electrophotographic system have become widespread. Each of these input / output devices has its own color space. For example, when a color image obtained by a scanner is transferred as it is to another color printer for printing, the color of the printed color image hardly matches the color of the original color image read by the scanner. In order to solve the problem of color reproducibility between devices for such a color image or the like, processing for converting the color space of the input device to the color space of the output device (referred to as color space conversion) is required. Therefore, in order to improve the color reproducibility of the input / output device, the color space conversion function is incorporated in the input / output device.

  Specifically, this color space conversion refers to the entire or a part of a series of image processing such as input gamma correction, luminance density conversion, masking, black generation, output gamma correction and the like. For example, in color space conversion, the three-color (for example, cyan, magenta, yellow (CMY)) of the output device are simultaneously referred to simultaneously referring to the digital image signals of the three-color (for example, red, green, blue (RGB)) of the input device. Convert to a digital image signal of Alternatively, digital image signals of three colors of RGB are converted into digital image signals of four colors (for example, cyan, magenta, yellow, black (CMYK)).

  As a method of realizing color space conversion, a method of storing conversion results in advance as a look-up table (hereinafter referred to as LUT) in memory and referring to the LUT for an input image signal and outputting the conversion results There is. In the color space conversion method using this LUT, it is common to use interpolation together in order to reduce the LUT memory. That is, the data of the conversion color (YMC or YMCK) corresponding to the representative point of the conversion color (RGB) is stored in the memory, and the interpolation operation is performed based on the conversion color data of several points stored in the memory. It is performed to calculate various conversion color data. The finer the method of setting the representative points on the axis such as RGB, the higher the conversion accuracy, but the required memory capacity increases. Conversely, if the representative points are rough, the conversion accuracy will be low, but the memory capacity required will be reduced. Hereinafter, the representative points on the axis will be referred to as grid points (grids), and the number of representative points on the axis will be referred to as the number of grid points per axis. As the number of lattice points per axis, a number from 8 to 33 is generally used. Hereinafter, it may be described as x grid that the number of lattice points per axis is x (for example, the case where the number of lattice points per axis is 33 is described as 33 grid).

  The number of grid points referred to in order to obtain YMC (YMCK) values corresponding to certain RGB values differs depending on the interpolation method. For example, interpolation calculations are performed with reference to eight lattice points in the case of cubic interpolation and to four lattice points in the case of tetrahedral interpolation. Since the conversion color data of the grid point is stored in the memory, multiple accesses to the memory occur in order to refer to the conversion color data of a plurality of grid points. Processing performance can not be improved. Therefore, a method has been proposed in which processing performance is improved by dividing a memory into a plurality of memory accesses and simultaneously performing a plurality of memory accesses for reading data of a plurality of lattice points.

  In Patent Document 1, in order to execute three-dimensional cubic interpolation at high speed, converted color data of 32 grids is divided into eight memories, stored, and read in parallel to achieve high speed. Further, Patent Document 2 shows a method of dividing and storing converted color data of a LUT which can not be represented by a power of 2 in the number of lattice points per axis in a memory. As an example, a method of dividing 33 grid conversion color data into eight memories and generating its address by 13 bits is described. Both patent documents 1 and 2 are common in the point that the even and odd coordinates of the coordinate of each axis store the same representative point in the same memory. That is, in the case of a three-dimensional LUT in which the conversion colors are three RGB colors, eight of (even, even, even), (even, even, odd),..., (Odd, odd, odd) The high-speed processing is enabled by dividing and storing in the memory of.

U.S. Pat. No. 4,837,722 JP 2001-36755 A

  In Patent Document 1, a memory capable of storing converted color data (hereinafter referred to as grid point data) of a total of 32768 (= 32 * 32 * 32) representative points is required to perform processing with 32 grids. Moreover, in patent document 2, in order to process with 33 grids, the memory which can store 35937 (= 33 * 33 * 33) lattice point data is required. Since the required memory capacity differs between the 32 grid case and the 33 grid case, it is necessary to perform memory division in accordance with the largest capacity in order to correspond to the number of grids of a plurality of types. When the number of grids is an odd number, when the memory is divided into eight (or four), the capacity of grid point data stored in each memory differs depending on the combination of even and odd of each axis. Therefore, when lattice point data is stored in the memory in order to set the LUT, it has been necessary to be aware of the number of lattice point data for each memory. Alternatively, in order to eliminate such control, it was necessary to additionally store unnecessary data in accordance with the largest capacity memory.

  The present invention has been made in view of the above problems, and has as its object to efficiently store lattice point data forming a look-up table in memories of a plurality of banks.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention has the following configuration. That is,
A data processing apparatus which loads data of lattice point data constituting one look-up table into a plurality of banks of memory represented by 2 ^M , where M is the number of axes constituting lattice point coordinates, and executes data processing There,
Receiving means for receiving grid point data to be loaded and a register address;
Conversion means for converting the register address received by the reception means into a bank specification and a memory address based on the number of lattice point data stored in the memory of each bank;
Storage means for storing the grid point data to be loaded in the memories of the plurality of banks in accordance with the bank designation and the memory address obtained by the conversion means ;
And the converting means, said register address, by comparing the threshold value according to the number of grid points data belonging to each of said plurality of banks, that determine the bank specified with the memory address.

  According to the present invention, lattice point data forming the look-up table can be efficiently stored in the memories of a plurality of banks.

FIG. 2 is a block diagram showing an example of the arrangement of an image processing unit according to the first embodiment; Diagram showing the format of the command. The figure which shows the number of banks division and data according to grid. The figure which shows the memory map according to grid mode. 6 is a flowchart showing the operation of the address decoder used in the first embodiment. FIG. 8 is a block diagram showing an example of the arrangement of an image processing unit according to the second embodiment; The figure which shows the data storage number of each bank after LUT setting. 12 is a flowchart showing the operation of the address decoder used in the second embodiment. FIG. 11 is a block diagram showing the configuration of an image processing unit in the third embodiment. 16 is a flowchart showing the operation of the address decoder used in the third embodiment. FIG. 1 is a block diagram showing a configuration example of a data processing device according to an embodiment.

  Hereinafter, the present invention will be described in detail based on preferred embodiments with reference to the attached drawings. In addition, the structure shown in the following embodiment is only an example, and this invention is not limited to the illustrated structure.

First Embodiment
FIG. 11 is a block diagram showing an example of a control configuration of the data processing apparatus 10 (for example, a printing apparatus) according to the first embodiment. The CPU 11 controls the operation of each part of the data processing apparatus by executing a program stored in the ROM 12 or the RAM 112. The transfer unit 111 provides various commands and input data 114 input by the input unit 113 to the data processing unit 100 under the control of the CPU 11. The input data 114 is, for example, image data for printing, and is obtained by communication with an external device or reading from the external storage device 14. The data processing unit 100 processes input data (image data), and the processed data is output (for example, printed) by the output unit 13. Note that at least a part of the functions of the transfer unit 111, the input unit 113, the data processing unit 100, and the like may be realized by the CPU 11 executing a predetermined program.

  FIG. 1 is a block diagram showing a configuration example of the data processing unit 100 according to the first embodiment. The data processing unit 100 includes a control unit 101, a processing unit 102, and a storage unit 103 having a plurality of memories (bank 0 to bank 7: difference in height indicates difference in capacity). The control unit 101 receives, from the transfer unit 111, a register command for setting a register and a LUT, and a data command in which data to be processed is stored. Note that, in the present embodiment, an image processing apparatus in which image data (RGB data) is processed by the data processing unit 100 is exemplified, but data to be processed is not limited to this.

  The control unit 101 analyzes the received command and determines whether the command is a register command or a data command. When the received command is a register command, the control unit 101 sets a value in a register or a memory (not shown) according to the address stored in the command. For example, if the received command is a register command and the address stored in the command is a register address as shown in FIG. 4A, the control unit 101 searches the memory of the storage unit 103 for a lookup table (LUT). Store the grid point data of As described above, the data processing unit 100 according to the present embodiment loads data of lattice points constituting one look-up table into memories of a plurality of banks to execute data processing.

  If the received command is a data command, data (for example, image data) is extracted from the data area of the command and input to the processing unit 102. For example, when RGB data is stored in the data command, the control unit 101 extracts RGB data from the data command and inputs it to the processing unit 102. The processing unit 102 performs, for example, predetermined processing including conversion processing (for example, processing of converting RGB data into CMYK data) with reference to the LUT of the storage unit 103. The data processed by the processing unit 102 is input to the control unit 101 again. When the control unit 101 receives the processed data from the processing unit 102, the control unit 101 again outputs the data command format to the outside. Note that the processing unit 102 determines, for example, the number of grid points of the LUT or the type of interpolation processing (for example, tetrahedron interpolation processing etc.) used for data conversion processing with reference to the LUT by referring to the set register value. You may The register value in this case is set by the aforementioned register command. The above is the rough flow of the image processing shown by the present invention. Next, the operation of each component will be described in detail.

  As described above, the control unit 101 performs setting of a register to be referred to by the processing unit 102, setting of the storage unit 103, data exchange with the processing unit 102, and the like in accordance with the command input from the transfer unit 111. First, the control unit 101 analyzes the input command and determines whether the command is a register command or a data command. The format of the command is shown in FIG. FIG. 2 (a) shows a register command, and FIG. 2 (b) shows a data command. Whether the command is a register command or a data command can be determined by referring to the register / data determination flag 201 located in the most significant bit of the command. For example, if the register / data discrimination flag 201 is 1, it is a register command, and if it is 0, it is a data command. When the control unit 101 determines that the received command is a register command, the control unit 101 accesses the storage unit 103 according to the address 203 stored in the command, or the register in the control unit 101 or the processing unit 102 Determine whether to access (not shown). Further, an RW flag 202 indicating whether the access is a read operation or a write operation exists in the register command, and the write access and the read access are switched according to the value. Further, setting data 204 exists in the register command, and in the case of a write operation, the value stored therein is set in the register in the control unit 101 or the processing unit 102 or the storage unit 103. On the other hand, when the control unit 101 determines that the received command is a data command, the control unit 101 sends the data (image data 205 in this embodiment) stored in the data command to the processing unit 102.

  Next, image processing performed by the processing unit 102 will be described. As an example of processing in the processing unit 102, an example of converting data using tetrahedron interpolation processing (for example, processing for converting RGB data into YMCK data) will be described with reference to a three-dimensional LUT that is 17 grids. The 17 grid LUT is a LUT having 17 grid points per axis. In the case of a 17 grid LUT, there are 17 grid points from 0 to 16 per axis, so the total number of grid points in three dimensions is 17 * 17 * 17 = 4913, and the 4913 grid point data Are loaded into the storage unit 103 and stored. The processing unit 102 accesses the storage unit 103 according to input data (RGB data) to read out a plurality of lattice point data (YMCK data), performs interpolation processing using them, and obtains conversion data (YMCK data).

In the case of tetrahedral interpolation, it is necessary to read out adjacent four grid point data from the storage unit 103. Therefore, the processing unit 102 divides the memory in the storage unit 103 into a plurality of banks to enable parallel access, and simultaneously reads out a plurality of lattice point data used for processing, thereby speeding up data processing. In the present embodiment, it is possible to simultaneously read out four grid point data required for interpolation processing by dividing the memory (bank) of the storage destination in an even or odd sequence of coordinate values of each axis of the grid point coordinates. ing. That is,
9 * 9 * 9 = 729 pieces of data corresponding to lattice points of (even, even, even) coordinates are stored in bank 0 of the memory in the storage unit 103,
9 * 9 * 8 = 648 pieces of data corresponding to grid points of (even, even, odd) coordinates are placed in bank 1,
9 * 8 * 9 = 648 pieces of data corresponding to (even, odd, even) grid points in the coordinates are in bank 2,
...,
8 * 8 * 8 = 512 pieces of data corresponding to (odd, odd, odd) grid points are stored in the bank 7
It is stored in the memory divided into eight banks and so on.

  FIG. 3A shows the number of lattice point data stored in the memory of each bank when the 17 grid LUT is referred to. Each memory of banks 0 to 7 shown in FIG. 1 has a size for storing the number of lattice point data shown in FIG. 3 (a). Since the number of lattice point data stored in each bank is different, when storing lattice point data in the storage unit 103, the control unit 101 needs to appropriately select and store the storage destination bank. The operation performed by the control unit 101 in order to classify data into different numbers of lattice point data and store the data in a plurality of banks will be described in detail.

  When the control unit 101 receives a register command for setting the register in the processing unit 102, the control unit 101 sets a value in a register (not shown) of the control unit 101 or the processing unit 102. Further, when the control unit 101 receives a register command for setting lattice point data, the control unit 101 stores the setting data 204 in the memory of the storage unit 103. Whether the register command is register setting or lattice point data setting is determined by the address 203 in the command. For example, when the command is a register command, the RW flag 202 indicates a write operation, and one of the register addresses in FIG. 4A is stored in the address 203, it is determined that the lattice point data is set. In the case of a register command for setting lattice point data, lattice point data (for example, CMYK data) at one lattice point coordinate is stored as setting data 204. The control unit 101 stores the memory in the storage unit 103 according to the register command including the grid point data to be loaded and the register address. In the present embodiment, one lattice point data consumes four register addresses as data handled in units of four bytes, and the first address of the four register addresses is stored in the address 203 of the register command. Be done.

  A register command for loading lattice point data of the LUT may be generated by, for example, the CPU 11 and loaded via the transfer unit 111. In this case, for example, CPU 11 reads grid point data stored in external storage device 14 in order of even and odd grid point coordinates and accordingly assigns consecutive register addresses from 0x0000 to 0x4CC0 to register command Generate Alternatively, the CPU 11 may generate lattice point data of even number and odd number of lattice point coordinates sequentially from the matrix coefficients, and thus sequentially assign register addresses from 0x0000 to 0x4CC0 to generate a register command. Alternatively, the transfer unit 111 may transfer lattice point data stored in the RAM 112 to the control unit 101 by assigning consecutive register addresses from 0x0000 to 0x4CC0 as the transfer destination address. In this case, the CPU 11 stores the grid point data on the RAM 112 in the order of even and odd grid point coordinates. Then, the transfer unit 111 sequentially reads lattice point data on the RAM 112, assigns a continuous register address from 0x0000 to 0x4CC0, and generates a register command. As described above, register addresses are assigned to lattice point data constituting one look-up table, and a register command is generated. Note that grid point data (for example, CMYK data) corresponding to one grid point coordinate is stored in setting data 204 of the register command for loading the look-up table.

  The control unit 101 causes the address decoder 104 to convert the register address (address 203) in the register command into the designation and address of the memory bank in the storage unit 103 according to a predetermined memory map. Then, the control unit 101 writes the lattice point data (setting data 204) stored in the register command into the memory of the designated bank. The address decoder 104 converts the register address stored in the received register command into a bank specification and a memory address based on the number of lattice point data stored in the memory of each bank. The control unit 101 stores lattice point data to be loaded, which is stored in the register command, in memories of a plurality of banks in accordance with the bank specification and the memory address obtained by the address decoder 104. Hereinafter, this process will be described in detail.

  FIG. 4A shows a memory map used when processing with 17 grids. Following 729 grid point data from (0, 0, 0) to (16, 16, 16) having grid point coordinates (even, even, even), grid point coordinates (even, even, odd) 648 grid point data from (0, 0, 1) to (16, 16, 15) are stored. These 729 grid point data and 648 grid point data are continuously stored, and unnecessary data for adjusting to 729, which is the maximum grid point data number, is stored before and after or in the middle of the 648 grid point data. There is no area. That is, the register addresses are assigned such that all lattice point data constituting one look-up table are continuous, and lattice point data groups classified into each of a plurality of banks are continuous. Also, the first 729 grid data are stored in the memory of bank 0, and the subsequent 648 grid data are stored in the memory of bank 1. Then, the register address continues as it is, and 512 grid point data from (1, 1, 1) to (15, 15, 15) whose grid point coordinates are (odd, odd, odd) are appropriate. It is mapped to the memory of the bank. The register address stored in the register command in this manner is converted into a bank and a memory physical address as shown in FIG. 4A, and is stored in each memory of the storage unit 103. Although the register address starts from 0x0000 in FIG. 4A, the present invention is not limited to this. All grid point data in the 17 grid LUT may be allocated to the continuous address space.

  FIG. 5 shows a flowchart showing the operation of the address decoder 104. The operation of the address decoder 104 will be described below with reference to the flowchart of FIG. As described above, one lattice point data is handled in 4-byte units, and four register addresses are consumed. First, in step S601, it is checked whether the register address stored in the register command is a multiple of four. . If it is not a multiple of 4 (the lower 2 bits are not 0), the memory in the storage unit 103 is not accessed, and the processing is ended. In step S602, the register address is divided by 4 to obtain a value A (that is, a value A obtained by shifting the address to the right by 2 bits). Then, by comparing the value A with a predetermined threshold (steps S603, S605, S607, S609, S611, S613, S615, S617), the bank and the memory address are determined as described below (steps S604, S606) , S608, S610, S612, S614, S616, S618).

(1) When 0 ≦ A <729, the bank is 0, and the memory address is A (S603, S604)
(2) When 729 ≦ A <1377, the bank is 1 and the memory address is A-729 (S605, S606)
(3) When 1377 ≦ A <2025, the bank is 2 and the memory address is A-1377 (S607, S608)
(4) When 2025 ≦ A <2601, the bank is 3 and the memory address is A-2025 (S609, S610)
(5) When 2601 ≦ A <3249, the bank is 4 and the memory address is A-2601 (S611, S612)
(6) When 3249 ≦ A <3825, the bank outputs 5 and the memory address A-3249 (S613, S614)
(7) When 3825 ≦ A <4401, the bank is 6 and the memory address is A-3825 (S615, S616)
(8) When 4401 ≦ A <4913, the bank is 7 and the memory address is A-4401 (S617, S618)
(9) When 4913 ≦ A, the memory is not accessed.

The threshold values used for bank selection are
729 = 9 * 9 * 9
1377 = 729 + 9 * 9 * 8
2025 = 1377 + 9 * 8 * 9
2601 = 2025 + 9 * 8 * 8
3249 = 2601 + 8 * 9 * 9
3825 = 3249 + 8 * 9 * 8
4401 = 3825 + 8 * 8 * 9
4913 = 4401 + 8 * 8 * 8
It is determined by The threshold is determined by the number of lattice point data stored in the memory of each bank. The number of grid point data stored in the memory of each bank is 2 ⁿ +1, the number of dimensions is m, and the number of odd coordinates among the coordinate values of each axis is p In this case, (2 ^{n -1} +1) ^p × (2 ^{n -1} ) ^m-p .

  As described above, by operating the address decoder, it is possible to convert the register address into the bank and memory address in the storage unit 103, which is the storage destination of the lattice point data. Note that the method of realizing the address decoder is not limited to this method, and another method such as calculation using a calculation formula may be used. In this manner, the necessary memory capacity, the number of commands for setting the lattice data, and the capacity of the ROM storing the firmware can be reduced by continuously mapping the necessary lattice data to the memory without excess or deficiency. It becomes possible.

  The lattice point data stored in the memories of banks 0 to 7 can be read, for example, as follows. For example, when the number of grid points on each axis of the three-dimensional lookup table is 17 grids, the grid point coordinates of the LUT are configured by coordinate values (r, g, b) of 5 bits on each axis. It is assumed that grid point coordinates (r, g, b) are obtained based on the input RGB data. Since the bank is determined by an odd or even sequence of coordinate values of each axis, the information specifying the bank is the LSB of r, g, b (r [0], g [0], b [0]) Are obtained by linking 4 × r [0] + 2 × g [0] + b [0]. In addition, the memory address of the storage unit 103 is a 4-bit data value obtained by removing the LSB from the 5 bits of r, g, b, r [4 ... 1], g [4 ... 1], b [4 ... 1] can get. That is, r [4... 1] x (9-g [0]) x (9-b [0]) + g [4 ... 1] x (9-b [0]) + b [4 ... 1] The memory address of the point is obtained. The processing unit 102 acquires a plurality of lattice point data corresponding to RGB data, which is input data, by the above processing, and performs interpolation processing using them to output data corresponding to input data (for example, RGB data). Get (eg CMYK data). The processing unit 102 performs interpolation processing based on the grid point data read out in this way and the RGB data, and converts the RGB data into corresponding YMCK data.

  As described above, in the present embodiment, the control unit 101 performs an operation of setting lattice point data in accordance with a memory map in which lattice point data necessary for processing of 17 grids are arranged without excess or deficiency. Therefore, it is only necessary to prepare necessary data for commands and firmware for setting the memory capacity and lattice point data of the storage unit 103, and the circuit can be reduced. Although the 17 grid three-dimensional LUT is illustrated in the above embodiment, the present invention is not limited to this. For example, the number of dimensions of the LUT may be two or more. Also, the number of grids (the number of grid points per axis) is not limited to 17. When the number of grids is an even LUT, the number of grid point data stored in the memory of each bank is equal. In the case of the LUT having an odd number of grids, although the number of lattice point data allocated to each bank is different as in the above embodiment, the number of lattice point data allocated to each bank is held by continuous addresses. The memory capacity can be reduced.

  Since the number of lattice points in bank 7 is 512, writing to the memory is inhibited if any of the bits higher than the 9th bit of the memory address of bank 7 is “1” in step S618. The comparison with the threshold 4913 (step S617) is not necessary. In this case, step S618 is executed when it is determined NO in step S615.

Second Embodiment
In the first embodiment, it is shown that the memory capacity of the storage unit 103 and the capacity of the ROM for storing the firmware can be reduced by providing the control unit 101 with a function to appropriately allocate the storage destination of the lattice point data. . In the second embodiment, an example in which one processing unit 102 is provided with a plurality of processing functions and used properly according to the register setting is shown.

  FIG. 6 shows a block diagram of an image processing apparatus according to the second embodiment. The same reference numerals as in FIG. 1 denote the same parts as in the first embodiment. The control unit 701 and the processing unit 702 that operate differently from the first embodiment will be described below. In the second embodiment, the register address is converted into a bank specification and a memory address according to instruction information for instructing one of a plurality of types of look-up tables having different numbers of grids per axis, and according to the instruction information, The processing unit 702 operates.

  The processing unit 702 performs 16 grid processing in addition to the 17 grid processing described in the first embodiment. The number of grids to be processed is set by the register value of the register 703. Hereinafter, the mode of processing with 17 grids is called 17 grid mode, and the mode of processing with 16 grids is called 16 grid mode. The control unit 701 has a register 703 storing “17 Grid Mode”, and the processing unit 702 switches between the 16 grid mode and the 17 grid mode by referring to the register 703. When “17 Grid Mode” of the register 703 is set to “0”, the processing unit 702 operates in the 16 grid mode, and when set to “1”, the processing unit 702 operates in the 17 grid mode. Thus, “17 Grid Mode” is used as instruction information for instructing the LUT used for processing. The setting of 17GridMode in the register 703 is realized by the register command input from the transfer unit 111.

The 16 grid mode is a processing mode using a LUT with 16 grid points per axis. When operating in the 16 grid mode, the number of grid points in a three-dimensional LUT such as RGB is 16 * 16 * 16 = 4096 in total since the number of grid points per axis is 16 from 0 to 15. Data corresponding to those grid points are read out from the memory divided according to even and odd combinations of grid point coordinates. That is,
Reading 8 * 8 * 8 = 512 grid point data corresponding to grid points whose coordinates are (even, even, even) from the memory bank 0 of the storage unit 103,
Reading 512 grid point data corresponding to (even, even, odd) grid points from the bank 1,
...
Reading out 512 pieces of data corresponding to (odd, odd, odd) grid points whose coordinates are read out from the bank 7 from the memory divided into eight pieces. FIG. 3B shows the number of grid point data stored for each bank when processing is performed with 16 grids.

  The amount of storage of grid point data in the storage unit 103 differs between the 16 grid mode and the 17 grid mode. In the present embodiment, in order to perform arithmetic processing in two modes by the same image processing module, the storage unit 103 is provided with a memory adapted to the capacity of 17 grids having a large capacity. That is, the memory configuration is the same as that of the first embodiment.

  Next, processing of the control unit 701 will be described. The control unit 701 has a register 703 for setting the processing mode (17 Grid Mode). First, the control unit 701 receives a register command for setting the register 703. When the control unit 701 receives a register command for setting the processing mode (17 Grid Mode), the control unit 701 sets the register 703 and inputs a setting value to the processing unit 702. Necessary settings for the processing unit 702 other than 17 Grid Mode are also input as commands at this time. The setting order of the registers is not specified, and the setting order may be reversed.

  Next, a register command for setting lattice point data is input to the control unit 701. The control unit 701 receives a register command for setting, in the storage unit 103, grid point data necessary for image processing. Since the number of grid point data in the LUT differs depending on whether processing is performed in the 16 grid mode or 17 grid mode, the number of register commands for setting grid point data received by the control unit 701 also differs. That is, in the case of processing in the 16 grid mode, register commands of 4096 grid point data settings are received, while in the case of processing in the 17 grid mode, register commands of 4913 grid point data settings are received.

  When the control unit 701 receives a register command for setting lattice point data, the control unit 701 refers to the address stored in the command and stores the lattice point data in the memory of the appropriate storage unit 103. As described above, since the number of grid point data stored in the storage unit 103 differs between the 16 grid mode and the 17 grid mode, the control unit 701 needs to distribute grid point data to the appropriate bank memory according to the setting of the grid mode. There is. FIG. 4B shows a memory map in the 16 grid mode. The control unit 701 refers to the already set 17GridMode of the register 703, and determines which of the memory maps of FIG. 4A and FIG. 4B is to be followed.

  As shown in FIG. 6, the control unit 701 includes an address decoder 704 in the same manner as the control unit 101, and the setting of 17GridMode in the register 703 can be referred to from the address decoder 704. Then, when the 17GridMode in the register 703 is '0', that is, 16 grid mode is indicated, the register address is converted to the bank and the memory address according to the memory map of FIG. Go.

  Consecutive register addresses are assigned to the grid point data of the 16 grid LUT as shown in FIG. 4 (b). That is, (even, even, odd) following the 512 grid point data from (0, 0, 0) to (14, 14, 14) whose grid point coordinates are (even, even, even) Consecutive register addresses are assigned to 512 grid point data from (0, 0, 1) to (14, 14, 15). As described above, continuous register addresses are assigned to lattice point data, and an unnecessary data area for adjusting to the maximum memory capacity (the capacity of 729 lattice point data) before, after, or along the 512 lattice point data. Does not exist. Thus, successive register addresses are assigned up to 512 grid point data from (1, 1, 1) to (15, 15, 15) whose grid point coordinates are (odd, odd, odd).

  Then, as shown in FIG. 4B, the address decoder 704 has 512 pieces of (0, 0, 0) to (14, 14, 14) whose lattice point coordinates are (even, even, even). Grid point data are mapped in order from address 0 of the memory (memory 0) of bank 0. Subsequently, the address decoder 704 stores 512 grid point data from (0, 0, 1) to (14, 14, 15) whose grid point coordinates are (even, even, odd) in the memory of bank 1 Map to (Memory 1). In this way, successive register addresses are mapped to a plurality of banks of memories, and 512 data of grid point coordinates (1, 1, 1) to (15, 15, 15) are mapped in the memory (memory 7) of bank 7. Be done.

  On the other hand, the operation when the 17GridMode of the register 703 is '1', that is, the 17 grid mode is the same as that of the first embodiment, and the grid point data is mapped to each memory of the storage unit 103 according to the memory map of FIG. Be done.

  As described above, the control unit 701 internally includes the address decoder 704 that converts a register address into a bank for storing data and a memory address, as in the first embodiment, and performs mapping of lattice point data as described above. To realize. FIG. 8 is a flow chart showing the operation of the address decoder 704 of the second embodiment. Steps that perform the same operations as the flowchart of FIG. 5 are given the same reference numerals. Hereinafter, the operation of the address decoder 704 will be described according to the flowchart of FIG.

  First, in step S601, the address decoder 704 checks whether the register address is a multiple of four. If it is not a multiple of 4, the process is ended without accessing the memory. If it is a multiple of four, the process proceeds to step S 602, where the address decoder 704 divides the register address by four to obtain the value A. Next, in step S901, it is determined whether 17GridMode of the register 703 is set to '1'. If it is set to 1, the process proceeds to step S918. Step S918 is processing to load grid point data of a 17-grid LUT into the storage unit 103, and the specific processing content is the same as that of the first embodiment (step S603 to step S618 in FIG. 5).

On the other hand, if 17 Grid Mode of the register 703 is set to “0”, the process proceeds to step S 902, and executes memory mapping corresponding to the LUT of 16 grids. That is, by comparing the value A with a predetermined threshold (steps S902, S904, S906, S908, S910, S912, S914, S916), the bank and memory address to be selected are determined as shown below (step S903). , S905, S907, S909, S911, S913, S915, S917), and grid point data are mapped.
(1) When 0 ≦ A <512, the bank is 0 and the memory address is A (S902, S903)
(2) When 512 ≦ A <1024, the bank is 1 and the memory address is A-512 (S904, S905)
(3) When 1024 ≦ A <1536, the bank is 2 and the memory address is A-1024 (S906, S907)
(4) When 1536 ≦ A <2048, the bank is 3 and the memory address is A-1536 (S908, S909)
(5) When 2048 ≦ A <2560, the bank is 4 and the memory address is A-2048 (S910, S911)
(6) When 2560 ≦ A <3072, the bank outputs 5 and the memory address A-2560 (S912, S913)
(7) When 3072 ≦ A <3584, the bank is 6 and the memory address is A-3072 (S914, S915)
(8) When 3584 ≦ A <4096, the bank is 7 and the memory address is A-3584 (S916, S917)
(9) When 4096 ≦ A, the memory is not accessed.

  As a result of storing the lattice point data in the storage unit 103 as described above, the set values are stored in the eight memories of the storage unit 103 as shown in FIG. FIG. 7A shows the result of storage of lattice point data in the 17 grid mode, and FIG. 7B shows the result of storage of lattice point data in the 16 grid mode. The fraction described in each bank in the figure indicates that the denominator represents the capacity of each memory (maximum number of storable lattice point data), and the numerator represents the number of the lattice point data stored therein. In the 17 grid mode, the entire area is used in all memories (memory 0 to memory 7) of the storage unit 103. However, in the 16 grid mode, grid point data necessary for 16 grid interpolation processing is used. It is stored in each memory.

  Next, the control unit 701 receives a data command. Image data to be subjected to image processing is extracted from the data commands input to the control unit 701, and input to the processing unit 702. The processing unit 702 performs predetermined image processing according to the set register value (the value of 17 Grid Mode) of the received image data. That is, if 17 Grid Mode is set to 1, the processing unit 702 performs processing in the 17 grid mode, and if it is set to 0, the processing unit 702 performs processing in the 16 grid mode. The processing unit 702 inputs the processed data to the control unit 701 again. The control unit 701 generates a data command from the received data after processing and outputs the data command.

  The above is the flow of the image processing in the image forming system of the second embodiment. As described above, the processing mode (17 Grid Mode) is first set in the register, and then grid point data suitable for image processing in the set processing mode is stored in the storage unit 103 when setting grid point data. Perform image processing from By performing register setting and lattice point data setting in such a procedure, even with an image processing module having a single storage unit 103 consisting of eight memories, multiple types of image processing can be performed. It becomes.

  Since the number of lattice point data stored in each bank in the 16 grid mode is 512, the address decoder 704 may generate the bank and memory address by extracting predetermined bits from the register address. For example, bits 13 to 11 of the register address (MSB: 13, LSB: 0) may be extracted as a bank, and bits 10 to 2 of the register address may be extracted as a memory address.

Third Embodiment
In the second embodiment, setting the processing mode (17 Grid Mode) in the register 703 at the time of setting the register shows that data can be stored in the memory according to the image processing in the set processing mode. . Here, the control unit 701 is configured to select a threshold held in advance according to the setting value of 17 GridMode in the register 703, and output a bank and an address to be stored according to the threshold. That is, since the configuration is to select from a plurality of modes (17 grids and 16 grids in the second embodiment) prepared in advance, selectable modes are limited. In the third embodiment, it is possible to set a set of thresholds in a register, that is, to change the set of thresholds in accordance with a lookup table used, and to adapt to a wider range of processing modes. I will provide a.

  FIG. 9 shows a block diagram of an image processing apparatus according to the third embodiment. The operation of the control unit 1001 is different from that of the second embodiment, and the operation of the control unit 1001 will be described below. The control unit 1001 has a register 1003 for storing threshold values Th0 to Th7. When receiving the register setting command for setting the threshold value, the control unit 1001 sets, in the register 1003, the threshold values Th0 to Th7 for switching the storage destination bank at the grid point data setting. Further, the processing mode is set in the register 1005. For example, when operating the control unit 1001 and the processing unit 702 in the 17 grid mode, the control unit 1001 sets the threshold used in the process shown in FIG. 5 in the register 1003. That is, the control unit 1001 sets 729, 1377, 2025, 2601, 3249, 3825, 4401, 4913 as the thresholds Th0 to Th7. The 17 grid mode is set in the register 1005. The processing unit 702 can recognize the processing mode by referring to the register 1005.

After storing the lattice point data in the storage unit 103 after setting the threshold in the register 1003, the control unit 1001 refers to the threshold values Th0 to Th7 to obtain a bank and a memory address, and transmits the lattice point data to the storage unit 103. Store The control unit 1001 includes an address decoder 1004 to convert a register address into a bank and a memory address. The address decoder 1004 of the third embodiment operates as shown in the flowchart of FIG. Steps S601 and S602 in FIG. 10 are the same as those in FIG. The address decoder 1004 compares the value A obtained by dividing the register address by 4 with the threshold value set in the register 1003 (S1103, S1105, S1107, S1109, S1111, S1113, S1115, S1117). Then, according to the result of the comparison, the selected bank and memory address are determined (S1104, S1106, S1108, S1110, S1112, S1114, S1116, S1118). More specifically, banks and memory addresses are determined as follows.
(1) When 0 ≦ A <Th0, the bank is 0, and the memory address is A (S1103, S1104)
(2) When Th0 ≦ A <Th1, the bank is 1 and the memory address is A-Th0 (S1105, S1106)
(3) When Th1 ≦ A <Th2, the bank outputs 2 and the memory address A-Th1 (S1107, S1108)
(4) When Th2 ≦ A <Th3, the bank outputs 3 and the memory address A-Th2 (S1109, S1110)
(5) When Th3 ≦ A <Th4, the bank outputs 4 and the memory address A-Th3 (S1111, S1112)
(6) When Th4 ≦ A <Th5, the bank outputs 5 and the memory address A-Th4 (S1113, S1114)
(7) When Th5 ≦ A <Th6, the bank is 6 and the memory address is A-Th5 (S1115, S1116)
(8) When Th6 ≦ A <Th7, the bank is 7 and the memory address is A-Th6 (S1117, S1118)
(9) When Th7 ≦ A, the memory is not accessed.

  In the above example, the number of banks is eight, but the present invention is not limited to this. For example, when the processing unit 702 uses only four banks, registers “Th4” to “Th7”, which are not used, are set to “0”. As a result, the process always branches NO in steps S1111, S1113, S1115, and S1117 so that lattice point data is not stored in that bank. When the processing unit 702 uses a larger number of banks, the storage unit 103 has a memory of eight or more banks, and the register 1003 stores the threshold Th8 or more. And the versatility of the control unit can be further enhanced.

  Alternatively, a signal (for example, a signal representing the number of grids) representing a processing mode to be input to the processing unit 702 may be automatically generated from the threshold stored in the register 1003. That is, when the threshold Th0 is 729, the control unit 1001 outputs “17 Grid Mode = 1” as a signal indicating processing in the 17 grid mode to the processing unit 702. On the other hand, if the threshold Th 0 is 512, the control unit 1001 outputs “17 Grid Mode = 0” to the processing unit 702 as a signal indicating processing in the 16 grid mode. By doing this, the operation equivalent to the setting of 17GridMode to the register 703 described in the second embodiment can be performed, and the setting of 17GridMode to the register 1005 can be omitted. If there are only two modes that can be set, either one may be detected. In the present embodiment, the fact that bits other than the MSB are 0 when the threshold Th0 is 512 may be used to output a predetermined bit of the threshold Th0 as a signal to be processed in the 17 grid mode. Here, as the predetermined bit, for example, a bit (except for the MSB) which becomes 1 at the value 729 can be used, that is, any one of bits 0, 3, 4, 6, and 7.

  Even when the processing unit 702 supports only one processing mode of 17 grid mode only as in the first embodiment, the control unit 1001 as proposed in the third embodiment functions effectively. Of course, in that case, it is not necessary to output a signal indicating the processing mode to the processing unit 702.

  As described above, by adding a register for setting the memory map to the control unit and setting the register, the control unit does not need to store the memory map at the time of design, and versatility as an element part It is possible to improve the Further, regarding the setting of the lookup table data, the lookup table data can be set without adding unnecessary data even if the number of data is not a power of two.

(Other embodiments)
The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or storage medium, and one or more processors in a computer of the system or apparatus read and execute the program. Can also be realized. It can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

101: control unit, 102: processing unit, 103: storage unit, 104, 704, 1004: address decoder, 111: transfer unit, 112: DRAM, 113: input data, 703, 1003, 1005: register

Claims (12)

A data processing apparatus which loads data of lattice point data constituting one look-up table into a plurality of banks of memory represented by 2 ^M , where M is the number of axes constituting lattice point coordinates, and executes data processing There,
Receiving means for receiving grid point data to be loaded and a register address;
Conversion means for converting the register address received by the reception means into a bank specification and a memory address based on the number of lattice point data stored in the memory of each bank;
Storage means for storing the grid point data to be loaded in the memories of the plurality of banks in accordance with the bank designation and the memory address obtained by the conversion means ;
And the converting means, said register address, by comparing a threshold value with which according to the number of grid points data belonging to each of said plurality of banks, data processing, characterized that you determine the memory address and the bank designation apparatus.   In the register addresses, successive register addresses are assigned to all lattice point data constituting the one look-up table, and successive register addresses are allocated to lattice point data groups classified into each of the plurality of banks. The data processing apparatus according to claim 1, wherein the data processing apparatus is assigned corresponding to grid point coordinates.   3. The data processing apparatus according to claim 2, further comprising an assignment unit that assigns a register address to lattice point data forming the one look-up table. The conversion means determines the bank specification and the memory address by comparing a value obtained by dividing the register address by the number of register addresses allocated to one lattice point data with the threshold value. The data processor according to any one of claims 1 to 3 . The data processing apparatus according to any one of claims 1 to 4 , wherein the memories of each of the plurality of banks have different capacities according to the number of lattice point data belonging to each of the plurality of banks. . Classification of grid point data constituting one look-up table into the plurality of banks is based on a combination of odd and even coordinate values of each axis constituting grid point coordinates, and the number of axes is three. The data processing apparatus according to any one of claims 1 to 5 , wherein the number of dovetail banks is eight. The conversion means switches a method for converting the register address into a bank specification and a memory address in accordance with instruction information indicating one of a plurality of types of look-up tables having different numbers of grids per axis. The data processing apparatus according to any one of claims 1 to 6 , wherein The conversion means determines the bank specification and the memory address by comparing the register address with a set of threshold values set based on the number of lattice point data belonging to each of the plurality of banks.
The data processing apparatus according to claim 7 , wherein the set of the threshold is switched according to the instruction information. The conversion means determines the bank specification and the memory address by comparing the register address with a set of threshold values set based on the number of lattice point data belonging to each of the plurality of banks.
Holding means for holding the set of thresholds;
7. The apparatus according to any one of claims 1 to 6 , further comprising: changing means for changing the set of threshold values held in the holding means according to a look-up table loaded to the plurality of banks of memories. The data processing apparatus according to claim 1. Reading means for simultaneously reading a plurality of lattice point data from the plurality of banks of memories based on lattice point coordinates obtained based on input data;
Any one of claims 1 to 9, further comprising a, interpolation means for obtaining the converted data for the input data performs an interpolation process using a plurality of grid point data read by the reading means The data processing apparatus according to claim 1. A data processing apparatus that loads grid point data constituting one look-up table into a plurality of banks of memory represented by 2 ^M , where M is the number of axes constituting grid point coordinates, and executes data processing Control method, and
A receiving step of receiving grid point data to be loaded and a register address;
A conversion step of converting the register address received in the reception step into a bank specification and a memory address based on the number of lattice point data stored in the memory of each bank;
Accordance bank designation and a memory address obtained by the conversion process, have a, a storage step of storing grid point data of the load subject to memory of the plurality of banks,
In the conversion step, the bank specification and the memory address are determined by comparing the register address with a threshold value corresponding to the number of lattice point data belonging to each of the plurality of banks. Control method. The program for making a computer perform each process of the control method described in Claim 11 .

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