JPH0563967A - Three-dimensional data transforming device - Google Patents

Abstract

PURPOSE:To shorten time for reading a plurarity of transformed output data to be used for arithmetic interpolation in the transformation accompanying the arithmetic interpolation of the three-dimensional digital data. CONSTITUTION:The three-dimensional space composed of three-dimensional input digital data R, G, and B is divided into 2X2X2-unit cube. Corresponding to each apex of the unit cube, transformed output data is stored. Based on the eight combinations of even and uneven number of three-dimensional input data corresponding to each apex, the transformed output data is divided into eight to be stored in ROMs 1 to 8. A plurarity of transformed output data required for the arithmetic interpolation are parallely read out from the ROM selected based on the input data. The transformed output data corresponding to the input data is obtained by interpolating the reading result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional data conversion device, and more specifically, to a predetermined conversion rule for converting three-dimensional digital data represented by three primary color image data in a color printer, a color scanner, a color copying machine or the like. According to the invention.

[0002]

2. Description of the Related Art In color printers, color scanners, color copying machines, etc., color correction of color-separated digital image data obtained by photoelectric scanning is often performed. Although the color correction of the digital image data as described above may be performed by calculation, it has been corrected in advance corresponding to the combination of the color separated image data (for example, the combination of the three primary color image data of red R, green G and blue B). A combination of data (for example, ink amount of yellow Y, magenta M, cyan C, and black K) is stored as a conversion table, and a combination of data before correction is used as an addressing signal (correction output). Data)).

In the data conversion using the conversion table as described above, if a combination of correction data corresponding to all combinations of input data is stored, an enormous storage capacity is required and a memory used as a conversion table. Therefore, the converted output data is appropriately thinned out and stored, and the correction data corresponding to the combination of the input data corresponding to the thinned out portion is generally obtained by interpolation calculation.

As a technique for performing the data conversion using the conversion table with the interpolation calculation as described above, there are conventionally known Japanese Patent Publication No. 58-16180 and Japanese Patent Laid-Open No. 63-1.
There is one such as disclosed in Japanese Patent No. 62248. In Japanese Patent Publication No. 58-16180, the three-dimensional space formed by the three-dimensional input digital data is divided into a plurality of unit cubes, and the converted output data is stored in correspondence with the vertices of the plurality of cubes and converted. Configure the table.
Then, the unit cube is divided into a plurality of (5 or 6) tetrahedrons having four vertices out of the eight vertices of the unit cube, and four tetrahedrons including points corresponding to three-dimensional input data.
The converted output data at each vertex is read and
By interpolating two converted output data, the final converted output data for the three-dimensional input data is output.

Further, in Japanese Patent Application Laid-Open No. 63-162248, the cube is used as it is and interpolated from eight converted output data read corresponding to eight vertices of the cube including points corresponding to three-dimensional input data. The final converted output data is output by calculation. JP-B-58-16180 and JP-A-63-162248.
In the data conversion disclosed in the publication, etc., the number of conversion output data to be stored in the conversion table can be reduced by using the interpolation calculation to suppress the memory capacity small, and the nonlinear conversion can be performed with a small error. In addition, the hardware can be relatively small and a relatively high speed circuit can be realized.

[0006]

However, if an attempt is made to further speed up the processing in the data conversion as described above, the speeding up can be expected by devising the hardware in the interpolation calculation unit, but one conversion output data In order to obtain the above, n pieces of converted output data required for interpolation are read from the memory (conversion table), so that a time n times as long as the memory read cycle is required. Therefore, even if the speed of the interpolation calculation unit is increased, it is difficult to significantly reduce the processing time because it takes a relatively long time to read the converted output data. There is a problem that the processing time becomes long when the number of converted output data is relatively large such as eight.

The present invention has been made in view of the above problems, and by enabling a plurality of converted output data required for interpolation to be read in parallel, the time required for data reading can be greatly shortened. Therefore, the purpose is to speed up the data conversion process. Another object of the present invention is to easily realize parallel reading of converted output data without increasing the memory capacity.

[0008]

Therefore, a three-dimensional data conversion apparatus according to the present invention is a three-dimensional data conversion apparatus which converts three-dimensional input digital data according to a predetermined conversion rule and outputs the same. Configured as shown.
In FIG. 1, the conversion output data storage means divides the three-dimensional space formed by the three-dimensional input digital data into a plurality of units based on the unit polyhedron, and outputs the conversion output data corresponding to each vertex of the plurality of unit polyhedra. The storage means is a means for storing converted output data in a plurality of independent storage means so that the stored contents are different from each other.

The conversion output data reading means is one of the conversion output data converting means for converting the conversion output data corresponding to a predetermined vertex of the unit polyhedron including the points on the three-dimensional space corresponding to the three-dimensional input digital data. The data is read in parallel from the above storage means. Then, the interpolation calculation means obtains and outputs converted output data corresponding to the three-dimensional input digital data by interpolation calculation based on the converted output data read in parallel by the converted output data reading means.

Here, the conversion output data storage means is
It may be configured by the same number of storage units as the number of vertices of the unit polyhedron, and the converted output data corresponding to each vertex of the unit polyhedron may be divided and stored in different storage units. In addition, each vertex of the unit polyhedron is divided into a plurality of groups including at least one group of a plurality of vertices,
The conversion output data storage means may be configured by dividing and storing the conversion output data corresponding to each vertex of the unit polyhedron in the storage means of the number corresponding to the number of divisions according to the division.

Further, the unit polyhedron is a cube, and each vertex of this unit cube is represented by a three-dimensional coordinate value with one side length of the unit cube being 1, and even or odd three-dimensional coordinate values corresponding to each vertex. It is also possible to divide the converted output data into eight in accordance with the eight combinations of, and divide and store in each of the eight storage means. Further, the unit polyhedron is a cube, and each vertex of the unit cube is a unit cube.
The converted output data is divided into four groups according to the remainder when the sum of the three-dimensional coordinate values corresponding to each vertex is divided by 4, and the converted output data is divided into four groups, and stored in four storage means. Each can be divided and stored.

[0012]

That is, the converted output data is stored in a plurality of independent storage means so that the stored contents are different from each other, and the converted output data can be read in parallel from one or more of the plurality of storage means. By letting you do
The converted output data required for interpolation is read in one read cycle.

If the conversion output data corresponding to each vertex of the unit polyhedron is divided and stored in the same number of storage units as the number of vertices of the unit polyhedron, all the vertices of the unit polyhedron are supported. It is possible to read the converted output data in parallel. Further, each vertex of the unit polyhedron is divided into a plurality of groups including at least one group of a plurality of vertices, and the converted output data corresponding to each vertex of the unit polyhedron is stored in a number of storage means corresponding to the number of divisions. Is configured to be divided and stored according to the division, the converted output data can be read in parallel for each group of vertices.

Here, when the unit polyhedron is a cube, if each vertex of this unit cube is represented by a three-dimensional coordinate value with one side length of the unit cube being 1, the three-dimensional corresponding to each vertex The converted output data can be divided into eight for each vertex according to eight combinations of even and odd coordinate values, and based on this, the converted output data can be divided and stored in each of the eight storage means. For example, based on the combination of the even and odd three-dimensional coordinate values of the vertices desired to be read, it is possible to select the storage means in which the converted output data corresponding to the relevant vertices are stored and perform the reading in parallel. ..

Further, the converted output data of each vertex of the unit cube can be divided into four groups according to the remainder when the sum of the three-dimensional coordinate values is divided by 4, and in this case, for four storage means. And storing the converted output data in correspondence with the division, selecting from four storage means according to the remainder when the sum of the three-dimensional coordinate values is divided by 4, and parallelizing for each of the four groups. Can be read.

[0016]

EXAMPLES Examples of the present invention will be described below. In FIG. 2 showing the system configuration of the first embodiment, three-dimensional input digital data is N for each three primary colors (red R, green G, blue B).
It is bit image data, for example, a color separation signal obtained by photoelectrically scanning a color original image. In this embodiment, the above 3
The primary color digital image data is converted according to a preset conversion rule, and finally output as N-bit digital image data of four colors of cyan C, magenta M, yellow Y, and black K. It is for converting the color separation signals of the R, G, and B3 primary colors read in to the C, M, Y, and K ink amounts in order to properly reproduce the printed matter, for example.

The conversion table, which will be described later, for performing the conversion does not store the converted output data corresponding to all combinations of the input digital data, but the three-dimensional space formed by the input digital data is converted into the input digital data. Is a unit cube having a size twice as large as the quantization unit of 1 side length and storing converted output data corresponding to each vertex of the unit cube. In other words, input digital data Only the converted output data corresponding to an even combination of are stored.

Therefore, the corresponding point in the three-dimensional space of the input digital data (hereinafter referred to as the input data point).
As shown in FIG. 3, it is located at any of the vertices, the sides (between vertices), the faces, and the inside of the unit cube. Here, when the input data point is located at the apex (circle), the converted output data corresponding to the apex may be read out and output as it is, and when the input data point is located on the side (circle), the vertices at both ends thereof may be read. Read out the converted output data corresponding to each, and interpolate by averaging them,
When located on the surface (marked with ⋄), the converted output data corresponding to the four vertices of the surface including the input data points are read, these are averaged and interpolated, and when located inside (marked with), the input data The converted output data corresponding to the 8 vertices of the unit cube including the points are read out, and these are averaged and interpolated.

For example, to interpolate the point (a) on the R axis in FIG. 3, the average of the converted output data (known data stored in the conversion table) of the vertices a and b existing on the R axis is taken. To interpolate. That is, if the three-dimensional coordinate value of the point (a) is (r + 1, g, b), the vertex a is (r, g,
b), the vertex b is (r + 2, g, b), and the interpolated converted output data f (r + 1, g, b) is f (r + 1, g, b) = {f (r, g, b) ) + F (r +
2, g, b)} / 2. Where f (r, g, b)
Is the converted output data of the vertex a, and f (r + 2, g,
b) is the converted output data of the vertex b.

Whether the input data points are located at the vertices, on the sides (between the vertices), on the surface, or inside of the unit cube, the conversion table stores the conversion output data only for even combinations of the input digital data. Therefore,
As shown in FIG. 4, the determination can be made based on the even / odd discrimination of each input digital data based on the least significant bit of each input digital data.

That is, when the least significant bits of the three-dimensional input data are all 0s and the respective input digital data are all even, the input data point is located at the vertex of the unit cube, and 2 of the least significant bits are located. One is 0 and the rest is 1 and 2
If one is an even number and the other one is an odd number, the input data point is located on the side of the unit cube and one of the least significant bits is
One is 0 and the other two are 1 and one is even and the remaining 2
If one is an odd number, the input data point is located on the surface of the unit cube, and further, if all of the least significant bits are 1 and the input digital data are all odd, it is located inside the unit cube. It will be. Furthermore, when the input data point is located on the side or the surface, the side or surface on which the input data point is located can be specified by the even / odd combination state. Since the vertices from which the converted output data used for the calculation should be read can be specified, there are eight interpolation calculation modes depending on the difference in the converted output data to be read, as shown in FIG.

Therefore, the converted output data corresponding to a predetermined vertex is read from the conversion table according to the corresponding position discrimination of the input data point with respect to the unit cube as described above,
If this is averaged and interpolated, all input digital data can be converted and output according to a predetermined conversion rule. In the present embodiment, the converted output data is RO.
Instead of storing in one memory (storage means) represented by M, eight ROs matching the number of vertices of a unit cube
M1 to ROM8 are divided and stored, and these ROM1
The conversion output data can be read in parallel from the ROM 8 so that even if a plurality of conversion output data are required for interpolation, the reading of the conversion output data is completed in one read cycle.

In the present embodiment, the eight ROMs
1 to ROM8 correspond to storage means, respectively, and these eight ROM1 to ROM8 constitute a conversion output data storage means to be a conversion table. The 8 ROMs 1
The division of the converted output data to the ROM 8 is performed as follows. That is, as described above, the three-dimensional space formed by the input data is set to the quantization unit 2 of the input data.
Since the double size is divided into a plurality of unit cubes with one side and the converted output data is stored only for the combination of even input digital data, the input digital data corresponding to each vertex of the unit cube is 4 Based on the remainder when the division is performed, each vertex of the unit cube can be classified into eight types as shown in FIG. 5, and the converted output data for the same combination of the remainders are stored in the same ROM. That is, since the input digital data corresponding to the vertices of the unit cube are all even numbers, the lower 2 bits corresponding to the remainder when this input digital data is divided by 4 are 10 or 00, and the remainder is either 0 or 2. Since the combination is different at each vertex of the unit cube, each vertex can be specified by the combination.

In FIG. 5,% 4 indicates the remainder (remainder) when divided by 4. If each vertex of the unit cube is represented by three-dimensional coordinates in which the length of one side of the unit cube is 1, the result is as shown in FIG. 6 regardless of the actual length of one side. However, it is possible to distinguish into eight by different combinations of even and odd three-dimensional coordinate values. In the case of the present embodiment, the converted output data is stored in correspondence with only the combination of even data as described above. Therefore, the same distinction is made as the remainder when the input digital data is divided by 4 as described above. That is, the coordinate value = 1 shown in FIG. 6 corresponds to the remainder 2 shown in FIG.

Here, the relationship between the address data of each of the ROM1 to ROM8 and the converted output data is as follows. That is, in this embodiment, the combination of the upper N-2 bits of the three-dimensional input digital data is used as the address of each of the ROMs 1 to 8, and the upper N-2 bits of the input digital data are combined as they are to form an address signal. In this case, the converted output data of the vertices of the unit cube including the input data points are output from each of the ROM1 to ROM8.

The outputs of the ROM1 to ROM8 when the address data of (r, g, b) are given are R1 (r, g, b).
˜R8 (r, g, b), and the value obtained by converting the input digital data corresponding to the vertices of the unit cube according to a predetermined conversion rule is f (4r + α, 4g + β, b).
+ Γ), the address data is designated as a combination of the upper N-2 bit data of each N-bit input digital data, and therefore the conversion characteristics in each ROM1 to ROM8 are expressed as follows (see FIG. 8). ).

ROM1 R1 (r, g, b) = f (4r, 4g, 4b) ROM2 R2 (r, g, b) = f (4r + 2,4g, 4b) ROM3 R3 (r, g, b) = f (4r, 4g + 2,4b) ROM4 R4 (r, g, b) = f (4r + 2,4g + 2,4b) ROM5 R5 (r, g, b) = f (4r, 4g, 4b + 2) ROM6 R6 (r, g, b) b) = f (4r + 2,4g, 4b + 2) ROM7 R7 (r, g, b) = f (4r, 4g + 2,4b + 2) ROM8 R8 (r, g, b) = f (4r + 2,4g + 2,4b + 2) For example, ROM1 stores converted output data corresponding to the case where all input digital data are multiples of 4, and ROM2 corresponds to red R when the input digital data is divided by 4. You Are those in which only data is stored converted output data corresponding to the remainder are 0 at 2, below, ROM3～ROM8
Is also the same. Therefore, 3D input data is 4
It is possible to determine which address designation signal should be given to which ROM based on the remainder (lower 2 bits of the input digital data) divided by, and the state of such interpolation calculation is shown in FIG. .. The interpolation mode of FIG. 7 corresponds to the mode of FIG.

For example, when the three-dimensional input digital data is (4r + 3, 4g, 4b), it corresponds to the mode (2) in FIG. 4 and is located on the side of the unit cube as shown in FIG. Will be done. Then, of the converted output data obtained by addressing with (r, g, b) which is a combination of the upper N-2 bits of the input digital data, the converted output data R obtained from the ROM 2
2 (r, g, b) is the input data point (4r + 3,4g,
4b) corresponds to the apex X at one end and the other apex Y
Since the coordinates of is (4r + 4, 4g, 4b), the converted output data corresponding to such a vertex is R1 (r + 1, g,
b) (see FIG. 8).

Therefore, the address data using the upper N-2 bits of the input digital data as it is is given to the ROM2, and at the same time, only the address data corresponding to the red R of the address data given to the ROM2 is given to the ROM1. By incrementing it and giving it as address data, as a result, the conversion output data corresponding to the vertices at both ends of the input data point located on the side of the unit cube can be read in parallel. If the data are averaged and interpolated, the converted output data corresponding to the input data points can be obtained.

Here, the hardware configuration for converting the above three-dimensional data will be described in detail with reference to FIG. First, the N-bit R, G, B color-separated signal is separated into lower 2 bits and upper N-2 bits, which represent the remainder when the three-dimensional input digital data is divided by 4, respectively. Then, the lower 2 bits are input to the selector 20,
The upper N-2 bits are used as an addressing signal for each ROM.
1 to ROM8, the address designated as a combination of the upper N-2 bits needs to be changed as shown in FIG. 7, and therefore the incrementer 1 for incrementing the upper N-2 bits is used. ~ 12 are provided.

The incrementers 1 to 12 are selectors 20.
Based on the 1-bit incrementer control signals I _{1 to} I _{12 from}
Whether to output the bit data as it is or to add and output 1 is individually controlled.

[0032]

[Table 1]

Here, since the address data given to each of the ROM1 to ROM8 is controlled by the incrementers 1 to 12, the incrementers 1 to 12 and the selector 20 for controlling the incrementers 1 to 12 are used in the present embodiment. It corresponds to the conversion data reading means, and each ROM 1
~ ROM8 corresponds to the individual storage means constituting the conversion output data storage means.

The outputs from the ROM1 to ROM8 are RO
Four adders 21 to 24, with two as one set in the order of M numbers
To the adder 25, the outputs of the adders 21 and 22 are input to the adder 25, the outputs of the adders 23 and 24 are input to the adder 26, and the outputs of the adder 25 and the adder 26 Is input to the adder 27, and finally the total of the eight pieces of converted output data is output from the adder 27, and the division processing circuit 28 including a bit shifter or the like outputs 1
It is divided by / 8, averaged, and output.

Therefore, the interpolation calculation means in this embodiment is composed of the adders 21 to 27 and the division processing circuit 28. Each of the adders 21 to 27 has control signals R1 to R from the selector 20 in addition to terminals A and B for inputting two signals to be added.
8 is input to the input terminals of SA and SB, and as shown in Table 2, the content of the addition processing is controlled according to the control signals R1 to R8.

[0036]

[Table 2]

In FIG. 2, R12 is R1 and R
2 represents a logical sum, R34 represents a logical sum of R3 and R4, and R56 and R78 are the same. Further, R1234 represents a logical sum of four control signals of R1 to R4, and R5678 represents a logical sum of four control signals of R5 to R8. The addition dexterity control signal R1~R8 and incrementer control signal I ₁ ~I ₁₂ in such a configuration, which is output from the selector 20 as described above, the selector 20, the input digital data inputted as shown in FIG. 9 based on the lower 2-bit data, to change the output of the addition dexterity control signal R1~R8 and incrementer control signal I ₁ ~I _12.

The mote number in FIG. 9 is the same as that in FIG.
It corresponds to the mode number in. For example, when the three-dimensional input data is (4r + 3, 4g, 4b), it corresponds to the mode number 4 in FIGS. 7 and 9. At this time, as the adder control signals R1 to R8, only R1 and R2 are output at a high level, and the remaining control signals R3 to R8 are all output at a low level. Further, of the incrementer control signals I _{1 to} I ₁₂ , only the control signal I ₁ is output at a high level, and the remaining I _{2 to} I ₁₂ are output.
All ₁₂ are output to low level.

The control signal I ₁ is input to the incrementer 1, and the incrementer 1 is input to the ROM 1 by R.
The input data (higher order N-2 bit data of originalidyl) corresponding to is incremented. As a result, the address (r + 1, g, b) is given to the ROM 1 and the other ROMs 2 to 8 are given. , The upper N-2 bits of the input digital data are used as they are, and the (r, g, b) address is given, and each RO
The converted output data is read in parallel from M1 to M8.

Since only R1 and R2 of the control signals R1 to R8 are high level, the adder 21 outputs RO
Although the output of M1 and the output of ROM2 are added, the outputs of the other adders 22 to 24 are 0 (see Table 2). Further, in the adder 25, since R12 is at the high level and R34 is at the low level, the processing of doubling the output of the adder 21 is performed, and the processing result is output to the adder 27. On the other hand, both inputs of the adder 26 are 0, and since both control signals are low level, 0 is output to the adder 27.

In the adder 27, since the control signal input to the SA terminal becomes high level, the process of doubling the value input to A is performed, and the addition of the outputs of ROM1 and ROM2 is performed by the adder. 21. The processing of doubling the addition result is performed by the adder 25, and the output from the adder 25 is further increased by 2
The doubling process is performed by the adder 27, resulting in R
The sum of the output of the OM1 and the output of the ROM2 is multiplied by four, and the division processing circuit 28 divides it by 1/8 to obtain the ROM.
The output of 1 and the output of ROM 2 are averaged and finally output.

In each of the ROM1 to ROM8, C, M,
A select signal (2-bit signal) for outputting only one color data in the combination of Y and K conversion output data is input. For example, when cyan C is selected, The cyan C data is output from the ROM1 to ROM8, and finally the cyan C digital data corresponding to the R, G, B three-dimensional input digital data is output.

As described above, in the present embodiment, the conversion output data is divided into eight ROM1 to ROM8 corresponding to the maximum number of read outs of the conversion output data and stored, and the conversion output data is read out in parallel from these. And, of course, 1
Since it is not necessary to read two or more converted output data from one ROM 1 to 8, even if there is only one converted output data used for the interpolation calculation (when the input data point is located at the vertex of the unit cube), Even if the input data points are located inside the unit cube, the reading of the converted output data can be completed in one read cycle, and all the converted output data can be stored in one ROM. The processing time can be greatly shortened as compared with the case of reading the necessary converted output data in time series.

Since the converted output data can be divided and stored in each of the ROM1 to ROM8, each ROM can be stored.
1 to ROM 8 have no conversion output data redundantly stored, and the system can be realized with the same memory capacity as when all conversion output data is stored in one ROM.
In the above embodiment, it is determined whether the input data point is located at the vertex, the side, the surface, or the inside of the unit cube dividing the three-dimensional space formed by the input digital data. , Output data of 4 or 8 vertices is simply averaged, but 8 of unit cube including input data points
It is also possible to read all the converted output data of the vertices, weight the read converted output data, and interpolate the converted output data corresponding to the input data points.

Next, a second embodiment whose system configuration is shown in FIG. 10 will be described. In the second embodiment, as shown in FIG. 11, the three-dimensional space formed by the three-dimensional input digital data is converted into two units of the quantization unit of the input digital data.
Unit cube (2 × 2 × 2) with double dimension as one side length
The unit cube is divided into a plurality of pieces, and the converted output data corresponding to each vertex of the unit cube is stored in the conversion table. Further, the unit cube is divided into six tetrahedra to be included in the unit cube. Input data points
It is designed to be regarded as being located at the apex of the unit cube or on any side of the six tetrahedrons.

Therefore, in the second embodiment, when the input data points are located on the sides of the tetrahedron, the converted output data of the vertices located at both ends of the tetrahedron are read out, and when the input data points are located at the vertices of the unit cube. It suffices to read the converted output data corresponding to the vertex, and the maximum number of converted output data required for the interpolation calculation is 2. Here, also in this embodiment, the converted output data is stored only for even combinations of the input digital data,
The converted output data according to the predetermined conversion rule stored corresponding to each vertex of the unit cube can be expressed as shown in FIG. 12, and based on this, the input data points are on the sides of the tetrahedron or the unit cube. The interpolation calculation when it is located at the vertex of
(2r, 2g, 2b) should always be used and performed as follows.

F (2r, 2g, 2b) = f (2r, 2g, 2b) f (2r + 1,2g, 2b) = (f (2r, 2g, 2b) + f (2r + 2,2g, 2b)) / 2 f (2r, 2g + 1,2b) = (f (2r, 2g, 2b) + f (2r, 2g + 2,2b)) / 2 f (2r + 1,2g + 1,2b) = (f (2r, 2g, 2b) + f (2r + 2, 2g + 2,2b)) / 2 f (2r, 2g, 2b + 1) ＝ (f (2r, 2g, 2b) ＋ f (2r, 2g, 2b ＋ 2)) / 2 f (2r + 1,2g, 2b + 1) ＝ (f (2r, 2g, 2b) ＋ f (2r ＋ 2,2g, 2b ＋ 2)) / 2 f (2r, 2g ＋ 1,2b ＋ 1) ＝ (f (2r, 2g, 2b) ＋ f (2r, 2g ＋ 2,2b ＋ 2)) / 2 f (2r ＋ 1,2g ＋ 1, 2b + 1) = (f (2r, 2g, 2b) + f (2r + 2,2g + 2,2b + 2)) / 2 As described above, in the present embodiment, the maximum number of conversion output data necessary for interpolation is 2, Even if the output data is read out in time series, the processing time is not significantly increased, but in order to further shorten the processing time, the converted output data is stored in the converted output data storage as in the first embodiment. The four ROMs (rom1 to rom4) are converted so that they can be read in parallel from a plurality of memories (storage means) that constitute the means. Is divided and stores the output data, these rom1
Two or one converted output data can be read in parallel from ~ rom4.

Also in this embodiment, as in the first embodiment, the interpolation operation can be performed by dividing and storing the converted output data in eight ROMs corresponding to the number of vertices of the unit cube.
As described above, it is not necessary to read eight converted output data at a time. Therefore, in order to simplify the circuit configuration of an adder or the like for adding ROM outputs, four converted output data are used in accordance with the regularity shown below. Divided into four ROMs and stored.

That is, as shown in FIG. 13, 1 of unit cube
If the side length is represented by three-dimensional coordinates, the coordinates of each vertex are represented as shown in FIG. 13 regardless of the actual length of one side, and the total sum of the three-dimensional coordinate values of each vertex is calculated. If divided by 4, the remainder at each vertex becomes 0, 1, 2, or 3, and by summarizing the same vertices, the 8 vertices of the unit cube can be divided into four groups. The converted output data is divided and stored in the respective rom1 to rom4 corresponding to the vertex group. The four groups are
1st group consisting of 1 vertex with a remainder of 0, 2nd group consisting of 3 vertices with a remainder of 1, 3rd group consisting of 3 vertices with a remainder of 2nd, 4th group consisting of 1 vertex with a remainder of 3 In the present embodiment, the converted output data corresponding to the vertices of the first group is stored in rom1.
m2, the third group corresponds to rom3, and the fourth group corresponds to rom4.

Here, the actual input data (r, g, b)
The formula for selecting rom1 to rom4 based on
Assuming that the remainder when divided by, is shown as follows. rom number = (r / 2, g / 2, b / 2)% 4 + 1 (1) In this way, the value obtained by mutually adding the upper bits except the least significant bit of the input digital data is divided by 4. , The value obtained by adding 1 to the remainder indicates the numbers 1 to 4 of rom, and the conversion output data of adjacent vertices are the same rom.
Therefore, the converted output data required for interpolation is always read in parallel from different rom1 to rom4. Further, if the conversion output data is divided into four ROMs and stored as described above, the conversion output data will not be redundantly stored and the memory capacity will not be wasted. ..

The converted output data rom1 to 4 (r, r) obtained on the basis of the address signals given to the respective rom1 to rom4.
g and b) are as follows, and different converted output data can be obtained from rom1 to rom4 by giving the same address signal. rom1 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g + 3)% 4)) rom2 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g + 2))% 4 )) Rom3 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g + 1)% 4)) rom4 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g)) % 4)) As will be described later, since the input digital data of this embodiment is 6 bits, the upper 5 bits excluding the least significant bit of the R and G input digital data and the upper 3 bits excluding the lower 3 bits of B are used. If a combination with data is given as the address data, the 5-bit address data corresponding to R and G is fixed, and the 5-bit address data of B is XXX00, XX01, XX10, XX 11 of 4
The same conversion result as when changing the
It can be obtained from 1-4.

Here, the hardware configuration shown in FIG. 10 will be described. First, in the second embodiment, as described above, the R, G, B primary color separation signals are 6 bits [0. ． 5]
Input as digital data. Then, the upper 5 bits of each input digital data [1. ． 5] is D-
It is inputted to the flip-flop 31 and the I terminals of the respective incrementers 32, 33 and 34 corresponding to R, G and B respectively.
To the INC terminals of the incrementers 32, 33, 34, the least significant bits R0, G0, B0 of each input data are also input at the same time, and the upper 5 bit data [ 1. ． 5] is incremented.

That is, the least significant bit R0 of each input data,
When G0 and B0 are zero (low level), the input 5-bit data is output as it is, and the least significant bits R0, G0, and B0 are 1 (high level) and are input. When the 5-bit data is 00H to 1EH, 1 is added to the input 5-bit data and output. Further, if the least significant bits R0, G0, B0 are 1 (high level) and the input 5-bit data is 1FH, adding 1 adds 00H, so increment it. Instead, the input 5-bit data is output as it is.

Therefore, when any of the input 6-bit data is an odd number (when one or two of the least significant bits is 1), the unit cube is divided as described above. Since it is located on the side of the tetrahedron, the upper 5 bits of the original data point to the vertex at one end of the side, and the increment allows the vertex at the other end of the side to be addressed.

The original upper 5 bit data and the 5 bit data (two types of address data) via the incrementers 32, 33 and 34 are output to the D-flip-flop 35 via the D-flip-flop 31. It is input to the addition selection circuits 36 and 37. In the addition selection circuits 36 and 37,
As shown in FIG. 15, when the lower 2 bits of the input R, G, B 5-bit data are summed and the sum is divided by 4, the remainder is 0, 1, 2, 3 Then, only one selected from the four outputs S1 to S4 is set to the high level and is output to the D-flip-flop 35. That is, the processing in the addition selection circuits 36 and 37 is
Corresponding to the setting of the rom number in the equation (1), the outputs S1 to S4 of the addition selection circuits 36 and 37 become the rom1 to 4 selection control signals.

The two kinds of address data are input to the selection circuits 38 to 41 after passing through the D-flip-flop 35. Here, since the lower 2 bits of the 5-bit address data corresponding to B are unnecessary, the lower 2 bits are deleted and output when output from the D-flip-flop 35. The outputs S1 to S4 of the addition selection circuit 37 are input to the selection circuits 38 to 41, respectively. Then, as shown in FIG. 16, the selection circuits 38 to 41 output the output S1 of the addition selection circuit 37 input to the SEL terminal.
Depending on the level of S4 to S4, one of the two types of address data input to the terminals A1 to A3 and B1 to B3 is selected and output.

For example, when the total value of the address data obtained through the incrementers 32, 33, 34 is a multiple of 4 (remainder zero) and S1 is output as a high level signal, the selection circuit 38 Output the address data obtained via the incrementers 32, 33, 34, and the other selection circuits 39 to 41 output the address data as the original upper 5 bit data as they are.

The address data selected by each of the selection circuits 38 to 41 is input to the D-flip-flop 42, and the addition selection circuit 36 is also included in the D-flip-flop 42.
A signal obtained by calculating the logical sum (S1orS1 ′, S2orS2 ′ ...) Of corresponding outputs in the addition selection circuit 37 by the logical sum circuits 43 to 46 is input.

The address data via the D-flip-flop 42 is output to the four rom (1) 47 to rom (4) 50, and the conversion output data (prestored at the corresponding address of each rom1 to rom4 ( 1 for Y, M, C, K
Color selection signal (YMCK-Se)
6-bit data of the color designated by (lect) is read in parallel.

As described above, in the second embodiment, each rom
The output of the address data to (1) 47 to rom (4) 50 is performed by incrementers 32 to 34, addition selection circuits 36 and 37, selection circuits 38 to 41, logical sum circuits 43 to 46, and a plurality of D-flip-flops 31. , 35, 42, and these correspond to the conversion output data reading means in the second embodiment. Also, rom (1) 47 to rom (4) 50 correspond to the four storage means forming the converted output data storage means.

The converted output data from each of rom (1) 47 to rom (4) 50 is passed through the D-flip-flop 51 to 2
One set is input to the adder circuits 52 and 53. In the adder circuit 52, the logical sum circuit 4 together with the converted output data is added.
The outputs from 3 and 44 are input respectively, and similarly, the output from the OR circuits 45 and 46 is input to the adder circuit 53.
The addition process is performed by the logic shown in FIG.

That is, in the adder circuits 52 and 53, rom (1) 47 to rom (4) 50 are added in accordance with the outputs from the logical sum circuits 43 to 46.
The converted output data from (1) is selected and output, the simple average is output, or the converted output data is output as zero. The converted output data from the two adding circuits 52 and 53 are input to the adding circuit 55 via the D-flip-flop 54. The adder circuit 55 includes an OR circuit 4
The output of the logical sum circuit 56 that calculates the logical sum of the outputs of 3 and 44 and the output of the logical sum circuit 57 that calculates the logical sum of the outputs of the logical sum circuits 45 and 46 are input.

The adder circuit 55 also performs addition processing by the logic shown in FIG. 17, and the output of the adder circuit 55 is output as final converted output data via the D-flip-flop 58. Second as above
In the embodiment, the adder circuits 52, 53, 55 and the D-flip-flops 51, 54, 58 controlled by the logical sum circuits 43 to 46, 56, 57.
The interpolation calculation means is constituted by.

Incidentally, each rom (1) 47 to rom (4) 50
In response to the following characteristics described above, outputs the converted output data of the input data points corresponding to the vertices of the unit cube corresponding to the color selection signal, as shown in FIGS. rom1 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g + 3)% 4)) rom2 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g + 2))% 4 )) Rom3 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g + 1)% 4)) rom4 (r, g, b) = f (2r, 2g, 2 (4b + 3- (r + g)) % 4)) Next, the operation of the circuit of FIG. 10 described above will be described by taking a typical example.

For example, the remainder when the total value of the original address data consisting of the upper 5 bit data is divided by 4 is zero, and the total of the address data obtained through the incrementers 32 to 34 is divided by 4. When the remainder is 1
It was. At this time, the output of the addition selection circuit 36 is S1.
Only the S2 of the output of the addition selection circuit 37 becomes the high level. This allows the selection circuit
Only the selection circuit 39 of 38 to 41 can increase the incrementers 32 to 34.
The address data obtained through the above is selected and output, and the remaining selection circuits 38, 40 and 41 output the original upper 5 bit data as the address data. Therefore,
Of rom (1) 47 to rom (4) 50, rom (2)
Only 48 is given the address data obtained through the incrementers 32-34, and rom (1) 47-rom (4) 50
The converted output data are output in parallel.

Since the outputs of the OR circuits 43 and 44 are both at high level, the adder circuit 52 outputs rom
The output of (1) 47 and the output of rom (2) 48 are simply averaged and output. On the other hand, since the outputs of the OR circuits 45 and 46 are both at the low level, the output of the adder circuit 53 is zero. Furthermore, since the output of the OR circuit 56 is at the high level and the output of the OR circuit 57 is at the low level, the adder circuit 55 outputs the output of the adder circuit 52 as it is.
The simple average value of the outputs of rom (1) 47 and rom (2) 48 is output as the final converted output data.

That is, since the addition selection circuit 36 determines that the remainder when the total value of the address data given as the original upper 5 bits of data is divided by 4, the remainder rom (1 ) 47 is given the address data, and the converted output data is treated as valid, while the remainder is 1 when the total value of the address data obtained as a result of the increment at the incrementers 32 to 34 is divided by 4. Because there was, ro corresponding to the remainder 1
The address data is given to m (2) 48 so that the converted output data can be read out in parallel from each of them. Then, the converted output data corresponding to the two vertices of the unit cube are averaged and interpolated to obtain the converted output data corresponding to the input data point located in the middle of the two vertices.

In other words, the outputs S1 to S4 from the addition selection circuits 36 and 37 are rom (1) 47 to rom, respectively.
(4) The conversion output data of rom (1) 47 to rom (4) 50 corresponding to 50 is output as a valid value only when a high level signal is output from at least one of the addition selection circuits 36 and 37. It is handled, and rom (1) 47〜
A maximum of two of the converted output data read out in parallel from rom (4) 50 is valid, and finally a simple average of the two converted output data is obtained, which divides the unit cube. This corresponds to the case where the input data points are located on the sides of the face piece.

On the other hand, when the input data points coincide with the vertices of the unit cube, it means that the three-dimensional input digital data are all even, so that the address data given as the upper 5 bit data of the original (6 bits). When,
The address data obtained via the incrementers 32-34 will be the same. Therefore, in the addition selection circuits 36 and 37, S
Since the same output in 1 to S4 is output as a high level, only one of the four converted output data read in parallel from each of rom (1) 47 to rom (4) 50 is selected and finally selected. It will be output as it is.

In the first embodiment, one side of the unit cube is twice the quantization unit of the input digital data, but this is generalized and set to 2 ^k (k ≧ 1) times. I shall. In this case, when all the three-dimensional input digital data are integer multiples of 2 ^k , only the corresponding conversion output data is stored in the conversion table.
As shown in FIG. 22, the input digital data is set to 2 ^{k + 1.}
The converted output data is divided into 8 by the remainder when divided by
It can be divided into two and stored. Such a characteristic is merely a generalization of the characteristic when k = 1 shown in FIG.

The outputs R1 to R8 (r, g, b) obtained when the address data (r, g, b) are given to each ROM divided as shown in FIG. 22 are as follows. Converted output data f corresponding to input digital data
(R, g, b). R1 (r, g, b) = f (2 ^{k + 1} r, 2 ^{k + 1} g, 2 ^{k + 1} b) R2 (r, g, b) = f (2 ^{k + 1} r + 2 ^k , 2 ^{k + 1} g, 2 ^{k + 1} b) R3 (r, g, b) = f (2 ^{k + 1} r, 2 ^{k + 1} g + 2 ^k , 2 ^{k + 1} b) R4 (r, g, b) = f ( 2 ^{k + 1} r + 2 ^k , 2 ^{k + 1} g + 2 ^k , 2 ^{k + 1} b) R5 (r, g, b) = f (2 ^{k + 1} r, 2 ^{k + 1} g, 2 ^{k + 1} b + 2 ^k ) R6 (r, g, b) = f ( ^{2k +} 1r + ^2k , ^{2k +} 1g, ^{2k +} 1b + ^2k ) R7 (r, g, b) = f ( ^{2k +} 1r, ^{2k +1} g + 2 ^k , 2 ^{k + 1} b + 2 ^k ) R8 (r, g, b) = f (2 ^{k + 1} r + 2 ^k , 2 ^{k + 1} g + 2 ^k , 2 ^{k + 1} b + 2 ^k ) Here, as described above If one side of the unit cube is 2 ^k times the quantization unit of the input digital data, then each R
It is necessary to perform weighting on the converted output data read in parallel from the OM1 to ROM8, and when the system configuration shown in FIG. 2 is rewritten by adding the configuration for performing such weighting, it becomes as shown in FIG. In FIG. 23, each R
The incrementers 1 to 12 corresponding to the OM1 to ROM8 are
It is provided similarly to FIG. Further, Rk, Gk, and Bk input to the incrementers 1 to 12 in FIG. 23 are 0 bits, 1 bits for each bit of the input digital data that is n bits.
, ..., k-1 bit, k bit, ... n-1
It shall indicate the value of k bits when expressed as bits.

In the configuration shown in FIG. 23, the lower k + 1 bits of the n-bit three-dimensional input digital data are input to the weighting coefficient generator 71, and the weighting coefficient generator 71 outputs each R.
A weighting factor W for multiplying and correcting the converted output data read in parallel from the OM1 to ROM8 in each of the multipliers 72 to 79.
1 to W8 are output. The setting of the weighting factors W1 to W8 is
Perform as follows.

W1 = (2 ^k −R ′) · (2 ^k −G ′) · (2 ^k −B ′) W2 = R ′ · (2 ^k −G ′) · (2 ^k −B ′) W3 = ^{(2 k -R ') · G} ' · (2 k -B ') W4 = R' · G '· (2 k -B') W5 = (2 k -R ') · (2 k -G') · B 'W6 = R' · (2 k -G ') · B' W7 = (2 k -R ') · G' · B 'W8 = R' · G '· B' where, R '= R [ 0. ． k−1] (when Rk = 0) R ′ = 2 ^k −R [0. ． k−1] (when Rk = 1) G ′ = G [0. ． k−1] (when Gk = 0) G ′ = 2 ^k −G [0. ． k−1] (when Gk = 1) B ′ = B [0. ． k−1] (when Bk = 0) B ′ = 2 ^k −B [0. ． k-1] (when Bk = 1) [0. ． k−1] indicates lower k bit data.

In the multipliers 72 to 79, each of the ROM1 to ROM8
After multiplying the n-bit converted output data read in parallel from the above by the weighting factors W1 to W8, the carry amount is bit-shifted to be converted into the original n-bit data, which is then output. The outputs from 72 to 79 are adders
All are added at 80 and finally output as converted output data.

By the way, in each of the above embodiments, the converted output data is divided into a plurality of ROMs for storage, but a RAM is used instead of the ROMs, and a ROM storing all the converted output data in advance is separately provided. The conversion output data stored in the ROM prior to the data conversion is provided in each RAM.
Alternatively, the conversion output data may be read out by transferring the data to the RAM and accessing the RAM.

In the above embodiment, the input image data of the three primary colors R, G, B are converted into the image data of Y, M, C, K, but the input digital data is Y, M,
C may be one that corrects and outputs each of the input Y, M, and C data, and the three-dimensional input digital data and the converted output data are not limited to the present embodiment. Absent.

[0077]

As described above, according to the present invention, 3
A conversion device for three-dimensional input digital data, wherein the conversion output data is thinned out and stored, and desired conversion output data is obtained by using interpolation calculation. Since the data can be read out in parallel, and the interpolation calculation can be performed with one read cycle of the converted output data, the processing time in the conversion device can be significantly shortened.

Further, the converted output data can be divided and stored in a plurality of storage means according to a predetermined rule, and there is an advantage that the memory contents are not duplicated and unnecessary memory capacity is not required.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a circuit block diagram showing a system configuration of a first embodiment of the present invention.

FIG. 3 is a diagram showing a unit cube that divides a three-dimensional space in the first embodiment.

FIG. 4 is a diagram showing an interpolation calculation mode in the first embodiment.

FIG. 5 is a diagram showing ROM division characteristics in the first embodiment.

FIG. 6 is a diagram for explaining the concept of ROM division in the first embodiment.

FIG. 7 is a diagram showing an interpolation calculation formula in the first embodiment.

FIG. 8 is a diagram showing a state of a specific interpolation calculation in the first embodiment.

FIG. 9 is a diagram showing characteristics of control signals in the first embodiment.

FIG. 10 is a circuit block diagram showing a system configuration of a second embodiment of the present invention.

FIG. 11 is a diagram showing characteristics of input data points in the second embodiment.

FIG. 12 is a diagram showing characteristics of converted output data in the second embodiment.

FIG. 13 is a diagram showing the concept of ROM division in the second embodiment.

FIG. 14 is a diagram showing characteristics of the incrementer in the second embodiment.

FIG. 15 is a diagram showing characteristics of an addition selection circuit in the second embodiment.

FIG. 16 is a diagram showing characteristics of a selection circuit in the second embodiment.

FIG. 17 is a diagram showing characteristics of the adder circuit according to the second embodiment.

FIG. 18 is a diagram showing characteristics of a ROM in the second embodiment.

FIG. 19 is a diagram showing the characteristics of the ROM in the second embodiment.

FIG. 20 is a diagram showing characteristics of a ROM according to the second embodiment.

FIG. 21 is a diagram showing characteristics of a ROM in the second embodiment.

FIG. 22 is a diagram showing characteristics when ROM division is generalized in the first embodiment.

FIG. 23 is a block diagram showing a configuration of a conversion device corresponding to a case where a division characteristic of a unit cube in the first embodiment is generalized.

[Explanation of symbols]

 1-12 Incrementer 20 Selector 21-27 Adder 28 Division processing circuit 32-34 Incrementer 36,37 Addition selection circuit 38-41 Selection circuit 43-46,56,57 OR circuit 52,53,55 Addition circuit

Claims (5)

[Claims] 1. A three-dimensional data converter for converting three-dimensional input digital data according to a predetermined conversion rule and outputting the converted data, wherein a three-dimensional space formed by the three-dimensional input digital data is based on a unit polyhedron. A means for storing the converted output data corresponding to each vertex of the plurality of unit polyhedrons divided into a plurality of units, wherein the converted output data are stored in a plurality of independent storage means so that at least the stored contents are different from each other. One or more of the conversion output data storage means, and conversion output data corresponding to a predetermined vertex of a unit polyhedron including points in the three-dimensional space corresponding to the three-dimensional input digital data. Of the converted output data read out in parallel from the storage means of the above, and the converted output data read in parallel by the converted output data read-out means By interpolation of brute, three-dimensional input digital data into seeking converting output data corresponding to output interpolation calculation means and the comprise constructed three-dimensional data conversion apparatus. 2. The converted output data storage means is composed of the same number of storage means as the number of vertices of the unit polyhedron, and the converted output data corresponding to each vertex of the unit polyhedron is divided and stored in different storage means. The three-dimensional data conversion apparatus according to claim 1, wherein the three-dimensional data conversion apparatus is configured as described above. 3. The converted output data storage means divides each vertex of the unit polyhedron into a plurality of groups including at least one group of a plurality of vertices, and the storage means has a number corresponding to the number of divisions. The three-dimensional data conversion apparatus according to claim 1, wherein the converted output data corresponding to each vertex of the unit polyhedron is divided and stored according to the division. 4. The unit polyhedron is a cube, and each vertex of the unit cube is represented by a three-dimensional coordinate value in which one side length of the unit cube is 1, and an even number of three-dimensional coordinate values corresponding to each vertex.
8 converted output data according to 8 odd combinations
The three-dimensional data conversion apparatus according to claim 1, wherein the conversion output data storage unit divides and stores the conversion output data in each of the eight storage units according to the division. 5. The unit polyhedron is a cube, and each vertex of the unit cube is represented by a three-dimensional coordinate value with one side length of the unit cube being 1, and the sum of the three-dimensional coordinate values corresponding to each vertex is expressed. Four
The converted output data is divided into four groups according to the remainder when divided by, and the converted output data storage means divides and stores the converted output data in four storage means in accordance with the division. Item 3. The three-dimensional data conversion device according to item 1.