JPH07230539A - Data converter, image forming device and table data storing method - Google Patents

Abstract

PURPOSE:To execute data conversion relating to plural kinds of characteristics by effectively utilizing a memory in each of plural look-up tables(LUTs) in a data converter for executing data conversion by interpolating operation using plural LUTs. CONSTITUTION:Since address converters 311 to 316 and data converters 341 to 347 are connected before and after respective LUTs 321 to 324 having the same capacity, addresses accessed by the LUTs 321 to 324 are always included within a fixed area in accordance with the value of a switching control signal EX. Thereby grading point data of other kinds can be stored in other areas not to be accessed by each of the LUTs 321 to 324 and data conversion of other kinds can be executed by switching the value of the control signal EX.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion device for converting a plurality of (multidimensional) signals into another signal by arithmetic processing using a look-up table (hereinafter referred to as LUT), and more particularly, for example, R (Red), G (green), B (blue), and other multi-order image signals are Y (yellow), M (magenta), C
The present invention relates to a data conversion device for converting each of (cyan) and BK (black) into one color signal.

[0002]

2. Description of the Related Art Non-linear conversion (gamma conversion or log conversion) of a digitized image signal is often performed using an LUT. This is because if the above-mentioned nonlinear conversion is to be obtained by an arithmetic circuit, the arithmetic circuit becomes very complicated and the circuit scale becomes large. On the other hand, for example, one video signal consisting of 8 bits is used. When the LUT is used to perform an arbitrary nonlinear conversion on
This can be realized if there is a 256-byte capacity memory used as the LUT. By the way, since the above-described conversion is for converting one image signal into another image signal having another property, the LUT used therein is a one-dimensional L
Called UT.

On the other hand, with the recent remarkable progress of the desktop publishing (hereinafter abbreviated as DTP) environment, there are increasing opportunities to handle color images. In this case, devices for inputting color images are scanners and video cameras. Etc., and the output device is various color printers such as an inkjet system, a dye thermal sublimation system, or an electrophotographic system.

Each of these color input / output devices has its own color space, and when the color image data obtained from a certain scanner is directly transferred to another color printer to output an image sample, It is unlikely that the color of the image sample will match the color of the original image. In order to match the colors of the two, the color space of the so-called input device (such as a scanner or video camera) is set to the output device (the various color printers described above).
It is necessary to perform processing such as conversion to the color space of (hereinafter, this processing is referred to as color conversion processing).

The color conversion processing performed here is performed with three colors (generally R (red) and B) obtained by an input device.
Image signals of (blue) and G (green) are converted into image signals of three colors or four colors on the output device side, and the LUT used for this conversion is called a three-dimensional LUT. .

However, if the process of converting the three-color image signal of the input device into one color of the plurality of colors of the output device is performed using only the three-dimensional LUT, the one-color image signal is Input 24 if it consists of 8 bits
LUT corresponding to 8 bits and output 8 bits is required,
In this case, the memory capacity is 16 M (mega) bytes). Furthermore, since the above memory is required for the number of colors of the output device, the actual memory capacity is 48 to
It has a large capacity of 64 Mbytes.

In such a case, since it is not practical in terms of cost, when the LUT is used in the color conversion process, it is general to use the interpolation calculation process together to reduce the memory capacity of the LUT to be used. is there.

There are various methods for this interpolation calculation processing, depending on how many pieces of data (hereinafter also referred to as grid point data) read from the LUT are used and what kind of relation grid point data is used. Generally, the more grid point data is used, the more the interpolation accuracy is improved, but the scale of the interpolation circuit tends to be large.

Among them, a four-point interpolation method as disclosed in, for example, Japanese Patent Publication No. 58-16180 is known as an interpolation method capable of reducing the circuit scale without significantly lowering the interpolation accuracy. Has been.

This interpolation method divides the cube into three planes when the eight lattice points specified by the upper bit signals of the three color signals are the eight vertices of the cube as shown in FIG. 1 of 6 tetrahedrons (see Fig. 2) obtained by
Interpolation is performed by using one.

By the way, since the interpolation formula in the interpolation calculation is defined for each of the above-mentioned six tetrahedrons, six interpolation formulas are prepared for one pre-conversion data. In such a case, the four grid point data used for the interpolation calculation are different for each interpolation formula, and the multiplication coefficient for each grid point data is also different. Therefore, a circuit for selecting the grid point data and calculating the multiplication coefficient is used. Becomes relatively complicated.

On the other hand, the inventor of the present application unifies the above six interpolation formulas into one interpolation formula in the previous application, reads out the grid point data used for the interpolation operation, and multiplies the read grid point data. We propose a simplified calculation of coefficients. Here, the unification of the proposed interpolation formulas is
This is performed based on the magnitude relation between the three-dimensional inputs.

[0013]

As described above, the four-point interpolation method is effective as a method capable of reducing the scale of the interpolation circuit without significantly deteriorating the interpolation accuracy, but further development of such an advantage is desired. Even in the case of adopting a configuration in which different interpolation operations are uniformly operated depending on the magnitude relationship (order relationship) of the three-dimensional inputs as described above, four requests with the same content are required for the request to improve the conversion speed. Using the LUT is a direct and effective means.

However, it can be said that the use of four LUTs in the four-point interpolation method as described above is a general configuration. In such a configuration, when four LUTs having the same contents are simultaneously accessed, The addresses accessed are different from each other. That is, the grid point data output simultaneously in the four LUTs are different from each other.

From this point of view, the main object of the present invention is to make the contents of each LUT different and to efficiently use four LUTs.

The following configuration is known as a conventional example of a configuration in which the contents of a plurality of LUTs are different from each other.

That is, each of the plurality of LUTs does not have the same interpolation function value (lattice point data), but
Each of the divided parts is stored. That is, the interpolation function value that should originally be stored in one LUT is divided and stored in a plurality of sub-LUTs that are obtained by dividing the one LUT.
S to be accessed according to the value of the lower bit signal of the input signal
The ub-LUT is changed. As a result, the original LUT has the same memory capacity as the LUT with the same contents.
It is possible to perform the same data conversion as in the case of using a plurality of.

However, only one type of data conversion is possible depending on one unit of the configuration disclosed in the above publication. Therefore, for example, when the data conversion for obtaining the output data of Y, M, C, Bk based on the input data of R, G, B is attempted by the above configuration, the above configuration of 4 units is required. This is because the contents of the LUT must be different if the output data is different.

By the way, in most cases, in output devices such as printers and copying machines, it is not necessary to simultaneously obtain the Y, M, C, and Bk data. Ie Y,
This is because the data conversion for obtaining M, C, Bk, etc. may be sequentially performed at predetermined time intervals. The present invention intends to efficiently use the LUT from such a viewpoint.

As another conventional example in which the contents of a plurality of LUTs used are different, the one described in Japanese Patent Laid-Open No. 5-63967 is known.

The configuration described in this publication is also related to one type of data conversion as described above, and the interpolation method using the tetrahedron disclosed here has a maximum of 2 in order to shorten the read time. This is performed using the LUT output (grid point data). From the above viewpoint, the present invention suppresses deterioration of interpolation accuracy by always performing four-point interpolation using four points.

The present invention has been made from the various viewpoints described above, and an object of the present invention is to provide a data conversion device capable of effectively utilizing a plurality of LUTs.

Another object of the present invention is to provide an effective data storage method for storing different data in a plurality of LUTs.

Still another object of the present invention is to provide a data conversion device capable of favorably performing data conversion according to the operation of the image output device.

Still another object of the present invention is to provide an image forming apparatus capable of effectively utilizing a plurality of LUTs in data conversion.

[0026]

Therefore, according to the present invention,
A data conversion device that performs data conversion using a plurality of look-up tables, and generating means for generating address data corresponding to each of the plurality of look-up tables based on input data to be converted, The address data generated by the generation means, and the exchange means for defining a lookup table corresponding to each of the plurality of address data generated by the generation means based on the number of the plurality of lookup tables. Characterize.

More preferably, in a data conversion device for performing data conversion by interpolation calculation using a plurality of look-up tables, each of the plurality of look-up tables is supported based on a part of input data to be converted. Address generating means for generating the address data to be generated, the address data generated by the address generating means, the value of the conversion switching control signal, and the remainder divided by the number of types of data conversion switched by the switching control signal. Address exchange means for defining a look-up table corresponding to each of the plurality of address data generated by the address generation means, and data output from each of the plurality of look-up tables based on each address defined by the address exchange means. And between the interpolation calculation coefficient Performs address exchange and symmetrical exchange in the address exchanging means, characterized in that comprises a, and interpolation operation means for performing an interpolation operation based on a combination of the data and the interpolation calculation coefficient.

Further, the address exchanging means determines the address data corresponding to the look-up table according to the operation of the image forming apparatus.

Furthermore, in the data storage method for storing data in a plurality of look-up tables, address data in the plurality of look-up tables of data to be stored is generated, and the generated addresses and the stored addresses are stored. A lookup table to which the generated address data corresponds based on the number of types of data, and stores the corresponding table data in the determined lookup table. To do.

[0030]

According to the above structure, the address accessed in each look-up table is always limited to the address of a fixed area according to the sum of the address data or the sum of the address data and the value of the switching control signal. This allows
It is possible to store different types of conversion data stored in different areas in each of the plurality of look-up tables, and to access only the table area having one conversion characteristic by the address.

On the other hand, by changing the contents of the switching signal, it is possible to change the above-mentioned area in each look-up table, and thereby it is possible to access the table area having other kinds of conversion characteristics. As a result, it is possible to perform multiple types of conversion.

[0032]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Before describing each embodiment of the present invention, the configuration of four-point interpolation used in this embodiment and the configuration for performing the interpolation operation in this case will be described. These are the same as those disclosed in Japanese Patent Publication No. 58-16180 and the above-mentioned prior application by the present inventor.

First, the 4-point interpolation method will be described.

The three color signals (n + m bits for each color) before conversion are Xi = Xh2 ^m + Xf, Yi = Yh2 ^m + Y
If f, Zi = Zh · 2 ^m + Zf, then Xh,
Yh and Zh are upper n of the respective signals Xi, Yi and Zi
Represents a bit signal, and Xf, Yf, Zf represent lower m bit signals of the respective signals Xi, Yi, Zi.

In the LUT, Xh = 0, 1, 2, ..., 2 ⁿ
-1, Yh = 0, 1, 2, ..., ^2n- 1, Zh = 0,
All combinations of 1, 2, ..., 2 ⁿ -1 (2 ³ⁿ ways)
On the other hand, converted color data (lattice point data) is stored, and these lattice point data are read out by a 3n-bit address signal in which Xh, Yh, and Zh are connected.

Color signal data before conversion (Xi, Yi, Z
i) the lower m bits of each, i.e. Xf, Yf, Zf
However, when all are "0", the lattice point data read out by the LUT by the address signal becomes the color data after conversion as it is. If not, interpolation processing is performed according to the values of Xf, Yf, and Zf.

As shown in FIG. 1, eight lattice points specified by the upper n-bit signals Xh, Yh, and Zh are arranged in a cube of 8 points.
When there are two vertices, the three color signals Xi, Y before conversion
i and Zi are represented as (absolute coordinates of) a point in this cube. Dividing this cube into three planes (Xf = Yf plane, Yf = Zf plane, Zf = Xf plane) forms six tetrahedra, each tetrahedron having four lattice points. .

The four-point interpolation method described here is one in which an interpolation calculation is performed using four grid point data of such a tetrahedron. That is, the color signal before conversion belongs to any of these six tetrahedra (if it belongs to a boundary surface, it should be assigned to either one of the two tetrahedra sharing this boundary surface). Which tetrahedron belongs to is determined by the magnitude relation of Xf, Yf, and Zf. For example, Xf
When>Yf> Zf, the color signal before conversion is located in the tetrahedron shown in FIG. 2, and the coordinates of the grid point data used for the interpolation processing are (Xh, Yh, Zh), (Xh + 1, Yh, Zh),
(Xh + 1, Yh + 1, Zh), (Xh + 1, Yh +
1, Zh + 1).

If the grid point data at each grid point coordinate is represented as D (X coordinate, Y coordinate, Z coordinate) and the interpolated data H1 (Xi, Yi, Zi), the interpolation calculation is as follows. It is done like an expression.

[0041]

[Equation 1] H1 (Xi, Yi, Zi) = 2 ^-m・ {(2 ^m -Xf) ・ D (Xh, Yh, Zh) + (Xf-Yf) ・ D (Xh + 1, Yh, Zh) + (Yf-Zf) ・ D (Xh + 1, Yh + 1, Zh) + Zf ・ D (Xh + 1, Yh + 1, Zh + 1)} (1) Next, regarding the unification of interpolation formulas explain.

The above equation (1) is defined for each of the six tetrahedrons as described above, and the interpolation equations that unify the equations are shown below.

[0043]

[Equation 2] H2 (Xi, Yi, Zi) = 2 ^-m・ {(2 ^m -MAX) ・ D (Xh, Yh, Zh) + (MAX-MED) ・ D (Xh + X_MAX, Yh + Y_MAX, Zh + Z_MAX) + (MED-MIN) ・ D (Xh + X_MAX + X_MED, Yh + Y_MAX + X_MED, Zh + Z_MAX + X_MED) + MIN ・ D (Xh + 1, Yh + 1, Zh + 1)}… (2) In the above formula, MAX, MED, and MIN are each X
The maximum value, the median value, and the minimum value of f, Yf, and Zf, and X_
MAX, Y_MAX, Z_MAX, X_MED, Y_M
ED and Z_MED are 1-bit signals indicating that Xf, Yf, and Zf are maximum values or median values, respectively.

For example, when Xf>Yf> Zf, the above signals have the following values.

[0045]

[Equation 3] MAX = Xf, MED = Yf, MIN = Zf, X_MAX = 1, Y_MAX = 0, Z? MAX = 0, X_MED = 0, Y_MED = 1, Z_MED = 0 Substituting it gives the same equation (1).

As described above, by using the unified interpolation formula as shown by the formula (2), the structure for the interpolation calculation is simplified. However, this interpolation calculation is performed by one LUT.
When processing is performed using only the LUT, it is necessary to access the LUT at least four times to output one conversion data, and the conversion speed decreases.

In order to solve this, as described above, the inventor of the present application has a configuration in which four LUTs are prepared in the previous application, and four lattice point data necessary for interpolation calculation are simultaneously read out to perform the interpolation calculation process. Indicated.

FIG. 3 and FIG. 4 show an example of the configuration of a data conversion device that uses four LUTs to perform the interpolation calculation shown in equation (2) at high speed. In the configuration examples shown in these figures, n = 4
It shows the case where m = 4.

In FIG. 3, 101, 102, and 103 are terminals for inputting upper 4-bit signals Xh, Yh, Zh of input data Xi, Yi, Zi, 111, 112, respectively.
113 is an adder that adds "1" to Xh, Yh, and Zh, 121 to 126 are 2-bit 1-output selectors each having a 4-bit width, 131 to 133 are 2-input OR circuits, and 141 to 144 are 4k. Byte (12-bit address, 8-bit output) conversion table memory (LU
T), 151 to 154 are multipliers, 161 is a terminal for inputting the value "2 ⁴ ", 162, 163 and 164 are the maximum, median and minimum values of the lower 4 bits Xf, Yf, Zf of the input data, respectively. , 171 to 173 are subtractors, 181 is an adder for summing the four multiplication results output from the multipliers 151 to 154, and 182 is equivalent to multiplication of the coefficient 2 ^{−m in} the equation (2). 183 is a terminal for outputting the output signal of the data converter.

FIG. 4 shows the sequence of Xf, Yf, Zf shown in FIG. 3, MAX, MED, MIN, X_MAX, Y_MA.
A circuit configuration for generating signals such as X, Z_MAX, ..., Z_MIN is shown.

In the figure, reference numerals 201, 202 and 203 denote terminals for inputting lower 4 bit signals Xf, Yf, Zf of input data Xi, Yi, Zi, 211, 212, respectively.
Reference numeral 213 denotes three comparators 221 to 221, which compare the magnitude relationships among the lower 4-bit signals Xf, Yf, and Zf with each other.
Reference numeral 6 is a logical element such as AND that generates a signal indicating the order relation of Xf, Yf, Zf from the outputs of the three comparators 211, 212, 213. Reference numerals 231 to 239 are the lower bit signals Xf, Yf, Zf. , OR, which is a median value, or a minimum value (a total of 9 bits), and OR logic elements 241 to 249 are the 9-bit signals corresponding to the corresponding data (Xf). , Yf or Zf), and AND logic elements 251 to 253 OR the signals gated by the AND elements 241 to 249 to obtain the maximum value (M
AX), median value (MED) and minimum value (MIN), OR logic elements 161, 162, 163 are terminals for outputting the maximum value, median value and minimum value, respectively. The maximum value, the median value, and the minimum value are input to the terminals with the same reference numerals shown in FIG.

Next, the operation of FIG. 4 is as follows.

Three 8-bit input data (X
i, Yi, Zi) upper 4-bit data (Xh, Y)
h, Zh) is input to the terminals 101, 102 and 103 shown in FIG. 3, and the lower 4-bit data (Xf, Yf, Zf) is input to the terminals 201, 202 and 203 shown in FIG.
The three lower 4-bit data (Xf, Yf, Zf) are compared with each other by the comparators 211 to 213, and Xf>
Data regarding whether or not the relationships of Yf, Yf> Zf, and Zf> Xf are established are provided by the comparators 211 to 211.
It is output from 213. The output signal is "1" when the relationship is established, and is "0" otherwise. By referring to two or more outputs of these comparators 211 to 213, the order relation of the three lower-order bit data is determined.

For example, if the relationship of Xf> Yf is established and the relationship of Yf> Zf is established, Xf>Yf> Zf.
Order relation is established. In this case, the outputs of the comparators 211 and 212 are both "1", so the above relationship is detected by the output of the AND element 221 being "1".

Similarly, when the output of the AND element 222 is "1", there is an order relation of Yf>Zf> Xf, and the AND element 2
When the output of 23 is "1", there is an order relation of Zf>Xf> Yf. There are 6 kinds of order relation of 3 data,
The remaining three ways are AND elements 224, 22 of negative logic input.
5, 226 (hereinafter, the term “negative logic input” may be omitted). For example, AN
The D element 224 detects a state in which the outputs of the comparators 211 and 212 are both "0". That is, when the output of the comparator 211 is “0”,

[0056]

[Outer 1]

When the output of the comparator 212 is "0",

[0058]

[Outside 2]

When the output of the AND element 224 is "0", the order relation of Zf≥Yf≥Xf is established.

Similarly, an AND element for detecting the "0" output of the comparators 212 and 213, and the comparator 21.
It may be possible to detect all six order relationships by providing AND elements that detect the "0" outputs of 1 and 213, but there is a slight problem. It is 3 when Xf = Yf = Zf
The outputs of the two comparators 211 to 213 are all "0".
Therefore, in the above-mentioned detection configuration, the negative logic input AN
This is because all three signals output from the D element are "1".

In this case, MAX, MED, and MIN have the same value, but the interpolation operation is performed without contradiction in the entire data converter. However, X_MAX, Y_MAX, Z
Since the six signals _MAX, X_MED, Y_MED, and Z_MED all become "1", there is a difference between the meaning and the value of the signal. Therefore, in the example shown in FIG. 4, the above problem does not occur.

Specifically, the comparators 212 and 213
The AND element 225 for detecting the "0" output of is also simultaneously detected for the "0" output of the AND element 224. A
The ND element 226 also performs similar detection. By this, X
When f = Yf = Zf, the output of only the AND element 224 becomes "1" and the outputs of the other AND elements become "0". This makes it possible to AND the arbitrary values of Xf, Yf, and Zf.
Since only one of the elements 221 to 226 outputs "1" and the other five AND elements output "0", X
The order relation of f, Yf, and Zf is classified into 6 types.

Based on the six signals indicating the order relationship of Xf, Yf, Zf obtained as described above, X_MAX, Y_MA
X, Z_MAX, X_MED, Y_MED, Z_ME
Nine signals D, X_MIN, Y_MIN, and Z_MIN are generated.

Here, X_MIN, Y_MIN, Z_M
IN is a signal indicating whether or not the corresponding data Xf, Yf, Zf is the minimum value, and is used to generate the minimum value MIN.

Next, the method of generating X_MAX, X_MED, X_MIN based on the order relationship (size relationship) of Xf, Yf, Zf is as follows. Note that the method of generating other signals regarding Y and Z is the same, so description thereof will be omitted.

Six kinds of order relations of Xf, Yf, Zf (a) Xf>Yf> Zf (b) Yf>Zf> Xf (c) Zf>Xf> Yf (d) Zf ≧ Yf ≧ Xf (e) Xf ≧ Zf ≧ Yf (Xf ≠ Yf) (f) Yf ≧
Two or more of Xf ≧ Zf (Yf ≠ Zf) do not hold at the same time, and only one of them holds. Which of the conditions holds is known by referring to the outputs of the AND elements 221 to 226. X_MAX
Is a signal indicating that Xf is the maximum value, and is one of (a) or (e) in the above six order relationships.
When the order relation of is established, the signal becomes "1". Therefore, the output signals of the AND elements 221 to 225 are set to O
What is synthesized by the R element 231 becomes X_MAX. Similarly, the signal X_MED is a signal indicating that Xf is a median value, and when the order relation of (c) or (f) is established among the above relations, the signal becomes "1".
Therefore, X_MED is a combination of the output signals of the AND elements 223 and 226 by the OR element.

Further, the signal X_MIN is a signal indicating that Xf is the minimum value, and is (b) or (d).
When the order relation of is established, the signal becomes "1", so that the combined output signal of the AND elements 222 and 224 by the OR element becomes X_MIN.

X_MAX (Y_ is generated as described above.
(MAX, Z_MAX) signal is the selector 12 in FIG.
1 to 123 and OR elements 131 to 133, and used to generate the MAX signal of FIG.

That is, X_MAX, Y_MAX, Z_
The corresponding lower 4-bit data Xf, Yf, Zf are gated by the MAX signal, and the gate operation is performed in the 2-input AND elements 241, 242, 243, and performed for each 4-bit signal.

The outputs of the AND elements 241, 242, 243 are combined by the 3-input OR element 251 having a 4-bit width to obtain the maximum value MAX, and the signal is output to the terminal 162.

Similarly, X_MED, Y_MED, Z_M
The ED signal is sent to the OR elements 131 to 133 shown in FIG. 3 and used for generating the MED signal shown in FIG.
The method of generating the MED signal and the method of generating the MIN signal are the same as the above-described MAX signal generating method.

The operation of the configuration shown in FIG. 3 will be described based on the signals generated by the configuration shown in FIG.

In the figure, the upper 4-bit signals Xh, Yh, and Zh of the three input data (each 8 bits) input to the terminals 101 to 103 are added by "1", and the adders 111 to 113 and the selector 121 are added. To 126 L side terminals. In addition, the 4-bit high-order bit signals Xh, Yh, and Zh are connected to 12 bits and are given as an address signal to the LUT 141 that stores the grid point data.

From this LUT 141, the value D (Xh, Yh, Zh) in the above-mentioned equation (2) is read. On the other hand, the signals output from the adders 111 to 113 are Xh + 1, Yh + 1, and Zh + 1, respectively, and these signals are sent to the H-side terminals of the selectors 121 to 126, and these signals are also linked to 12 bits to LU.
It is given to T144 as an address signal.

From the LUT 144, the value D (Xh + 1, Yh + 1, Zh + 1) in the expression (2) is read. The selectors 121 to 123 are respectively shown in FIG.
X_MAX, Y_MAX, Z_MA generated by the circuit of
It is controlled by X, and when these signals are "1", H
On the other hand, when it is "0", the terminal on the L side is selected. H
When the side is selected, the upper 4 bit signals Xh, Yh, Zh
A value obtained by adding "1" to any of the above is output from the selector, and when the L side is selected, the upper 4-bit signal is output from the selector as it is. Therefore, X_MAX
Is 1 when Y_MAX is "1", Yh + 1 is output when Y_MAX is "1", and Zh + 1 is output when Z_MAX is "1". The 4-bit signals output from these selectors are concatenated into 12 bits and applied to the LUT 142 as address signals. Therefore, from the LUT 142,
D (Xh + X_MAX, Yh + Y_M in the equation (2)
The value of (AX, Zh + Z_MAX) is read.

Similarly, the selectors 124 to 126 generate the above X_MAX, Y_MAX, Z_M generated by the circuit of FIG.
Controlled by a logical sum signal between the corresponding signals of the AX signal and the X_MED, Y_MED, and Z_MED signals, each 4-bit signal output from these selectors is concatenated into 12 bits and given to the LUT 143 as an address signal. Therefore, from this LUT 143, D (Xh + X_MAX + X_MED, Yh + Y_MAX in the equation (2) is calculated.
The value + Y_MED, Zh + Z_MAX + Z_MED) is read.

The four grid point data (8 bits each) read from the LUTs 141 to 144 are given to the multipliers 151 to 154 as multiplicands, respectively.

On the other hand, the terminal 161 has a value of 2 ⁴ and the terminals 162 to 164 have the MA generated by the circuit shown in FIG.
X, MED, and MIN are input, and these signals are sent to the multipliers 171 to 173. In the subtractor 171, 2 ⁴ -M
AX, subtractor 172 uses MAX-MED, subtractor 173
Then, MED-MIN is respectively calculated, and the subtraction results are given to the multipliers 151 to 153 as multipliers. Further, the MIN signal input from the terminal 164 is directly given to the multiplier 154 as a multiplier. In the above four multipliers, the four terms in the above equation (2) are multiplied, and the multiplication result is sent to the adder 181.

Then, the adder 181 adds all the four input values and outputs the result to the next bit shifter 1
Send to 82. The bit shifter 182 performs an operation corresponding to the first coefficient 2 ^−m (here, m = 4) in the equation (2), the output of the bit shifter 182 is sent to the output terminal 183, and H2 in the above equation (2) is used. (Xi, Yi, Z
i) will be output from the terminal 183.

<First Embodiment> FIG. 5 is a block diagram showing the main parts of a data conversion apparatus according to the first embodiment of the present invention.

FIG. 5 shows an address switch and a data switch which are means for rearranging addresses and data newly added to the data converter shown in FIGS. 3 and 4 and control of these switches. It shows a circuit and the like.

That is, in FIG. 5, the address generator and the interpolation calculator are omitted. In the figure, 301 to 30
Reference numeral 4 indicates an address signal input to each of the LUTs 141 to 144 in FIG. 311-3
Reference numeral 16 denotes an address exchanger having a function of mutually exchanging the supply paths of two address signals with each other, and makes the LUT to be accessed different according to the input data as will be described later. 321 to 324 are LUTs,
These have the same memory capacity as the LUTs 141 to 144 in FIG. 3, but the contents of the stored table data are different. That is, the LUTs 141 to 144 in FIG. 3 have exactly the same data stored in all four of them, and four LUTs redundantly hold grid point data having the same content. On the contrary,
The LUT in FIG. 5 basically holds the grid point data having the same content in a divided state.

Next, reference numerals 341 to 347 are data exchangers having a function of mutually exchanging lattice point data read from the LUT. These data exchangers 341 to 347
The grid point data 351 to 354 output from the above are respectively sent to the multipliers 151 to 154 in FIG. 3 and interpolation calculation processing is performed.

Such a data exchanger is provided because when the address signals are rearranged by the above-mentioned address exchangers 311 to 316, the grid point data read from the LUTs 321 to 324 are rearranged in the same manner. This is because in the interpolation calculation process, the correspondence between the respective grid point data and the weighting coefficient to be multiplied is different. The address exchangers 311 to 316 and the data exchangers 341 to 346 are LUTs 321 to 321 in terms of their functions.
The address exchanges 31 are arranged symmetrically with 24 in between.
Data exchange is performed in each of the data exchangers 341 to 346 corresponding to the exchange of addresses in each of 1 to 316.

Reference numeral 361 is a terminal for inputting a 2-bit control signal: EX for switching the conversion table (type of data conversion), and reference numerals 362 and 363 are 2-bit 2-input adders. These adders are high-order bit signals Xh, Yh, Z
The remainder when the sum of h and the switching control signal EX is divided by 4 (hereinafter referred to as (Xh, Yh, Zh + EX)% 4) is calculated. The calculation result is output to the signal line 365. In calculating (Xh + Yh + Zh + EX)% 4, the necessary signals are the lower 2 bits of each of the upper bit signals Xh, Yh, Zh and the control signal EX. First, the adder 362 outputs the lower 2 bits of the signal Xh and the signal Yh. The lower 2 bits of are added. The carry output of the addition result is ignored, and the lower 2 bits of the output of the adder 362 and the lower 2 bits of the signal Zh are added by the adder 363. Further, ignoring the carry output of this addition result, the lower 2 bits which are the output of the adder 363 and the control signal EX (2 bits) are added by the adder 364, and the lower 2 bits ignoring the carry output of this addition result (Xh + Yh + Zh + EX)% 4.

The 2-bit signal thus obtained is 2
Input AND elements 371 to 373, 2-input OR element 37
4, and input to the inverters 375 and 376, respectively, and control signals for the address exchanger and the data exchanger are generated.

The operation of the address exchanges 311 to 316 and the data exchanges 341 to 346 will be described below.
Each exchange has two signal inputs and two signal outputs (each input and output has a plurality of bit widths), and a 1-bit control signal input, and depending on the value of this control signal, FIG. It has two operation modes shown in. That is, when the control signal is “0”, as shown in FIG. 6A, the signal input from the upper stage is output to the upper stage, and the signal input from the lower stage is output to the lower stage (through mode). . On the other hand, when the control signal is “1”, the signal input from the upper stage is output to the lower stage and the signal input from the lower stage is output to the upper stage, as shown in FIG. Done (exchange mode).

FIGS. 7A to 7D show (Xh + Yh + Z).
h + EX)% 4 depending on the value,
316 is an explanatory diagram showing how address signals are rearranged in each 316. FIG.

Address signals 301 to 304 shown in FIG.
Is an X address (Xh or Xh + 1), a Y address (Yh or Yh + 1), a Z address (Zh or Zh
+1) is a signal obtained by concatenating the three, and when the value obtained by simply adding these three addresses, Xh + Yh + Zh, is set to S, the values of the address signals 301 to 304 are clear from the configuration shown in FIG. Respectively S, S + 1, S +
2, S + 3.

Here, when the switching control signal EX = 0, the value of S% 4 changes according to the lower 2 bit signals of the upper bit signals Xh, Yh, Zh, as is apparent from the configuration shown in FIG. In FIG. 7 (a), S% 4 = 0, and FIG. 7 (b).
Shows S% 4 = 1, FIG. 7C shows S% 4 = 2, and FIG. 7D shows address exchange corresponding to S% 4 = 3.

When Adr is the sum of the X, Y and Z addresses input to each LUT by the following address exchange, L
Adr input to the UT 321 (see FIG. 5, the same applies below)
Is an address switch, S in the case of FIG. 7A, S + 3 and S + in FIGS. 7B to 7D, respectively.
2, S + 1.

When S% 4 = 1 (FIG. 7B), LUT3
Since Adr of the address input to 21 is S + 3, at this time, Adr% 4 = (S + 3)% 4 = 0, and similarly Sr
When% 4 = 2 (FIG. 7C), the address of the address input to the LUT 321 is S + 2.
+2)% = 0 (the description is omitted when S% 4 = 0, 3), and eventually the address Ad input to the LUT 321 is
As long as EX = 0, r is Adr% 4 = 0.

Next, the address Adr input to the LUT 322 is S + 1 in the case shown in FIG.
In (b) to FIG. 7 (d), S, S + 3, and S + 2, respectively. Therefore, when S% 4 = 1 (FIG. 7B), the LUT
Since Adr of the address input to 322 is S,
At this time, Adr% 4 = S% 4 = 1, and similarly, the address Adr input when S% 4 = 2 is S + 3.
dr% 4 = (S + 3)% 4 = 1, and eventually LUT3
The address Adr input to 22 is Adr% = 1 as long as EX = 0.

Similarly, the address Adr input to the LUT 323 is Adr% 4 = 2 as long as EX = 0.
The address Adr input to the LUT 324 is Adr% 4 = 3 as long as EX = 0.

Thus, when the control signal EX is 0,
In the LUTs 321 to 324, Adr% 4 is 0,
Only addresses 1, 2, and 3 are given, and other addresses are not input.

Therefore, as will be described later with reference to FIG. 31 and subsequent figures, conversion table data relating to the first type is stored in each of the LUTs 321 to 324 at an address accessed only when EX = 0, and EX = It is possible to store the conversion table data related to the second to fourth types at other addresses corresponding to each of 1-3.

FIG. 8 shows the value of Adr% 4 of the address at which each LUT is accessed for EX = 0, 1, 2, 3. As can be seen from FIG. 8, with respect to different EX values, the values of Adr% 4 of the addresses accessed by the LUTs are all different, and four independent conversion table data can be stored without duplication.

The operation of the address exchangers 311 to 316 has been described above, but the operation of the data exchangers 341 to 347 is as described above.
1 to 316 and the data exchangers 341 to 347 are the LUT 32.
Since they are arranged symmetrically with respect to 1 to 324, the operation is also completely symmetrical. Therefore, the grid point data of the four independent conversion tables stored in the LUTs 321 to 324 by the data exchangers 341 to 347 are read according to the value of EX, and the data in the order before the address signals are exchanged are returned and interpolated. It can be sent to the calculation unit, and thereby the interpolation calculation can be favorably performed. As a result, according to the present embodiment, it is possible to switch four types of data conversion processing according to the value of EX.

<Second Embodiment> FIG. 9 is a block diagram showing the configuration according to the second embodiment of the present invention.

In the above-described first embodiment, six 2-input / 2-output address exchangers and six data exchangers were used, but this embodiment relates to a configuration in which these exchangers are reduced to five, respectively. It is a thing.

In FIG. 9, reference numerals 401 to 405 are address exchangers, 411 to 415 are data exchangers, 421 is an exclusive-OR (hereinafter abbreviated as EXOR) element, 4
22 and 423 are 2-input AND elements, and 424 is an inverter. Other elements or signals are similar to those denoted by the same reference numerals in FIG. Also,
In this example (FIG. 9), (Xh + Yh + Zh + EX)%
Although the description of the circuit for calculating 4 is omitted, this circuit is shown in FIG.
It is similar to the calculation circuit in.

FIGS. 10A to 10D show (Xh + Yh +).
It is explanatory drawing showing the address exchange operation of each address exchanger corresponding to the value of Zh + EX)% 4.

As is clear from the comparison between FIG. 7 and FIG.
The address signal rearranging function according to the present embodiment is the same as the first embodiment.
This is equivalent to the address signal rearranging function in the above embodiment. Therefore, this embodiment has the same data conversion function as the first embodiment.

<Third Embodiment> FIG. 11 shows the third embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration according to an example of FIG.

This embodiment uses five address exchangers and five data exchangers, respectively, and is similar to the second embodiment, but a decoding circuit (FIG. 9 and the logic elements 421 to 424 shown in FIG.
The logic elements 371 to 376) in FIG. That is, the 2-bit signal obtained when (Xh + Yh + Zh + EX)% 4 is calculated is used as it is as the control signal of the exchange, the upper bit signal is input to the address exchanges 441 and 442, and the lower bit signal is exchanged. It is input to the devices 443 to 445.

In FIG. 11, 441 to 445 are address exchangers, 451 to 455 are data exchangers, and other elements and signals are the same as those in the second embodiment (FIG. 9).

FIGS. 12A to 12D show (Xh + Yh +).
It is explanatory drawing showing the address exchange operation of each address exchanger corresponding to the value of Zh + EX)% 4.

As is apparent from the figure, the address signal rearranging function according to the present embodiment is equivalent to the address signal rearranging function according to the above-mentioned first and second embodiments. Therefore, this embodiment also has a data conversion function as in the first and second embodiments.

<Fourth Embodiment> FIG. 13 shows a fourth embodiment of the present invention.
3 is a block diagram showing a configuration relating to the embodiment of FIG.

In the third embodiment (FIG. 11), the address exchanges 443 to 445 and the data exchange 453 are performed.
.About.455 are connected in series to the former-stage exchangers, and in such a case, the signal delay time generated in these exchangers is relatively long. In this embodiment, in order to reduce the delay time, the same function as that of the exchange is realized by using selectors of two inputs and one output (a plurality of bit widths) in parallel. Further, in the present embodiment, as for the circuit for calculating (Xh + Yh + Zh + EX)% 4, the speed of addition is changed by changing the order of addition as compared with the first to third embodiments.

In FIG. 13, 461 to 468 are the above-mentioned selectors, and 471 is the lower 2 bits of the upper bit signal Zh.
An adder 473 for adding the bit and the control signal EX (2 bits) adds the output signals of the lower 2 bits excluding the carry from the adder 362 and the adder 471, and outputs the control signal 365. It is an adder. Other elements and signals are similar to those denoted by the same reference numerals in FIGS. 5 and 11.

Selectors 461 to 468 send control signal 365.
When the lower bit of is "0", the L side is selected, and when it is "1", the H side is selected. The address signal rearrangement function by the selectors 461 to 464 is exactly the same as the function by the address exchangers 443 to 445 in the third embodiment (FIG. 11), and similarly the data rearrangement function by the selectors 465 to 468 is the same as that shown in FIG. 11 data exchanges 453-455
It is exactly the same as the function by.

Further, in the circuit for calculating (Xh + Yh + Zh + EX)% 4, three adders are connected subordinately in the circuit shown in FIG. 5, but in the present embodiment, the adder subordinately connected is Since it is reduced to two steps, the above calculation can be performed at high speed.

As described above, the present embodiment has exactly the same data conversion function as the first to third embodiments described above, but has the minimum delay time in address rearrangement and data rearrangement. It is possible to realize the following configuration.

In all of the four embodiments described above, the arrangement of the address exchanges and selectors and the arrangement of the data exchanges and selectors are symmetrical with respect to the LUT. Since the address exchange function and the data exchange function are the same, they can be replaced. That is, the arrangement of the address exchangers and the like in the Nth (N = 1, 2, 3, 4) embodiment and the arrangement of the data exchangers and the like other than the Nth embodiment are combined to form a data converter. It becomes possible.

<Fifth Embodiment> FIG. 14 shows the fifth embodiment of the present invention.
3 is a block diagram showing a configuration relating to the embodiment of FIG.

In the first to fourth embodiments described so far, the four LUTs are utilized as effectively as possible and the four types of conversion table data are stored. Therefore, the hardware scale for generating the address rearranging means, the data rearranging means, and the control signals for these rearranging means has been relatively large.

In this embodiment, by storing only two types of conversion table data in four LUTs and enabling two types of data conversion, addresses and data rearranging means and control signals of these means are stored. This is to reduce the scale of hardware to be generated and simplify it.

In FIG. 14, 501 to 504 are L having the same memory capacity as the LUT in the first to fourth embodiments.
Although it is a UT, only two types of conversion table data are stored. 511 is a terminal for inputting a control signal EX1 (1 bit) for switching between these two types of conversion tables, 5
12 is the LSB of the high-order bit signal Xh and the LS of the same signal Yh
EXOR element for calculating exclusive OR with B, 51
3 is an EXOR element for calculating the exclusive OR between the LSB of the signal Zh and the control signal EX1, and 514 is an EXO for calculating the exclusive OR between the outputs of the two EXOR elements.
It is an R element.

Selector 461 for rearranging address signals
~ 464 and selectors 465 for rearranging data
468 has the same function as in the fourth embodiment, and other elements and signals are the same as those shown in the figures referred to in the previous embodiments.

In the first to fourth embodiments, in order to switch four conversion tables, (Xh + Yh + Zh + EX)
% 4 was calculated, but since only two conversion tables are switched in this embodiment, (Xh + Yh + Zh + E)
X)% 2 should be known. This value is the L of each data
This can be easily calculated by simply calculating the exclusive OR with SB. The result of this calculation is the EXOR element 5 as the signal 515.
14 and inputs to selectors 461-468. FIG. 15 shows the relationship between the value of the control signal EX1 and the value of Adr% 2 (Adr = Xh + Yh + Zh) of the address input to each LUT.

With the above arrangement, in this embodiment,
Two independent conversion tables can be stored in the LUTs 501 to 504, and two types of data conversion can be switched by the control signal EX1 (1 bit).

<Sixth Embodiment> FIG. 16 shows a sixth embodiment of the present invention.
3 is a block diagram showing a configuration relating to the embodiment of FIG.

FIG. 15 referred to in the fifth embodiment.
LUT501, LUT503, LUT50
It is clear that 2 and LUT 504 hold the same data, respectively. Therefore, it is not necessary to rearrange addresses and data in the entire four LUTs, and the rearrangements (exchanges) can be performed separately for each two.

Reference numerals 521 to 522 are address exchangers for performing such address exchanges, and reference numerals 523 to 524 are data exchangers for similarly performing data conversion. Since the method of generating the control signal 515 of these exchangers is the same as that of the fifth embodiment, the description of the same generator is omitted. Other address generators and interpolation calculators (not shown) are the same as before.
It is similar to that shown in FIG.

As is apparent from the above, this embodiment is capable of performing two types of data conversion with the same function as that of the fifth embodiment.

<Seventh Embodiment> FIG. 17 shows a seventh embodiment of the present invention.
3 is a block diagram showing a configuration relating to the embodiment of FIG.

In this embodiment, the least significant bit is removed from the 12-bit address input to each LUT to form an 11-bit address, and the memory capacity of each LUT is halved accordingly.

The meaning of removing the least significant bit from the 12-bit address will be described below. The above fifth
In the sixth embodiment, only two conversion table data are stored while holding the LUT capable of storing four conversion table data, which means that the LUT is not used 100% effectively.

That is, if only two types of data conversion are required, in order to utilize the LUT 100% effectively,
It is necessary to reduce the memory capacity of T by half. A new configuration for realizing this is shown in FIG.

In the figure, the element different from each of the above embodiments is only the EXOR element 551, and the other elements are basically based on the fourth embodiment shown in FIG. However,
The configuration of the circuit for calculating (Xh + Yh + Zh)% 4 is the same as that of the first embodiment shown in FIG.

The operation of the circuit shown in FIG. 17 differs from the first to fourth embodiments in that the control signal for table switching is only 1 bit. This control signal is subjected to exclusive OR operation with the upper 1 bit of the value (2 bits) of (Xh + Yh + Zh)% 4, and is sent to the exchanges 441, 442, 451 and 452 as a switching control signal. The values "0" and "1" of the control signal EX1 correspond to the values "0" and "2" of the 2-bit control signal EX in FIG.

Therefore, the value of Adr% 4 of the address input to each LUT has a relationship with the value of EX as shown in FIG. Therefore, in the configuration shown in FIG.
Only addresses with Adr% 2 = 0 are stored in the LUT 321 and LUT 323, and Adr% 2 is stored in the LUT 322 and LUT 324.
It can be seen that only the address of = 1 is input.

For example, the X address (Xh or Xh +
1), when the Y address (Yh or Yh + 1) and the Z address (Zh or Zh + 1) are linked, assuming that the Z address is linked to the lowermost side, one of the two addresses where the Z address is continuous is Adr%. When 2 = 0, the other becomes Adr% 2 = 1 (when the Z address returns from the maximum value to 0, the X address and the Y address change, so the above relationship may be broken).

More specifically, since the Z address has 4 bits, 16 of these Z addresses are continuous, and Adr%
The address of 2 = 0 and the address of Adr% 2 = 1 are arranged alternately. Adr% 2 = in this sequence
Which of 0 and Adr% 2 = 1 comes first depends on the values of the X address and the Y address. In this case, the LUT
321 and LUT 323 have every other Adr% 2 lined up
Since only the address of = 0 is input to the LUT 322 and the LUT 324, only the address of Adr% 2 = 1 which is arranged every other line is input. Therefore, there is redundancy in this address signal, and the address of each LUT has the highest redundancy. The lower bits can be predicted from the upper 11-bit address.

As a result, the address input of each LUT is 1
It can be understood that the least significant bit can be removed from 2 bits to reduce to 11 bits. This means that the memory capacity of each LUT can be reduced by half.

Next, for the 11-bit address signal, a new problem arises as to how the conversion table data should be stored in each LUT. By predicting the least significant bit removed from the address signal, virtually defining a 12-bit address, and storing the grid point data corresponding to this 12-bit address signal at the location accessed by the 11-bit address. Can be resolved.

<Eighth Embodiment> FIG. 19 shows an eighth embodiment of the present invention.
3 is a block diagram showing a configuration relating to the embodiment of FIG.

In the seventh embodiment, the 12-bit address signal is reduced to 11 bits, and the number of types of conversion tables stored in the LUT is reduced to two, which is half, but in this embodiment, the address is further increased. The number of signals is reduced to 10 bits, and the number of conversion tables stored in the LUT is set to one.

Therefore, there is no control signal for switching the conversion table, and the four address signals are rearranged based on the value of (Xh + Yh + Zh)% 4 and input to the four LUTs.

In FIG. 19, reference numerals 561 to 564 are LUTs having an address signal of 10 bits, and other elements have the same functions as those denoted by the same reference numerals in FIG.

In the present embodiment, the value of Adr% 4 of the address signal given to each LUT is constant, and LUT5
It becomes 0,1,2,3 with respect to 61-564, respectively.

Therefore, the upper 10 bits to the lower 2 bits of the 12-bit address formed by concatenating the X address, the Y address, and the Z address can be predicted for each LUT. Only by inputting 10 bits of the address signal, the grid point data required for the interpolation calculation can be read. The problem of what kind of grid point data is stored in each address of the LUT can be solved by applying the idea shown in the description of the seventh embodiment.

In the present embodiment and the seventh embodiment described above, the arrangements of the exchanges and selectors for rearranging addresses and data should be the same as those shown in the first to fourth embodiments. Of course, you can also do it.

<Ninth Embodiment> The first to the first embodiments described so far.
All the eighth embodiments have been described on the assumption that the lattice point data is already stored in each LUT.

If the conversion table is fixed and there is no change, this LUT may be constructed by a ROM. However, as will be described later with reference to FIG. Possible memory (RA
M) must be used. In this case, it is necessary to load the initial data or changed data into the LUT, and this embodiment relates to a method of loading the initial data or changed data into the LUT.

FIG. 2 shows the configuration relating to the ninth embodiment of the present invention.
It shows in 0.

In this embodiment, the conversion table data is loaded into the data converter of the eighth embodiment from an externally connected CPU or the like.

In the figure, reference numeral 581 denotes an address generation unit for generating four addresses to be given to four LUTs, which is equivalent to the contents shown in the section of the prior art. However, the address signal is not 12 bits but 10 bits excluding the lower 2 bits.

Reference numeral 591 is a block for rearranging addresses, and the address exchanger 44 in the eighth embodiment.
1, 442 and selectors 461 to 464. 6
01 to 604 are RAMs used as LUTs,
In addition to address input and data input terminals, a chip select terminal (CS), a write pulse input terminal (WR), an output control terminal (QC), etc. are provided for write control. In these RAMs 601 to 604, the CS terminal input is "1".
At this time, if a pulse is input to the WR terminal, data is written to the address being input at that time, while CS
When the terminal input is "0", no data is written even if a pulse is input to the WR terminal. Reference numeral 610 is a terminal for inputting an address signal from an external CPU or DMA (direct memory access) controller, etc., 611 is a terminal for inputting data to be written in the memory of the address, 612.
Is a terminal for inputting a data write pulse to the WR terminal of the RAM, and 614 is for switching between a mode for loading table data in the present data conversion device and an original mode for converting input data into other data by interpolation calculation processing. , 621 to 623 are selectors controlled by the control signals. This control signal is output to the output control terminals (O
It is also sent to C), and this signal is set to "1" in the data conversion mode to enable data reading from the RAMs 601 to 604. The other elements are the same as those already described in the above embodiments.

When loading the conversion table data, the control signal input from the terminal 614 is set to "0", and the selector 6
21 to 623 are all switched to the "L" side terminals. As a result, the 12-bit address signal input from the external CPU or the like through the terminal 610 is transferred to the three selectors 6.
It is input to the address generation block via 21 to 623 (each having a 4-bit width). In the address generation block, the addresses are concatenated and the upper 10 bits of them are output to the signal line 582. The address on this signal line is
"1" is added to the lowest order, and other signal lines 583 to 58
"0" is added to the lowest of the address signals on 5 and 1
1 bit.

The address signals on the signal lines 583 and 584 are the address generation control signals (X_MAX, Y_MAX).
Etc.), but it is ignored when the conversion table data is loaded. Although the address signal on the signal line 585 is tentatively determined, this is also ignored.

The above four 11-bit address signals are input to the address rearrangement block 591 and added by the adder 363.
The rearrangement is performed based on the output signal (2 bits) of. The 12-bit address signal input from the terminal 610 is divided into 4 bits each from the beginning, and the divided signals are Xa and Y.
If a and Za, the output value of the adder 363 is (Xa + Y
The value is a + Za% 4. When the output value is "0", the address on the signal line 582 is sent to the RAM 601 and the lowest "1" is input to the CS terminal of the RAM 601. At this time, C of the other three RAMs 602-604
"0" is input to the S terminal. In this state, write data is input from the terminal 611 and the terminal 61
When a write pulse is input from 2, this data is written only in the RAM 601.

Similarly, when (Xa + Ya + Za)% 4 is "1", (Xa + Ya + Za)% is stored in the RAM 602.
When 4 is “2”, the RAM 603 stores (Xa + Ya + Z
a) When% 4 is "3", data is written only in the RAM 604.

With the above operation, the conversion table data can be stored in all areas of the four RAMs.

<Tenth Embodiment> FIG. 21 is a block diagram showing the structure according to the tenth embodiment of the present invention.

The present embodiment realizes the same function as that of the ninth embodiment with a different configuration. Specifically, the chip select signals given to the four RAMs are added by the adder 363.
Is generated by decoding the 2-bit signal output from the.

In FIG. 21, 631 is the above-mentioned decoder, and the input 2-bit signals are "00", "01",
"10" and "11", while S1, respectively
The output of only S2, S3 and S4 becomes "1". These S
Outputs 1, S2, S3 and S4 are RAMs 601 to 6 respectively
Sent to 04. As a result, the chip select signals input to the RAMs 601 to 604 become exactly the same as in the ninth embodiment, and this embodiment has the same function as that of the ninth embodiment.

<Eleventh Embodiment> FIG. 22 is a block diagram showing the structure according to the eleventh embodiment of the present invention.

The present embodiment shows a configuration for loading the conversion table data when there are four types of conversion tables as in the above-described first to fourth embodiments.
In FIG. 22, 611 to 614 are four RAMs for loading table data, and the memory capacity of each RAM is four times that of the ninth and tenth embodiments.
Further, although the address input is increased from 10 bits to 12 bits, the other control signal inputs are the same.

In this embodiment, since the conversion table data to be loaded is four times as large as that in the ninth and tenth embodiments, the address signal input to the terminal 610 is 14 bits. Since the upper 2 bits of this 14-bit signal function as a conversion table switching signal when loading table data, a selector 624 for switching to the conversion table switching control signal EX during interpolation processing is provided. on the other hand,
Of the 14-bit signal, the lower 12 bits are divided into 4 bits as in the above embodiment, and selectors 621 to 6 are provided.
Sent to 23. The other elements, signals, and the like are the same as those in the above-described embodiments, and thus the description thereof will be omitted.

Across the four RAMs 611-614,
4 types of conversion table data are loaded, but CPU
From the side, it is merely an operation of sequentially loading the four conversion tables on one linear address space. In response to such a load operation from the CPU side, on the data conversion device side, the address rearrangement block 591 and the decoder 6
By the operation of 31 or the like, predetermined table data is stored in a predetermined address of each RAM. The timing of writing these data is the same as in the ninth embodiment.

<Twelfth Embodiment> In this embodiment, a processing method equivalent to the address signal rearrangement shown in each of the above embodiments will be described.

The address signals can be rearranged not only by directly rearranging the address signals but also by controlling the method of generating the address signals. In the present embodiment, the address signals are rearranged equivalently by rearranging the selector control signals when the selector control signals are selected to generate the address signals. Before showing the configuration of the present embodiment, X_MMD = X_MAX + X_MED, Y_
MMD = Y_MAX + Y_MED, Z_MMD = Z_M
AX + Z_MED, and using these signals, FIG.
23 shows a method of generating an address having a configuration different from that shown in FIG.
, And the contents will be described.

In the figure, reference numerals 701 to 706 are added selectors, and each selector is an original selector 1.
The same operation as 21 to 126 is performed. That is, when the control signal is "0", the address signal on the L side is selected and "1" is selected.
At this time, the H-side address signal is selected.

In the configuration shown in FIG. 3, the address signals supplied to the LUT 141 are Xh, Yh, Zh (4 bits each).
Although it was a signal in which Xh, Xh,
Yh and Zh are assigned to selectors 701, 702 and 703, respectively.
After selection in step 3, they are connected, and as a result, the same address signal as in FIG. 3 is input to the LUT 141. The same applies to the address signal input to the LUT 144. Below, the selectors 121 to 126 and 701 to 706 are treated as one functional block called the address selection unit 700.

FIG. 24 is a block diagram showing the structure relating to the twelfth embodiment of the present invention. In this embodiment, the address selecting section 700 is used.

In the figure, reference numeral 710 denotes four sets of 3-bit selector control signals (Xh + Yh + Zh + EX).
The control signal rearrangement unit rearranges based on the value of% 4, and performs exactly the same rearrangement operation as the address signal rearrangement means of the above-described embodiments. Therefore, as the internal configuration, any of the configurations shown in the first to fourth embodiments can be used. Other elements and the like are the same as those in each of the above-described embodiments.

As shown in the first to eighth embodiments, the addresses are rearranged, and the grid point data read from the LUT are arranged in the reverse order of the addresses so that the interpolation calculation process can be favorably performed. It is necessary to change. In the present embodiment, this is overridden, but the description of the interpolation calculation process after the LUT is omitted. Since the direct rearrangement of the address signals and the rearrangement of the control signals for selecting the addresses in the same manner and the rearrangement of the addresses as a result are completely equivalent, the present embodiment is described in the first to fourth embodiments. It has the same function as that of the embodiment.

<Thirteenth Embodiment> FIG. 25 shows the first embodiment of the present invention.
It is a block diagram which shows the structure regarding the Example of FIG.

In this embodiment, an address is generated by using 12 adders of a 4-bit signal and a 1-bit signal without using the address selection block in the twelfth embodiment. In the figure, 711 to 722 are the adders. In the twelfth embodiment, when the control signal is "0", each selector in the address selection block has X
Select h (or Yh, Zh), and when "1", Xh
+1 (or Yh + 1, Zh + 1) was selected. This is equivalent to adding the selector control signal to Xh and outputting it. Therefore, according to the present embodiment,
It is understood that the same function as that of the embodiment can be realized.

<Fourteenth Embodiment> FIG. 26 is a block diagram showing the structure according to the fourteenth embodiment of the present invention.

In the figure, the element different from the thirteenth embodiment and the like is the multiplication coefficient rearranging section 741. This block is output from the adder 472 (Xh + Yh + Zh
Based on the value of + EX)% 4, the output signals of the subtracters 171 to 173 and the MIN signal input from the terminal 164 are rearranged and sent to the multipliers 151 to 154. The sorting method (order) is the address sorting block 59.
This is the same as the rearrangement of addresses in 1.

The lattice point data read out from the LUT after the addresses are rearranged needs to be rearranged in the reverse order of the addresses so that the interpolation calculation processing can be performed well. Even if the multiplication coefficients are rearranged without being changed, the same calculation result can be obtained.

This is because when there is a multiplication coefficient corresponding to each grid point data, by rearranging either the grid point data or the multiplication coefficient and taking the above correspondence, the target arithmetic processing can be performed. Because it will be. Therefore, the same data conversion function as the above-mentioned first to fourth, twelfth, and thirteenth can be realized also by this embodiment.

<Fifteenth Embodiment> FIG. 27 is a block diagram showing the structure according to the fifteenth embodiment of the present invention.

The embodiment described so far is based on the above (2).
Although four-point interpolation calculation was performed on the three-dimensional space based on the formula, the present embodiment applies the present invention to three-point interpolation in the two-dimensional space.

The interpolation formula is shown below.

[0179]

[Equation 4] H3 (Xi, Yi) = 2 ^-m {(2 ^m -MAX) ・ D (Xh, Yh) + (MAX-MIN) ・ D (Xh + X_MAX, Yh + Y_MAX) + MIN ・ D ( (Xh + 1, Yh + 1)} (3) In the above formula, Xi and Yi are two-dimensional input data (Xi = Xh · 2 ^m + Xf, Yi = Yh · 2 ^m + Y) before conversion.
f), MAX and MIN are the larger and smaller values of Xf and Yf, respectively, X_MAX is "1" when Xf≥Yf, and Y_MAX is "1" when Yf≥Xf, and "1" otherwise. A signal that becomes 0 ″, D (Xh, Yh), is the grid point data at the grid point addresses Xh, Yh.

This embodiment shows a case where the input data is 8 bits and m = 4. In FIG. 27, reference numerals 801 to 803 denote 8-bit address LUTs storing three types of conversion table data in the respective divided areas, 811 to 813 each are an address exchanger for exchanging two addresses with each other, and 821 to 821. 824
Is a data exchanger for exchanging two pieces of grid point data with each other, and 831 is a remainder calculator for calculating (Xh + Yh + EX3)% 3.

The value output from the remainder calculator 831 is in the range of 00 ₂ to 10 ₂ , and in the output of 2 bits, the upper bit is the signal 832 and the lower bit is the signal 833.
Is output as. The signal 832 is the address exchange 811.
The signal 833 is used as a control signal for the data exchange 821 and the address exchange 813 and the data exchange 823. The OR output of both signals obtained by the 2-input OR element 834 is sent to the address exchange 812 and the data exchange 822 as a control signal.

In addition, 835 is a subtracter for calculating MAX-MIN, and 836 is three multipliers 151, 152, 1
An adder for adding the multiplication results output from 54, 837
Is a shifter that performs a process corresponding to the 2- ^m coefficient in the equation (3), and 838 is a terminal that outputs the interpolation calculation result shown in the equation (3).

In the LUTs 801, 802, 803, the value of (Xh + Yh + Zh + EX3)% 3 is 0,
Lattice point data is stored corresponding to addresses 1 and 2. When EX3 = 0, the first type conversion table of each LUT is accessed, and the interpolation processing operation is performed based on the grid point data read from this conversion table. When EX3 = 1, the second type conversion table of each LUT is accessed, and when EX3 = 2, the third type conversion table is accessed.

The remainder calculator 831 has two 4-bit inputs and one 2-bit input. The weight of each bit in the 4-bit signal is 2 ³ , 2 ² , 2 ¹ , 2 from the higher order.
⁰ and the remainder divided by 3 for each weight is 2 ¹ ,
It becomes 2 ⁰ , 2 ¹ , 2 ⁰ .

[0185] Thus, the input signals of all 10-bit 2 ^2P weight bits and 2 ^{2P + 1} of the weights of the bits (where P = 0,
1, 2, ...) and add to each
The addition result of the bits having the weight of ^{2P + 1} is given a weight of 2 ¹ , and then added to the other addition result (the sum of the bits having the weight of 2 ^2P ). If bit signals having a weight of 2 ² or more are generated in each addition process or the whole addition process,
Replace that bit with a signal with a weight of 2 ⁰ or 2 ¹ ,
Continue the addition.

By the above processing, 2 bits (0
.About.3), but when 3 (11 ₂ ) is detected at the end and replaced with 00 ₂ , the remainder is divided by 3.

Although three address exchangers and three data exchangers are used in this embodiment, it is also possible to use a 3-input 1-output (plural bit width) type selector instead of these exchangers. is there. It is also possible to apply the above-mentioned twelfth to fourteenth embodiments to this embodiment.

Further, it is possible to reduce the address signal of each LUT to 7 bits and reduce the type of the conversion table stored in each LUT to one type. At this time,
There is no control signal for switching the conversion table, and addresses and data are rearranged based on the value of (Xh + Yh)% 3.

Since the value of (Xh + Yh)% 3 of the address signal input to each LUT is fixed, the 8-bit address signal has redundancy and can be reduced by 1 bit. The reduced 1-bit signal can be predicted from the (Xh + Yh)% 3 value and the 7-bit address signal that are determined for each LUT. By this prediction, an 8-bit address is virtually determined from the 7-bit address, and the grid point data that should be read by the 8-bit address is stored in the address accessed by the 7-bit address. As a result, one type of conversion table can be read well with a 7-bit address.

<Sixteenth Embodiment> FIG. 28 is a block diagram showing the structure according to the sixteenth embodiment of the present invention.

In this embodiment, the present invention is applied to 5-point interpolation on a 4-dimensional space.

The interpolation formula is shown below.

[0193]

[Expression 5] H4 (Xi, Yi, Zi, Qi) = 2 ^-m {(2 ^m -MM1) ・ D (Xh, YH, Zh, Qh) + (MM1-MM2) ・ D (Xh + X_M1, Yh + Y_M1, Zh + Z_M1, Qh + Q_M1) + (MM2-MM3) ・ D (Xh + X_M2, Yh + Y_M2, Zh + Z_M2, Qh + Q_M2) + (MM3-MM4) ・ D (Xh + X_M3, Yh + Y_M3, Zh + Z_M3, Qh + Q_M3) + MM4D (Xh + 1, Yh + 1, Zh + 1, Qh + 1)} (4) In the above equation, Xi, Yi, Zi, and Qi are data It is the four-dimensional input data before conversion, each Xi = Xh.2
^m + Xf, Yi = Yh · 2 ^m + Yf, Zi = Zh · 2 ^m
It is expressed as + Zf, Qi = Qh · 2 ^m + Qf. MM
1, MM2, MM3, MM4 are lower bit signals Xf,
A signal obtained by rearranging Yf, Zf, and Qf in descending order is shown.
D (Xh, Yh, Zh, Qh) is the grid point address Xh,
The grid point data in Yh, Zh, and Qh are shown. Also,
X_M1, X_M2, and X_M3 are respectively Xf ≧ MM
It is a 1-bit signal which is "1" when the relationship of 1, Xf≥MM2 and Xf≥MM3 is established, and is "0" otherwise. Y_M1 to Y_M3, Z_M1 to Z_3, Q
_M1 to Q_M3 are similar signals.

In this embodiment, the input data is 8 bits each, m
= 4 (bits). FIG. 28
, 841 to 845 are LUTs of 16-bit addresses storing five types of conversion table data, 104
Is the top 4 of the input data Qi increased when expanded to 4 dimensions
A terminal for inputting the bit signal Qh, 114 is a +1 circuit for adding "1" to the 4-bit signal, and 851 to 856 are
A selector for generating an address signal to be input to the LUT, 861 to 875 are selectors for rearranging the address signals, 877 is a terminal for inputting a control signal EX5 for switching five kinds of conversion tables, and 879 is the selector 861. To 875 switching control signals 881 to 88
To produce 3, (Xh + Yh + Zh + Qh + EX
5) A remainder calculator that calculates% 5. The value output from the remainder calculator 879 is in the range of 000 _{2 to} 100 ₂ and is a 3-bit signal. Among them, the most significant bit (weight: 2 ² ) is sent to the selectors 861 to 865, the signal 822 having a weight of 2 ¹ is to the selectors 866 to 870, and the least significant bit (weight: 2 ⁰ ) is to the selectors 871 to 875, respectively. Sent. Further, this 3-bit signal is a block 88 for rearranging the lattice point data read from the LUT.
5, and the rearrangement is performed in the opposite order to the rearrangement of the address signals. The structure of this data exchange block is symmetrical to the selector groups 861 to 875 which rearrange the address signals. 886 to 889 are MM1 and M, respectively.
This is a terminal for inputting M2, MM3, and MM4. A sorting circuit can be used as a means for rearranging the lower bit signals Xf, Yf, Zf, Qf in descending order and generating MM1, MM2, MM3, MM4.

Further, 155 and 174 represent three dimensions in four.
Multipliers and subtractors newly required as the dimension is expanded, 891 is an adder for adding the multiplication results output from the five multipliers, 892 is a shifter, and 893 is converted by interpolation calculation processing. This is a terminal for outputting data.

FIG. 29 shows the value of Adrs% 5 of the address input to each LUT for each value of EX5, where Xh + Yh + Zh + Qh is Adrs. As is clear from this, the five types of conversion table data are five L
It can be properly stored in and read from the UT.

Also in this embodiment, the above-mentioned twelfth to first
The fourth embodiment can be applied, and the address signal of each LUT can be reduced by 2 bits to 14 bits, and only one type of conversion table can be stored and read. The principle is the same as that described in the fifteenth embodiment.

<17th Embodiment> FIG. 30 is a block diagram showing the structure according to the 17th embodiment of the present invention.

The present embodiment relates to data conversion by three-dimensional four-point interpolation based on the above-mentioned equation (2). In this embodiment, four grid point data required for four-point interpolation are read out from two LUTs twice. That is, it takes two cycles of processing time to obtain one data conversion output.

In FIG. 30, 901 and 902 are LUTs storing two types of conversion table data, 911 is an address exchanger for exchanging two address signals, and 912 is L.
A data exchanger for exchanging two grid point data read from the UT, 915 and 916 are data delay registers,
921 is a terminal for inputting a CYC signal for identifying two cycles (when CYC = 0, the first cycle, CYC =
1 is a second cycle), 922 is a selector for selecting MAX in the first cycle, MIN in the second cycle, 923 is a selector for selecting 2 ⁴ in the first cycle, and 2 is a second cycle.
Selector for selecting MED in each cycle, 9
24 and 925 are registers for delaying the output of the selector by one cycle, 931 is an adder, 932 is an accumulator, 933 is a shifter, 934 is a terminal for outputting the converted conversion data, and 941 to 943 are 2-input AND elements,
Reference numerals 944 to 946 are 2-input OR elements. Other elements and the like have the same functions as the elements with the same reference numerals shown in FIGS. 3 and 14.

The LUT 901 stores the grid point data of Adr% 2 = 0 of the first type conversion table and the grid point data of Adr% 2 = 1 of the second type conversion table. In the table, grid point data of Adr% 2 = 1 of the first type conversion table and grid point data of Adr% 2 = 0 of the second type conversion table are stored.

Therefore, when the table switching control signal EX1 input from the terminal 511 is "0", the first conversion table is accessed, so that the address of Adr% 2 = 0 is stored in the LUT 901 and Adr% 2 = 1. Address is L
Each is provided to the UT 902. This control is performed according to the exclusive OR operation result (output of the EXOR element 514) between the LSB of each of the higher-order bit signals Xh, Yh, Zh and EX1.

That is, (Xh + Yh + Zh)% 2 = 0
At this time, the output of the EXOR 514 also becomes "0", and the address exchange 911 becomes through. CYC in the first cycle
Since = 0, the outputs of the 2-input AND elements 941 to 943 are all “0”, and the outputs of the 2-input OR elements 944 to 946 are X_MAX, Y_MAX, and Z_MAX, respectively. Two
The outputs of the input AND elements 941 to 943 are control signals of the selectors 121 to 123, respectively, whereby each selector selects the L side to select the signals Xh, Yh, Zh, and then concatenates these signals to exchange addresses. It is sent to the container 911.

On the other hand, since the address exchange 911 is in the through state, the address connecting the signals Xh, Yh, Zh is sent to the LUT 901. A at this address
The value of dr% 2 is "0". On the other hand, 2-input OR element 9
The outputs of 44 to 946 are selectors 124 to 126, respectively.
When only X_MAX is “1” and the others are “0”, the selector 124 selects Xh + 1 and the selectors 125 and 126 respectively select Yh and Zh.
Select. The selected signals are concatenated and sent to the LUT 902 through the address exchange 911. The value of Adr% 2 of this address is "1".

In the second cycle, since the value of the CYC signal becomes "1", the outputs of the 2-input AND elements 941 to 943 become X_MMD, Y_MMD and Z_MMD, respectively, and the outputs of the 2-input OR elements 944 to 946 all become "1". It becomes 1 ”. X_MMD is X_MAX and X_MED
Is a signal obtained by performing a logical OR operation on Y_MMD and Z_MMD. If X_MAX is "1", X_MMD is also "1", and either Y_MMD or Z_MMD is "1". Here, Y_MMD is “1”, Z
_MMD is set to "0". Based on these signals, the selectors 121 to 123 select Xh + 1, Yh + 1, and Zh. The selected signals are combined and given to the LUT 901 through the address exchange 911 (the state of this address exchange is the same slew state as in the first cycle). The value of Adr% 2 of this address is "0".

The selector 12 is controlled by the control signal of "1" output from all the 2-input OR elements 944 to 946.
4 to 126, Xh + 1, Yh + 1, Zh +, respectively.
1 is selected. The selected signals are combined, passed through the address switch 911 and provided to the LUT 902. The value of Adr% 2 of this address is "1".

When (Xh + Yh + Zh)% 2 = 1,
The output of the EXOR 514 becomes "1", the addresses are exchanged by the address exchange 911, and similarly, the value of Adr% 2 of the address input to the LUT 901 is 0, and the LUT 90
The value of Adr% 2 of the address input to 2 becomes "1". Only when the table switching signal EX1 is switched from "0" to "1", the value of Adr% 2 of the address input to the LUT 901 becomes "1".

As described above, the four grid point data of the conversion table of the first type are read out from the two LUTs twice. When these grid point data pass through the data switch 912, data exchange is performed corresponding to the operation of the address switch 911. As a result, the correspondence with the multiplication coefficient can be obtained.

The data output from the data exchanger 912 is delayed by one cycle in the registers 915 and 916 and then sent to the multipliers 151 and 152.

The multiplier 15 is read in the first cycle.
The lattice point data input to 1 corresponds to a multiplication coefficient of 2 ⁴ -MAX. This multiplication coefficient is
2,923, MAX selected in the first cycle
And 2 ⁴ are delayed by 1 cycle by the registers 924 and 925, respectively, and then input to the subtractor 171 to be generated.

Next, the lattice point data read in the first cycle and input to the multiplier 152 has MAX-MED
Corresponds to the multiplication coefficient. As for this multiplication coefficient, MAX selected in the first cycle in the selector 922 is delayed by one cycle in the register 924 and input to the subtractor 172, and the MED selected in the second cycle in the selector 923 is input to the subtractor. 172 is input and generated.

Multiplication between the corresponding grid point data and the multiplication coefficient is performed in each of the multipliers 151 and 152, and the multiplication results are added up in the adder 931 and set in the accumulator 932.

Next, the grid point data read in the second cycle and input to the multiplier 151 includes MED-MIN.
Corresponds to the multiplication coefficient. This multiplication coefficient is 2 ⁴
It is generated in the same way as the multiplication coefficient of -MAX. However, the signal selected by the selectors 922 and 923 is MIN.
And switch to MED.

Similarly, the multiplication coefficient corresponding to the multiplier 152 is MIN. This multiplication coefficient delays the MIN signal selected in the second cycle in the selector 922 by one cycle in the register 924, and the value of 2 ⁴ output from the selector 923 in the first cycle of the next conversion process from this MIN signal. Lower 4 bits of 0000 ₂
Is generated in the subtractor 172 by subtraction.

Multiplications between the lattice point data read in the second cycle and the corresponding multiplication coefficients are performed at 151 and 152, and the multiplication results are added up by the adder 931 and sent to the accumulator 932. It is cumulatively added to the value held in the cycle. Then, the addition result is the shifter 92.
It is output as conversion data to the terminal 934 via the terminal 3.

In this embodiment, two types of conversion table data are stored in two LUTs.
As described in the description of the sixteenth embodiment, it is possible to reduce the address signal by 1 bit so that the conversion table has one kind. At that time, the conversion table switching control signal EX1 becomes unnecessary.

As described above in the first to seventeenth embodiments, according to the embodiment of the present invention, when the data conversion is performed by the interpolation calculation using n LUTs, the data of the maximum n types of characteristics are obtained. The conversion can be done. That is, each LU
By switching the address (area) exclusively accessed in T and storing the grid point data having different characteristics for each area, different kinds of data conversion can be performed every time the table area is switched.

In each of the following embodiments, as described in the ninth and subsequent embodiments, each LUT does not have all the grid point data in advance, but the grid point data is loaded into the LUT every data conversion. The switching control of the embodiment and the printing operation associated therewith will be described.

<Eighteenth Embodiment> This embodiment shows a case where the present invention is applied to an electrophotographic printing operation used in a printer, a copying machine or the like.

FIG. 31 is a flow chart showing a control procedure relating to this printing operation, FIG. 32 is a timing chart of various signals in this control, and FIG. 33 is a block diagram showing a configuration for this control.

The type of data conversion and the table area switching control in the print operation according to this example will be described below with reference to these figures.

The structure shown in this embodiment is a printer using a data (color) conversion device capable of converting eight types of data using four LUTs as shown in the above-mentioned several embodiments. This relates to the print operation of the copying machine. In the initial state, the following eight types of data are stored in advance in each of the four LUTs for each area to be accessed according to the switching control. That is, as shown in step S3101 of FIG. 31, when plain paper is used as the recording medium, R (red), G
Lattice point data for color conversion of (green) and B (blue) data to M (magenta), similarly, grid point data for color conversion to C (cyan) when plain paper is used, and , OHP paper, R, G, B
Lattice point data for color conversion of data into M and C, respectively, are stored in four divided areas of each LUT.

The control CPU 1101 (see FIG. 33) is
The engine control unit 1102 that controls the print output (see FIG.
3), the print operation control is started in step S3101 shown in FIG. 31, and it is determined in step S3102 what the recording medium used for printing is. This determination is performed by the sensor 11 for determining the type of recording medium.
06 (see FIG. 33). The user may detect the setting input of the recording medium instead of using the sensor to determine the type of the recording medium.

If it is determined that the paper is plain paper, the control procedure advances to step S3103 and subsequent steps. Step S3
After 103, formation of a latent image using a laser beam or an analog optical system (both not shown) on a photoconductor drum (not shown), development using toners of M, C, Y, and Bk and development of these. Images are output by transfer to plain paper, but in the case of electrophotography, toner M, C, Y, B
Images are sequentially output for each page of k (one sheet of plain paper) for each color k (hereinafter, also referred to as frame sequential output). That is, latent image formation, development, and toner transfer are sequentially repeated for each color. For this reason, data (color) conversion is also performed frame by frame for each color.

That is, when the control CPU 1101 determines that the paper is plain paper as described above, the switching control signal EX2 = is set in synchronization with the rise of the page head signal TOP (see FIG. 32) from the engine control unit 1102. 0, E
X1 = 0 is set (see FIG. 32), and the area for converting to M (magenta) when plain paper of each LUT is used in the subsequent data conversion is accessed. At the same time, the memory read control unit 1105 (see FIG.
3) sequentially supplies a memory address for one page to the buffer memory 1104 (see FIG. 33) in synchronization with the page head signal TOP, and reads each 8-bit R, G, B data.

Data converter 1000 (see FIG. 33)
Performs the color conversion based on the read R, G, B data, and outputs the conversion data M (see FIG. 32) for M (magenta), as described above in each of the embodiments.
The engine unit 1103 (see FIG. 33) performs a printing operation based on this conversion data M, and performs image output related to M (magenta) for one page (up to transfer of toner M to plain paper) (above, Steps S3103, S310
4).

Next, in step S3105, the ninth
With the configuration for data loading described in the embodiment and subsequent embodiments, during the data conversion pause, the grid point data relating to Y of plain paper is stored in the area accessed with EX1 = 0 (see FIG. 32). When the storage of this table data is completed, in step S3106, the switching control signals are set to EX1 = 1 in synchronization with the rising of the next page head signal TOP, as described above (EX2 = 0 remains unchanged, as shown in FIG. 32), and each LU accessed after that
The T area is switched. As a result, in the same manner as above, in the data converter 1000, the R, G, B signals are converted into conversion data C regarding C (cyan), and based on this, the above M (magenta) is transferred onto the plain paper. C
An image of (cyan) is formed.

Further, in step S3107, the grid point data relating to Bk of plain paper is stored in the table area accessed with EX = 1 during the data pause period (FIG. 32).
reference). Thereafter, in step S3108, the switching control signal is set to EX1 = 0 (EX2 = 0 remains unchanged,
32), the area accessed thereafter in each LUT is an area for storing Y (yellow) grid point data when plain paper is used. And R, G, B
Data conversion for accessing these areas is performed based on the signal, and Y (yellow) images are formed in an overlapping manner.

Next, in step S3109, the grid point data relating to M of plain paper is stored in the table area accessed with EX1 = 0 during the data conversion pause (see FIG. 32), and the control signal EX1 is set to "1" in step S3110. 1 "is set, data conversion is performed based on RGB data for one page, and a Bk (black) image is formed in an overlapping manner (see FIG. 32).

In the final step S3111, in preparation for the next image output, the grid point data for cyan (C) of plain paper is stored in the table area accessed with EX1 = 0, and this control procedure ends.

On the other hand, when it is determined in step S3102 that the recording medium is OHP paper, the switching control signal is EX2 = EX2 = in step S3112.
1 and subsequent steps S3113 to S3120
Then, the same control as that in steps S3104 to S3111 described above is performed.

As described above, the switching control signals EX1 and EX2 are set in synchronism with each page head signal TOP, and the image formation (printing) corresponding thereto is performed in the frame sequential manner.

<Nineteenth Embodiment> FIGS. 34 and 35.
Are flow charts and timing charts for almost the same configuration as the eighteenth embodiment, and the control configuration of these is the same as that shown in FIG.

The difference from the eighteenth embodiment is that two types of grid point data are stored by one data load. That is, as shown in FIG. 34, steps S3404, S
When M (magenta) and C (cyan) images are formed using plain paper in 3405, a grid related to Y of plain paper is displayed in the table area accessed with EX1 = 0 during the next data conversion pause in step S3406. Point data and EX1
The grid point data for Bk of plain paper is stored (loaded) in the table area accessed when = 1 (see FIG. 35). Then, based on the table data, Y (yellow)
And Bk (black) images are formed (steps S3407 and S3408), and similarly, step S340.
At 9, grid point data regarding M (magenta) and C (cyan) of plain paper is loaded.

<Twentieth Embodiment> FIGS. 36 and 37.
FIG. 19 is a flow chart, a timing chart, and a control configuration block diagram regarding the same configuration as in the eighteenth and nineteenth embodiments.

In this embodiment, plain papers M, C, Y, and Bk are loaded in the initial state (see step S3601 in FIG. 36), and sensor detection (step S360) is performed.
Only when OHP paper is detected in 2), M of OHP,
The grid point data regarding C, Y, and Bk are loaded at once (step S3603, see FIG. 37). When the image formation is completed, the grid point data for plain paper is always stored (step S360).
8).

<Twenty-first Embodiment> FIGS. 38 and 39.
FIG. 19 is a flow chart and a timing chart showing a configuration for loading table data similar to the eighteenth to twentieth embodiments.

In this embodiment, first the sensor detection (see FIG.
Step S3801) is performed, and in response to this detection,
Lattice point data for obtaining M (magenta), C (cyan), Y (yellow), and Bk (black) conversion data of OHP or plain paper are stored (step S3).
802 or S3803, see FIG. 39). Then, after that, frame-sequential image output is performed in the order of M, C, Y, and Bk (steps S3804 to S3807).

<Twenty-second Embodiment> FIGS. 40, 41 and 4
2 and 43 show the structure according to the 22nd embodiment of the present invention.

In this embodiment, as shown in FIG. 43, a conversion table corresponding to two types of images and two types of paper is used when "text" and "natural image" are mixed in one page image. Perform data conversion. Therefore, R read from the buffer memory 1104 (see FIG. 42),
A 2-bit attribute bit indicating the value of the switching control signal EX1 is added to each pixel of the G and B data, so that the R, G, and B data is one of the two types of images described above. Can be determined.

In FIG. 40, in the initial state shown in step S4001, the above-mentioned two types of "text" and "natural image" and OHP are respectively added to the four types of tables accessed according to the combination of the values of EX1 and EX2.
M (magenta) corresponding to the combination of paper and plain paper
The grid point data for obtaining the converted data of is stored. When the printing operation is started, step S4002
Detects whether the OHP paper is plain paper, then step S40
At 05, the LUT of the type corresponding to the value of the attribute bit EX1 added to the R, G, B data for each pixel is accessed to obtain the grid point data. Then, based on this, interpolation calculation is performed to obtain converted data, and further image output is sequentially performed to print one page.

In the next step S4003, the grid point data for obtaining the C (cyan) conversion data relating to the above-mentioned four kinds of combinations is stored while the data conversion is not performed during this period.

Thereafter, the same operation as described above is performed in step S40.
This processing is ended in steps 07 to S4011.

In the eighteenth to twenty-second embodiments, the case where the grid point data is stored in the LUT and the image is output based on the LUT is described. Of course, four kinds of data stored in advance in the LUT are used. It is also possible to form an image based on fixed grid point data.

In the above description, the case of so-called frame sequential is explained, but for example, the case of dot sequential when M, C, Y and Bk are recorded in 1 pixel units like an ink jet printer. It is obvious that the same applies to the present invention.

[0246]

As described above, according to the present invention,
Depending on the sum of the address data or the sum of the address data and the value of the switching control signal, the address accessed in each look-up table is always limited to the address in a certain area. As a result, different types of conversion data stored in different areas in each of the plurality of look-up tables can be stored, and 1
It is possible to access only the table area having one conversion characteristic.

On the other hand, by changing the contents of the switching signal, it is possible to change the above-mentioned area in each look-up table, and thus it is possible to access a table area having another type of conversion characteristic. As a result, it is possible to perform multiple types of conversion.

As a result, the redundancy of the LUT, which has been a problem in a device having a plurality of LUTs for data conversion, can be eliminated, and the LUT can be used 100% effectively.

Further, according to the present invention, it is possible to provide an image forming apparatus incorporating the above-mentioned lookup table.

[Brief description of drawings]

FIG. 1 is a schematic diagram conceptually showing an interpolation space defined by upper bits of three input data.

FIG. 2 is a schematic diagram conceptually showing a general interpolation space of a 4-point interpolation method.

FIG. 3 is a block diagram showing a configuration of an interpolation calculation used in the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an interpolation calculation used in the embodiment of the present invention.

FIG. 5 is a block diagram showing a main configuration of a data conversion apparatus according to the first embodiment of the present invention.

FIG. 6 is a schematic diagram showing an operation concept of a switch for address, data, etc. used in a data converter according to an embodiment of the present invention.

7 (a) to 7 (d) are explanatory views for explaining address exchange in the above embodiment.

FIG. 8 is an explanatory diagram showing a relationship between an access area of each LUT and a switching control signal in the above embodiment.

FIG. 9 is a block diagram showing a main configuration of a data conversion device according to a second embodiment of the present invention.

FIG. 10 is an explanatory diagram for explaining address exchange in the above embodiment.

FIG. 11 is a block diagram showing a main configuration of a data conversion device according to a third embodiment of the present invention.

FIG. 12 is an explanatory diagram for explaining address exchange in the above embodiment.

FIG. 13 is a block diagram showing the main configuration of a data conversion device according to a fourth embodiment of the present invention.

FIG. 14 is a block diagram showing the main configuration of a data conversion device according to a fifth embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a relationship between an access area of each LUT and a switching control signal in the above embodiment.

FIG. 16 is a block diagram showing the main configuration of a data conversion device according to a sixth embodiment of the present invention.

FIG. 17 is a block diagram showing the main configuration of a data conversion device according to a seventh embodiment of the present invention.

FIG. 18 is an explanatory diagram showing a relationship between an access area of each LUT and a switching control signal in the above embodiment.

FIG. 19 is a block diagram showing the main configuration of a data conversion device according to an eighth embodiment of the present invention.

FIG. 20 is a block diagram showing the main configuration of a data conversion device according to a ninth embodiment of the present invention.

FIG. 21 is a block diagram showing the main configuration of a data conversion device according to a tenth embodiment of the present invention.

FIG. 22 is a block diagram showing the main configuration of a data conversion device according to an eleventh embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration for address generation according to a twelfth embodiment of the present invention.

FIG. 24 is a block diagram showing the main configuration of a data conversion device according to a twelfth embodiment of the present invention.

FIG. 25 is a block diagram showing the main configuration of a data conversion device according to a thirteenth embodiment of the present invention.

FIG. 26 is a block diagram showing the main configuration of a data conversion device according to a fourteenth embodiment of the present invention.

FIG. 27 is a block diagram showing the main configuration of a data conversion device according to a fifteenth embodiment of the present invention.

FIG. 28 is a block diagram showing the main configuration of a data conversion device according to a sixteenth embodiment of the present invention.

FIG. 29 is an explanatory diagram showing a relationship between an access area and a switching control signal in the above embodiment.

FIG. 30 is a block diagram showing the main configuration of a data conversion device according to a seventeenth embodiment of the present invention.

FIG. 31 is a flow chart showing a procedure of access area switching and image output control associated therewith according to an eighteenth embodiment of the present invention.

FIG. 32 is a timing chart of various signals in the above control.

FIG. 33 is a block diagram showing a configuration for executing the control procedure.

FIG. 34 is a flow chart showing a procedure of access area switching and image output control associated therewith according to a nineteenth embodiment of the present invention.

FIG. 35 is a timing chart of various signals in the above control.

FIG. 36 is a flowchart showing a procedure of access area switching and image output control accompanying it according to a twentieth embodiment of the present invention.

FIG. 37 is a timing chart of various signals in the above control.

FIG. 38 is a flow chart showing a procedure of access area switching and image output control associated therewith according to a twenty-first embodiment of the present invention.

FIG. 39 is a timing chart of various signals in the above control.

FIG. 40 is a flow chart showing a procedure of access area switching and image output control associated therewith according to a twenty-second embodiment of the present invention.

FIG. 41 is a timing chart of various signals in the above control.

FIG. 42 is a block diagram showing a configuration for executing the control procedure.

FIG. 43 is a schematic diagram showing an example of an image output in the above embodiment.

[Description of Reference Signs] 111 to 114 +1 Adder 121 to 126, 461 to 468, 621 to 624, 7
01-706, 922, 923 Selectors 141-144, 321-324, 501-504, 8
01-803, 841-845, 901, 902 LU
T 151-155 Multiplier 171-174 Subtractor 181,362-364,471,473,711-7
22,836,891 Adder 182 Shifter 211-213 Comparator 311-316, 401-405, 441-445, 5
21,522 Address Exchangers 341-346, 411-415, 451-455, 5
23,524 Data exchanger 512-514,551 exclusive-OR element 581 Address generation block 591 Address rearrangement block 601-604, 611-614 RAM 631 Decoder 700 Address selection block 741 Multiplication coefficient rearrangement block 831,879 Residual calculator 885 data rearrangement block 915, 916, 924, 925 register

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04N 1/46 G06F 15/68 310 A H04N 1/40 D 1/46 Z

Claims (16)

[Claims] 1. A data conversion device that performs data conversion using a plurality of look-up tables, wherein address data that should correspond to each of the plurality of look-up tables is generated based on input data to be converted. Generating means, exchanging means for defining look-up tables respectively corresponding to the plurality of address data generated by the generating means, based on the address data generated by the generating means and the number of the plurality of look-up tables. A data conversion device comprising: 2. A data conversion device for performing data conversion by interpolation calculation using a plurality of look-up tables, wherein an address corresponding to each of the plurality of look-up tables is based on a part of input data to be converted. The address generation means generates the data based on the address generation means for generating data, the address data generated by the address generation means, the conversion switching control signal, and the number of types of data conversion switched by the switching control signal. Between address exchange means for defining a look-up table corresponding to each of the plurality of address data, and data output from each of the plurality of look-up tables based on each address defined by the address exchange means and an interpolation calculation coefficient. In the address exchange means A data conversion device comprising: an interpolation calculation unit that performs a symmetrical exchange with a dress exchange and performs an interpolation calculation based on a combination of the data and an interpolation calculation coefficient. 3. The data converter according to claim 2, wherein when the value of the switching control signal is constant, the remainder is constant for each of the plurality of look-up tables. 4. The data conversion apparatus according to claim 2, wherein the symmetrical exchange in the interpolation calculation means is performed based on the remainder. 5. The data conversion apparatus according to claim 1, wherein the data output from each of the plurality of look-up tables is output from the plurality of look-up tables at one time. 6. The data conversion according to claim 1, wherein the data output from each of the plurality of look-up tables is output from the plurality of look-up tables in a plurality of times. apparatus. 7. The address generation by the address generation means and the interpolation calculation by the interpolation calculation means
7. The data conversion device according to claim 1, wherein the interpolation calculation for each of the plurality of lookup tables is integrated into one interpolation calculation. 8. The input data is R (red), G (green)
And B (blue) color signal data, and the conversion data is M (magenta), C (cyan), Y (yellow), and Bk (black) color signal data. 7. The data conversion device according to any one of 7. 9. The type of data conversion is to print M (magenta), C (cyan), Y (yellow), Bk (black) on plain paper or OHP paper, respectively, or a text image or a natural image. 9. The type of data conversion in the case of using M (magenta), C (cyan), Y (yellow), and Bk (black) when printing an image, according to claim 2. Data converter. 10. The data conversion apparatus according to claim 2, wherein the switching control signal is output according to the operation of the image forming apparatus. 11. The data of the plurality of look-up tables are updated by being stored in the look-up tables respectively corresponding to the address data defined by the address exchanging means. The data converter according to any one of 1. 12. An image forming apparatus comprising the data conversion device according to claim 2. 13. The address exchanging means determines the address data corresponding to the look-up table according to the operation of the image forming apparatus.
The image forming apparatus according to item 1. 14. The image forming apparatus according to claim 12, wherein the operation of the image forming apparatus is an operation of detecting a type of a medium on which an image is formed. 15. The image forming apparatus is a frame-sequential color image forming apparatus, and addresses are exchanged in the address exchanging means in accordance with the frame-sequential color image forming operation. 15. The image forming apparatus according to any one of 14. 16. A data storage method for storing data in a plurality of look-up tables, wherein address data in the plurality of look-up tables of data to be stored is generated, and the generated addresses and the stored data are stored. A lookup table to which the generated address data corresponds, based on the number of types of data, and to store the corresponding table data in the determined lookup table. How to store table data.