JP4288865B2 - Color interpolation method and color interpolation apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a color interpolation method and a color interpolation device, and more particularly to a color interpolation method and a color interpolation device which are speeded up. As a color conversion method, calculation using a multidimensional LUT and an interpolation calculator is known. U.S. Pat. No. 4,837,722 proposes a method of calculating by interpolating interpolation calculators in parallel for high-speed calculation.
[0002]
[Prior art]
Color printers, color scanners, color copiers, and the like often perform color correction on color separation digital image data obtained by photoelectric scanning. The color correction of the digital image data as described above may be performed by calculation, but has already been corrected corresponding to a combination of color separation image data (for example, a combination of three primary color image data of red R, green G, and blue B). A combination of image data (for example, ink amounts of yellow Y, magenta M, cyan C, and black K) is stored as a conversion table, and a combination of data that has been corrected (conversion) using the combination of the data before correction as an addressing signal. (Output data) may be configured to be read out.
[0003]
In the data conversion using the conversion table as described above, if a combination of correction data corresponding to all combinations of input data is stored, an enormous storage capacity is required, which increases the cost of the memory used as the conversion table. Therefore, it is generally performed that the conversion output data is appropriately thinned and stored, and the correction data corresponding to the combination of input data corresponding to the thinned portion is obtained by interpolation calculation.
[0004]
As described above, as a technique for performing data conversion using a conversion table with interpolation calculation, as disclosed in Japanese Patent Publication No. 58-16180 and Japanese Patent Publication No. 63-162248, etc. There is something. In Japanese Examined Patent Publication No. 58-16180, a three-dimensional space formed by three-dimensional input digital data is divided into a plurality of unit cubes, and converted output data is stored in correspondence with the vertices of the plurality of cubes. Configure the table.
[0005]
Then, the unit cube is divided into a plurality of (5 or 6) tetrahedrons composed of four vertices among the eight vertices of the unit cube, and four vertices of a tetrahedron including points corresponding to three-dimensional input data. The conversion output data in each is read, and the four conversion output data are interpolated to output final conversion output data for the three-dimensional input data.
[0006]
In Japanese Patent Laid-Open No. 63-162248, the cube is used as it is by interpolation from eight converted output data read corresponding to eight vertices of a cube including points corresponding to three-dimensional input data. The final converted output data is output. In the data conversion disclosed in the above Japanese Patent Publication No. 58-16180 and Japanese Patent Laid-Open No. 63-162248, the number of conversion output data to be stored in the conversion table can be reduced by using an interpolation operation to increase the memory capacity. In addition to keeping it small, non-linear conversion can be performed with a small error, and the hardware is relatively small, and a relatively high-speed circuit can be realized.
[0007]
[Problems to be solved by the invention]
When performing operations in parallel, there is a problem that the circuit becomes complicated because it must be designed as a whole. Further, one unit cannot be used repeatedly, and for example, a multiplier and an adder are used separately. Also, the number of interpolation calculation points is fixed by hardware. However, for example, the input data is L ^* a ^* b ^* It is known that 8-point interpolation is optimal, and 4-point interpolation is optimal when the input data is R, G, B, Y, M, or C. In this case, the optimum interpolation calculation is not performed for each.
[0008]
The present invention has been made in view of such problems, and an object of the present invention is to provide a color interpolation method and a color interpolation apparatus capable of high-speed calculation. That is, the first is to minimize the total amount of memory and achieve the maximum computing capacity, and the second is to arrange the same type of units, facilitating parts and timing design, and third, to easily interpolate. We propose a mechanism that can change the required number of grid points.
[0009]
[Means for Solving the Problems]
(1) The invention according to claim 1 is the entire color conversion table. Table values for every other grid Multiple color conversion tables The Have An operation for sequentially accumulating operation results using each of the plurality of color conversion tables. And color interpolation is performed.
[0010]
By configuring in this way, the same unit can be used and pipelined by arranging the arithmetic circuits serially, Processing The speed can be increased.
(2) The invention according to claim 2 overall The color conversion table is n colors Input data is input Be done Sometimes divided into 2 n powers Has been It is characterized by that.
[0011]
If comprised in this way, the number | score of interpolation calculation can be set freely.
(3) The invention according to claim 3 is divided. plural The combinations that do not use the color conversion table at the same time are arranged in parallel.
[0012]
With this configuration, the delay can be reduced.
(4) The invention described in claim 4 For input of n-color input data, When interpolating with less than 2 to the power of n, When performing an operation using each of the plurality of color conversion tables, Do not use the color conversion table The operation multiplies by 0 It is characterized by that.
[0013]
If comprised in this way, the effect equivalent to bypassing with a simple structure will be acquired.
(5) The invention according to claim 5 Variablely select the number of interpolation calculation points according to the type of input data It is characterized by that.
[0014]
If comprised in this way, the optimal interpolation calculating means can be selected according to input data.
(6) The invention according to claim 6 is the entire color conversion table. Table values for every other grid Multiple color conversion tables The Have An operation for sequentially accumulating operation results using each of the plurality of color conversion tables. Calculate using Calculation unit It is characterized by having.
[0015]
With this configuration, the same units can be used and the pipelines can be speeded up by arranging the arithmetic circuits serially.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention, taking the case of three-dimensional input as an example. In the figure, reference numeral 1 denotes a bit distributor that receives 24 bits of input data and distributes the bits. The input 24-bit data is, for example, R is 8 bits, G is 8 bits, and B is 8 bits. A coefficient generator 2 receives the output signal from the bit distributor 1 and outputs a weight and an address. There are eight coefficient generators 2 from # 0 to # 7. These coefficient generators 2 are connected in series such that # 0 enters # 1 and # 1 enters # 2.
[0017]
Reference numeral 10 denotes an arithmetic unit using eight sub-LUTs and eight multiplier accumulators. Reference numeral 3 denotes a sub-LUT and a multiplier / accumulator (hereinafter simply referred to as an arithmetic unit), and as shown in the figure, eight are connected in series from # 0 to # 7. Zero data is input as input to the # 0 arithmetic unit. The output of the # 0 computing unit enters the # 1 computing unit, and the output of the # 1 computing unit enters the # 2 computing unit. Thereafter, the same connection is made, and the calculation output is accumulated. In the calculation unit 10, reference numeral 4 denotes a divider that receives the output of the final-stage calculator and divides it by the sum of the weights to obtain an output (8 bits).
[0018]
The arithmetic unit 10 shown in the figure is provided for each of Y, M, and C. That is, 10 is a Y-system arithmetic unit, 20 is an M-system arithmetic unit, and 30 is a C-system arithmetic unit. An 8-bit calculation output is obtained from each calculation unit. If there is K or spot color output, this unit will increase. The color conversion LUT value is input in common to each calculation unit. This color conversion LUT value is divided and given for each computing unit 3. Each coefficient generator 2 gives a weight and an address to the corresponding arithmetic unit 3. The circuit shown in the figure operates in synchronization with a timing clock (not shown). The operation of the circuit thus configured will be described as follows.
[0019]
The embodiment shown in FIG. 1 is a circuit that realizes a four-point interpolation method using a triangular pyramid. FIG. 2 is an explanatory diagram of four-point interpolation using a triangular pyramid. When a cube is divided by triangular pyramids, it is divided into six triangular pyramids. Then, an interpolation formula is obtained for each condition. For example, when x ≧ y ≧ z, the interpolation value p of an arbitrary point P in the triangular pyramid _xyz Is expressed by the following equation.
[0020]
p _xyz = P _a (1-x) + p _b (Xy) + p _c (Yz) + p _g z (1)
However, this equation shows the case where the lattice spacing is 1. Here, pa to pg indicate the values of the vertices of the triangular pyramid. The circuit shown in FIG. 1 implements the expression (1) in hardware.
[0021]
When the original LUT for three-dimensional interpolation is N × N × N (N is an even number), it is divided into eight and transferred to each block. In this dividing method, as shown in FIG. 3, every other data arranged is divided into eight (N / 2) × (N / 2) × (N / 2) LUTs. In FIG. 3, when the entire LUT shown in FIG. 3A is made up of every other point of .largecircle., .Quadrature., .DELTA., And x, and divided by the data constituted by each point, (b) to (e) of FIG. Is divided as shown in FIG. The figure shows a two-dimensional case. In the case of three dimensions, it is divided into eight.
[0022]
The LUT divided in this way will be referred to as a secondary LUTn. Here, n is a number from 0 to 7. In this sub-LUT, when n is changed from 0 to ((N / 2) -1) and its binary number is i, j, k,
LUTn [I] [J] [K] = LUT [2 · I + i] [2 · J + j] [2 · K + k] (2)
Is an LUT having a size of 1/8. Here, I, J, and K are R, G, and B addresses of 0 to 7, and i, j, and k are values of 0 or 1. Expression (2) indicates that the secondary LUT corresponds to the address indicated in Expression (2) of the original LUT represented by the right side. That is, the sub-LUT on the left side is taken from the location represented by the address of the LUT shown on the right side. As described above, according to the present invention, the number of interpolation calculations can be freely set by dividing the color conversion table into 2 n powers when n colors are input.
[0023]
Here, the description will be made assuming that N = 16. In FIG. 1, input R, G, B values are divided by the bit sorter 1 into upper and lower values for each color and upper and lower determination values. FIG. 4 is a block diagram showing an embodiment of the bit distributor 1. The input value is 24 bits in total, 8 bits for each of R, G, and B. R enters the R channel 40, G enters the G channel 41, and B enters the B channel 42.
[0024]
For example, in the R channel 40, 50 is an upper / lower bit distributor that receives 8-bit R data, and 51 is an upper half / lower half distributor that receives the output of the upper / lower bit distributor 50. The upper / lower bit distributor 50 outputs a 3-bit upper value (0 to 7), and the upper half / lower half distributor 51 outputs a 1-bit upper / lower discrimination value and a 5-bit lower value (0 to 0). 16) is output. The above configuration is the same for other G channels and B channels. The 5-bit lower value output from the R channel, the G channel, and the B channel enters the triangular pyramid code generator 43, and the triangular pyramid code generator 43 outputs a 3-bit triangular pyramid code (0 to 5). Is done. In the triangular pyramid code, codes from 0 to 5 are assigned to the triangular pyramid shown in FIG. 2 to identify each triangular pyramid. The combinations of the triangular pyramid generation codes are as shown in FIG. For example, the triangular pyramid code when B ≧ R ≧ G is “4”.
[0025]
Here, the upper value, the upper / lower discriminant value, and the lower value are calculated by the calculation formula shown in FIG. For example, the upper value is represented by an input value / 34, the primary lower value is represented by a remainder (% 34) obtained by dividing the input value by 34, the up / down discrimination value is represented by an input value / 17, and the final value The lower value is represented by the input value% 17. The triangular pyramid code generator 43 outputs a code for determining the position of the triangular pyramid (a combination of four points) used for the interpolation calculation using the final lower values of the three colors. The data output here is transferred to the next coefficient generator 2 (# 0) in synchronization with each calculation.
[0026]
FIG. 6 is a block diagram showing an embodiment of the coefficient generator. The coefficient generator 2 outputs an address for the secondary LUTn and a weighting coefficient for interpolation calculation, and sends them to the secondary LUTn and multiplier block (arithmetic unit) 3. The upper values (0 to 7) for each of R, G, and B from the bit sorter 1 enter the adder 61, and the lower value (0 to 16) and the upper and lower discrimination bits (0 to 1) are address generation / weight generation. Enter the vessel 60. The address generator / weight generator 60 also contains LUT ID [0-7]. This LUT ID is the same as the position data shown in FIG.
[0027]
The address generator / weight generator 60 generates an increment address and a weight coefficient for each of R, G, and B. Here, the increment address is for adding 1 to the necessary axis based on the smallest value when designating the address of the LUT. For example, when (3, 4) is a base address in two dimensions, +0 or +1 is performed as in (4, 4), (4, 5). Thus, the position of the triangular pyramid is determined. Here, determining the position of the triangular pyramid means determining which of the LUT lattices (the triangular pyramid constituted by any point of the lattice is used).
[0028]
The upper value (0 to 7) and increment address (0 to 1) for each of R, G, and B enter the adder 61, and the adder 61 generates an R address (0 to 7). This configuration is the same for the remaining G channel and B channel. From the R channel, the G channel, and the B channel, respective addresses are generated to enter the computing unit 3, and weight coefficients (0 to 17) are generated to enter the computing unit 3. On the other hand, the upper value, the lower value, the upper / lower discrimination bit, and the triangular pyramid code enter the next coefficient generator 2.
[0029]
FIG. 7 is a block diagram illustrating one embodiment of an address / weight generator 60 in the coefficient generator. The lower value (0 to 16) for each of R, G, and B enters the difference calculation unit 70. The difference calculation unit 70 receives the R, G, B subordinate values and the 4-bit output from the difference calculation indicator 71 and generates a weight coefficient (0 to 17). The difference calculation indicator 71 has a table as shown in FIG. A weight corresponding to the triangular pyramid code is assigned to each LUT code.
[0030]
The LUT code is divided into 000, 001, 010, 011, 100, 101, 110, and 111, and a weight is given to each triangular pyramid. Four weights are given for each triangular pyramid. For example, in the case of the triangular pyramid code “3”, the LUT code 000 is 2, 010 is 7, 110 is 8, and 111 is 12. Four weights are given to each triangular pyramid. The fact that there are four weights for each triangular pyramid and the remaining is zero corresponds to the fact that equation (1) consists of four multiplication terms. That is, although there are eight computing units 3 in FIG. 1, four are actually performing the computation. As described above, according to the present invention, when the entire color conversion table is divided into a plurality of color conversion tables and interpolation is performed with a number smaller than 2 to the power of n, 0 is applied to a portion not using the color conversion table. By adding the weight, an effect equivalent to bypassing with a simple configuration can be obtained.
[0031]
In FIG. 7, reference numeral 72 denotes an exclusive OR circuit, which receives LUTID [0 to 7] and R / G / B upper / lower discrimination bits, outputs a 3-bit LUT code, and gives it to the difference calculation indicator 71. . The difference calculation instruction unit 71 receives the 3-bit LUT code and the triangular pyramid code, outputs the 4-bit weight data shown in FIG.
[0032]
The difference calculation unit 70 receives the lower value for each of R, G, and B and the 4-bit weight data from the difference calculation indicator 71, performs the difference calculation as shown in FIG. 17) is output. The AND circuit 73 receives the upper / lower discriminating bits for each of R, G, and B and the 3-bit output from the exclusive OR circuit 72, and gives an increment address (0 to 1) for each of R, G, and B. Output.
[0033]
As described above, as shown in FIG. 6, the coefficient generator 2 outputs the address and interpolation calculation weight coefficient for the sub-LUTn, and sends them to the block (arithmetic unit) 3 of the sub-LUTn and multiplication accumulator. The address generator / weight generator 60 performs bit manipulation and the processing shown in FIGS. As a result, the incremental address for the weighting factor and the sub-LUTn is calculated.
[0034]
In the present invention, since the original LUT is divided into a plurality of sub-LUTs, for example, when the up / down judgment value is 0, no increment occurs. When the up / down judgment value is 1, the type of LUT to be selected is changed. In addition, the incremental address becomes 1. Each color increment address is added to each color upper value. However, there is an upper limit. In this case, the maximum address 7 of the secondary LUT is not exceeded (see FIG. 6).
[0035]
The secondary LUTn and multiplication accumulator (arithmetic unit) 3 receives the data of the previous stage, multiplies the LUT data output by the address for the secondary LUTn and the weight, accumulates it, and sends it to the next stage. In this case, 0 data is given to the arithmetic unit 3 in the first stage. If no weight is generated for the secondary LUTn (when not used), a weight of 0 is given. In this case, the stage may be bypassed by using a selector instead of performing multiplication with 0.
[0036]
FIG. 10 is a block diagram showing an embodiment of the sub-LUTn and the multiplier (arithmetic unit) 3. In the figure, reference numeral 80 denotes a sub-LUTn which receives an address (3 × 3 bits) and receives a color conversion LUT value and outputs data corresponding to the input address. The secondary LUTn outputs 8-bit data. A multiplier 81 receives the weighting coefficient (5 bits) from the coefficient generator 2 and the output data from the sub-LUTn 80 and performs multiplication. The multiplier 81 outputs 13-bit data. Reference numeral 82 denotes an adder that adds the data (8 + 5 bits) from the computing unit 3 in the previous stage and the output (13 bits) of the multiplier 81. The output (13 bits) of the adder 82 becomes the output of the arithmetic unit 3 at the corresponding stage. Here, the output of the sub-LUTn, the output of the multiplier 81, and the output of the adder 82 are latched so that the data is shifted from left to right with a synchronous clock, enabling high-speed operation. It can be said. The operation of the circuit thus configured will be described as follows.
[0037]
A weight coefficient (5 bits) and an address (3 × 3) bits are input from the coefficient generator 2 to the calculator 3. Of these, the address enters the secondary LUTn, and 8-bit conversion data is output from the secondary LUTn. The multiplier 81 multiplies the output of the sub-LUTn by the weight coefficient (5 bits). The multiplication result is added to the data from the previous stage by the subsequent adder 82, and the output (8 + 5 bits) enters the arithmetic unit 3 at the subsequent stage.
[0038]
By performing this calculation process in eight stages, a product of the sum of the weighting coefficients and the final value is calculated. This multiplication value is divided by the sum of the weighting coefficients by the divider 4 (see FIG. 1) and becomes the final output. The divider 4 may be created by logic or LUT. In the case of four-point interpolation with 16 × 16 × 16 grid points, the total weight is 17. Thus, according to the present invention, by arranging the arithmetic circuits serially, the same unit can be used and a pipeline can be formed, so that the speed can be increased.
[0039]
When the processing as described above is performed, each block, and further, the inside of each block is divided into several stages and pipelined to realize a high-speed throughput. For example, as shown in FIG. 10, the speed is increased by providing a latch to narrow the pipeline width. However, in this case, a delay occurs until the first calculated value is output. When each block is pipelined, it is delayed by at least 8 clocks, and when the inside is further divided into several stages, it is delayed by the number of clocks multiplied by the number of stages. In either case, the delay time until data is first output varies depending on the number of stages, but since it is output once after it is output, there is no difference in throughput.
[0040]
In the above-described embodiment, the case where eight interpolation calculation points are provided is shown, but the present invention is not limited to this, and the number of interpolation calculation points can be varied. Thereby, an optimal interpolation calculation means can be selected according to the input data.
[0041]
FIG. 11 is a block diagram showing another embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 1 is a bit distributor that receives input data (R, G, B, 8 bits in total, 24 bits) and performs bit distribution, and 2 is a coefficient generator that receives input data and generates weights and addresses. There are 8 from # 0 to # 7. The # 0 coefficient generator 2 receives the position data (0) and the output of the bit distributor 1. The # 1 coefficient generator 2 receives the position data (1) and the output of the # 0 coefficient generator 2. The # 2 coefficient generator 2 receives the position data (2) and the output of the # 0 coefficient generator 2, and the # 3 coefficient generator 2 receives the position data (4) and the # 0 coefficient. The output of the generator 2 is input, the position data (3) and the output of the coefficient generator 2 of # 3 are input to the coefficient generator 2 of # 4, and the position data (5 ) And the output of the coefficient generator 2 of # 3 are input, the position generator (6) and the output of the coefficient generator 2 of # 2 are input to the coefficient generator 2 of # 6, and the coefficient generator 2 of # 7 is input. Contains the position data (7) and the output of the coefficient generator 2 of # 6.
[0042]
101 is a sub-LUT and multiplication accumulator (calculator), and there are two, # 0 and # 1. The # 0 arithmetic unit 101 is composed of a sub-LUT0 and a multiplication accumulator, and the # 1 arithmetic unit 101 is composed of a sub-LUT7 and a multiplication accumulator. Then, the weight coefficient and address from # 0 coefficient generator 2 are input to # 0 arithmetic unit 101, and zero data is input. The # 1 arithmetic unit 101 receives the weighting coefficient and address from the # 7 coefficient generator 2, and the output of the # 1 adder 103.
[0043]
Reference numeral 102 denotes an arithmetic unit composed of a sub-LUT and a multiplier, and there are six units from # 0 to # 5. The # 0 arithmetic unit 102 is composed of a sub-LUT 1 and a multiplier, the # 1 arithmetic unit 102 is composed of a sub-LUT 2 and a multiplier, and the # 2 arithmetic unit 102 is composed of a sub-LUT 4 and a multiplier. , # 3 arithmetic unit 102 is composed of a sub-LUT 3 and a multiplier, # 4 arithmetic unit 102 is composed of a sub-LUT 5 and a multiplier, and # 5 arithmetic unit 102 is composed of a sub-LUT 6 and a multiplier. Is done.
[0044]
Reference numeral 103 denotes an adder, and there are two, # 0 and # 1. The # 0 adder 103 contains the output of the # 0 arithmetic unit 101, the output of the # 0 arithmetic unit 102, the output of the # 1 arithmetic unit, and the output of the # 2 multiplier 102. The # 1 adder 103 includes the output of the # 0 adder 103, the output of the # 3 computing unit 102, the output of the # 4 computing unit 102, and the output of the # 5 computing unit 102. Yes. The output of the # 1 adder 103 enters the # 1 arithmetic unit 101, and the output of the # 1 arithmetic unit 101 enters the divider 4. Then, the divider 4 divides the accumulated value by the sum of the weighting coefficients and outputs it as 8-bit data. These arithmetic units, adders, and dividers constitute the arithmetic unit 100. There are n arithmetic units having such a configuration for each color.
[0045]
In the arrangement of the arithmetic units shown in FIG. 1, the delay is performed by at least eight pipelines. However, when the arithmetic units are arranged as shown in FIG. 11, the delay can be halved. Since there are combinations that do not occur simultaneously in the sub-LUTs of each block shown in FIG. 1, they are grouped in parallel. The sub-LUT 0 and the sub-LUT 7 are used in any triangular pyramid, but are not used simultaneously in the combination of the sub-LUTs 1, 2, 4 and the sub-LUTs 3, 5, 6.
[0046]
In such a group, an accumulator in each block can be omitted as shown in FIG. 11, and a 4-input adder 103 can be used as shown in the figure. In this case, all three types of inputs are added. This calculation may take OR (OR) instead of an adder. This is because only one value is generated. In addition, a selector can be used.
[0047]
According to this embodiment, the delay can be reduced.
In the embodiment shown in FIG. 1, since eight types of color conversion LUTs can be accessed, the interpolation method can be easily changed by controlling the weights. By using this, it is possible to switch between the 4-point interpolation and the 8-point interpolation of the first embodiment.
[0048]
As a method of interpolating with 8 points, there is Japanese Patent Laid-Open No. 8-114870 (multi-dimensional interpolation method and apparatus), but using this method is advantageous because the weighting factor is simplified. However, since the total sum of the weights is quadrupled, the calculation bit width needs to be increased accordingly. Furthermore, the denominator parameter of the divider at the final stage is also made variable. When the bit shift described later is used, the bit shift amount is changed. If the input is R, G, B or Y, M, C, then L using 4-point interpolation ^* a ^* b ^* Then, 8-point interpolation may be used. In this way, the vicinity of the input gray is accurately interpolated.
[0049]
Here, it is possible to obtain the interpolation value by bit shift by multiplying the table output in advance (2 to the power of n ÷ data grid interval). For example, if the output is 9 bits and the maximum value is 480 (255 × 32/17 times), it is sufficient to shift by 5 bits, and a divider that tends to be large can be omitted. However, the LUT capacity increases. If the maximum value is 240 (255 × 16/17 times), a 4-bit shift occurs, but the calculation accuracy slightly decreases.
[0050]
This method can also be realized by software. Although there is no effect with one MPU, when there are a plurality of MPUs, the color interpolation operation of this configuration can be effectively performed by calculating each step for each. For example, the calculation can be performed while relaying with a computer connected to the network. In the case of 4 dimensions, the same processing can be performed by arranging 16 arithmetic units, and in the case of N dimensions, it can be realized by arranging 2 N units.
[0051]
【The invention's effect】
As described above in detail, according to the present invention, the following effects are produced. (1) According to the invention described in claim 1, by arranging the arithmetic circuits serially, the same unit can be used and can be pipelined, so that the speed can be increased.
[0052]
(2) According to the second aspect of the present invention, the color conversion table is divided into 2 to the nth power when n colors are input, so that the number of interpolation calculations can be set freely.
[0053]
(3) According to the invention described in claim 3, delays can be reduced by arranging the combinations in which the divided color conversion tables are not used at the same time in parallel.
[0054]
(4) According to the invention described in claim 4, when the entire color conversion table is divided into a plurality of color conversion tables, and interpolation is performed with a number smaller than 2 to the power of n, the color conversion table is not used. By adding a weight of 0 to, an effect equivalent to bypassing with a simple configuration can be obtained.
[0055]
(5) According to the invention described in claim 5, by changing the number of interpolation calculation points, an optimal interpolation calculation means can be selected according to input data.
(6) According to the invention described in claim 6, by arranging the arithmetic circuits serially, the same unit can be used and can be pipelined, so that the speed can be increased.
[0056]
Thus, according to the present invention, it is possible to provide a color interpolation method and a color interpolation apparatus capable of high-speed calculation. That is, the first is to minimize the total amount of memory and achieve the maximum computing capacity, and the second is to arrange the same type of units, facilitating parts and timing design, and third, to easily interpolate. The required number of grid points can be changed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is an explanatory diagram of four-point interpolation using a triangular pyramid.
FIG. 3 is an explanatory diagram of division of an LUT.
FIG. 4 is a block diagram illustrating an embodiment of a bit distributor.
FIG. 5 is an explanatory diagram of a triangular pyramid cord.
FIG. 6 is a block diagram illustrating an example embodiment of a coefficient generator.
FIG. 7 is a block diagram illustrating an example embodiment of an address / weight generator.
FIG. 8 is a diagram showing the contents of a difference calculation indicator.
FIG. 9 is a diagram showing the contents of a difference calculation indicator.
FIG. 10 is a block diagram illustrating an embodiment of a sub-LUT and a multiplier.
FIG. 11 is a block diagram showing another embodiment of the present invention.
[Explanation of symbols]
1-bit sorter
2 Coefficient generator
3 Sub LUT and Multiplication Accumulator
4 Divider
10, 20, 30 arithmetic unit

Claims (6)

It has a plurality of color conversion tables in which the table values of the entire color conversion table are extracted every other grid, and performs color interpolation using an operation that sequentially accumulates the operation results using each of the plurality of color conversion tables. A color interpolation method characterized by that. The overall color conversion table, color interpolation method of claim 1, wherein the input data of n colors is divided into at 2 of n-th power is input. 3. The color interpolation method according to claim 2, wherein combinations in which the plurality of divided color conversion tables are not used simultaneously are arranged in parallel. When the input of n-color input data is interpolated with a number less than 2 to the power of n , when performing an operation using each of the plurality of color conversion tables, an operation that does not use the color conversion table is: The color interpolation method according to claim 1, wherein 0 is multiplied . Claim 1 or 3 SL placing color interpolation method characterized by variably selecting the interpolation calculation points according to the type of input data. An arithmetic unit that has a plurality of color conversion tables in which the table values of the entire color conversion table are extracted every other grid, and calculates using a calculation that sequentially accumulates the calculation results using each of the plurality of color conversion tables A color interpolation device characterized by comprising:

Images