JP4402523B2 - DATA CONVERSION METHOD, DATA CONVERSION DEVICE, PROGRAM, AND STORAGE MEDIUM - Google Patents

Description

The present invention relates to a data conversion method for conversion of data, data conversion equipment, related program, and a storage medium.

  Since color space conversion processing of image data is generally non-linear conversion, a lookup table storing output values for representative input values and an output value for calculating input values other than the representative input values are calculated. A conversion method combined with an interpolation operation is used.

  Here, as a typical input value setting method, it is common to set representative values at equal intervals of a power of 2 (8, 16, 32, etc.), and R (red), G (green) ), B (blue), when a color space consisting of three color components is input and data conversion is performed to another color space, as shown in FIG. 11, a three-dimensional rectangular parallelepiped indicating the range of input values is shown. Each side is divided into grids at equal intervals (four equal parts in FIG. 11), and the corresponding output values are stored in the lookup table with each vertex of the grid as a representative input value.

  As described above, the reason for performing the equidistant grid division of the power unit of 2 is that it is possible to simplify the calculation of the address for referring to the lookup table from the input value and the calculation of the weighting coefficient of the interpolation operation. FIG. 12 shows a configuration example of a conventional data conversion apparatus when such an equidistant grid division is performed.

  FIG. 12 shows an example of the configuration of the data conversion apparatus when the input value is composed of three components with 8 bits each, and equidistant grid division (grid interval 16) is performed.

  In FIG. 12, 1201, 1202, and 1203 are 8-bit input values, and their value ranges are from 0 to 255. When these three input values 1201 to 1203 are RGB image data, each corresponds to an R (red) component, a G (green) component, and a B (blue) component. A table address generation unit 1204 receives the MSB 4 bits of the input values 1201 to 1203 and calculates the address of corresponding data in a lookup table 1205 described later from the grid numbers of the input values 1201 to 1203. For interpolation, usually a plurality of table outputs are required. However, in the case of tetrahedral interpolation, the table address cannot be obtained unless it is determined which tetrahedron is used. The information of the tetrahedron selected from 1206 is obtained, and the addresses of all points necessary for interpolation are calculated.

  1205 is a look-up table, which is a table storing output values for typical input values. Here, since the input values are divided into equidistant grids with a grid interval of 16, the input values 1201 to 1203 are Output values of grid vertices corresponding to values 0, 16, 32, 48, (middle), 224, 240, 255 are stored, and the total number of data stored in the lookup table 1205 is 17 × 17. X17.

  Since the output value corresponding to the maximum input value 255 is stored in the lookup table 1205, only the last grid interval is 255-240 = 15. For this reason, the maximum input value 255 and the input values 240 to 254 may be treated specially, but they do not affect the overall configuration of the data conversion apparatus, and thus will not be described here. Depending on the situation, by using the virtual input value 256 instead of the maximum input value 255, the last grid interval becomes 16, and no special treatment is required. Aside from the special handling of the final grid with the grid interval 15, the grid number (0 to 15) indicating which grid the MSB 4 bits belong to among the 8 bits of the input values 1201 to 1203 is shown, and the LSB 4 Bits indicate relative positions within the grid.

  Reference numeral 1206 denotes a tetrahedron determination unit, which is necessary when performing tetrahedral interpolation by an interpolation calculation unit 1207 described later. The LSB 4 bits of the input values 1201 to 1203 are received, and from the magnitude relationship between them, the size in the grid is received. The relative positional relationship of the input values is obtained, and which tetrahedron is used for interpolation is determined. Further, the tetrahedron determination unit 1206 calculates an interpolation coefficient used in the interpolation according to the determined tetrahedron.

  An interpolation calculation unit 1207 receives a table output value from the lookup table 1205 and an interpolation coefficient from the tetrahedron determination unit 1206, performs an interpolation calculation by tetrahedral interpolation, and outputs an interpolation output value. Here, tetrahedral interpolation has been described, but the interpolation calculation processing performed by the interpolation calculation unit 1207 may be a method other than tetrahedral interpolation.

  As described with reference to FIG. 12, when using equidistant grid division, a data conversion apparatus can be configured with a relatively simple configuration. However, since color space data conversion processing has non-linearity, simple equidistant grid division is possible. Then, a data conversion error may become large.

  Therefore, as shown in FIG. 13, the data conversion error can be reduced by performing non-uniform grid division and finely dividing the highly nonlinear portion.

  FIG. 14 shows a configuration of a data conversion apparatus disclosed in Patent Document 1 as a conventional example of a data conversion apparatus in the case of an unequal interval grid.

  In FIG. 14, 1401, 1402, and 1403 are 8-bit input values, and each of the input values 1401 to 1403 is divided into two, MSB 3 bits and LSB 5 bits, to an address / interpolation coefficient generation unit 1404 described later. Entered. Reference numeral 1404 denotes an address / interpolation coefficient generation unit that outputs an address of a point used for interpolation to a lookup table 1405 described later, and outputs an interpolation coefficient to an interpolation calculation unit 1406 described later. Reference numeral 1405 denotes a lookup table, and 1406 denotes an interpolation calculation unit. Since the interpolation calculation processing performed by the interpolation calculation unit 1406 is not tetrahedral interpolation, there is no portion corresponding to the tetrahedron determination unit 1206 of FIG. 1407 is a coarse sample lookup table (LUT-1), 1408, 1409 and 1410 are fine sample lookup tables (LUT-2), and 1411 is an address generator.

  The difference between FIG. 14 and FIG. 12 resides in the address / interpolation coefficient generation unit 1404, and the contents will be described.

  The MSB 3 bits of each input value 1401-1403 are collected and refer to a coarse sample lookup table (LUT-1 in the figure) 1407 forming a 9-bit address. The coarse sample lookup table 1407 holds the following information for each three-dimensional grid when the input is divided at equal intervals by the grid interval 32.

  Base address: In the lookup table 1405, an address indicating the data of the base point of a coarse grid (equally spaced grid with a grid interval of 32).

  Sample rate: A code indicating whether or not a coarse grid is divided into finer grids (subsamples) and the ratio of subsamples. With this information, the size of the fine grid belonging to the coarse grid is determined, and the grid size is 32, 8, 4 or 2 for each component.

N _A , N _A · N _B : values indicating the size of the table in order to calculate the address of the lookup table 1405. If the coarse grid is subsampled, the size of the table relative to the subsampled values is determined by the ratio of the subsamples.

Among these pieces of information, the base address, N _A , N _A · N _B are input to the address generation unit 1411, and the sample rate is a fine sample lookup table (LUT-2 in the figure) 1408, 1409, 1410. Is input. Fine sample lookup tables 1408, 1409, and 1410 exist for each input value 1401 to 1403, and for the sample rate information obtained by the LSB 5 bits of the input value and the coarse sample lookup table 1407, Information is retained.

  Offset: Indicates an offset value to be added to the base address by the address generation unit 1411 according to the input value (LSB 5 bits). When the grid size indicated by the sample rate is 32 (no subsample), the offset value is 0, but in other cases, it belongs to a different grid depending on the input values of 0 to 31.

  Interpolation coefficient: Interpolation coefficient determined by the grid size indicated by the sample rate and the input value.

Of these pieces of information, the offset is input to the address generation unit 1411, and the interpolation coefficient is input to the interpolation calculation unit 1406. The address generation unit 1411 uses the base address N _A and N _A · N _B coming from the coarse sample lookup table 1407 and the offset information coming from the fine sample lookup tables 1408, 1409, and 1410 to perform lookup. The address given to the table 1405 is calculated.

In addition, as a conventional example of a data conversion apparatus that supports non-uniformly spaced grids, a normal that represents the distance between the input value and the base point of the grid to which the input value belongs in advance for all values of each input component There is one in which a table of converted values is created, and by using this table, selection of tetrahedrons for tetrahedral interpolation and calculation of interpolation coefficients are performed efficiently (see Patent Document 2). .
US Pat. No. 5,321,797 JP 2000-221973 A

  The conventional data conversion apparatus shown in FIG. 14 can realize data conversion corresponding to the unequal interval grid, but the two-stage table reference of the coarse sample lookup table 1407 and the fine sample lookup tables 1408 to 1410 is referred to. In particular, since the size of the coarse-sample lookup table 1407 is large, the mounting cost is higher than that of the data converter of the equidistant grid shown in FIG.

  In addition, the address generation unit 1411 needs to perform addition processing of the base address and offset, which complicates the address calculation processing.

  In addition, since the data conversion apparatus of Patent Document 2 prepares a lookup table indicating distances normalized with respect to all input values, a very diverse unequal interval grid can be realized. Since the size increases, the data conversion device with limited resources increases the implementation cost.

  Also, since address calculation for referring to the lookup table is not shown, this needs to be solved separately.

Therefore, the present invention has been made in view of the drawbacks of the prior art as described above, and in the case of performing data conversion of an equidistant grid, the non-uniformly spaced grid is not significantly increased in mounting cost. and to provide a data conversion method capable of performing data conversion, data conversion equipment, a program and a storage medium.

In order to achieve the above object, in the data conversion method of the present invention , in the input value of each component corresponding to the grid divided at unequal intervals between the minimum interval and the maximum interval, the range of the input value is reduced to the minimum value. the upper bits of the input value corresponding to the entry is divided at intervals as the input of the first table, the input value conversion step of converting grid numbers corresponding to the input value and the its grid spacing, said in the input value A shift step for shifting lower bits corresponding to the maximum interval by a shift amount corresponding to the grid interval converted in the first conversion step, and four sides used for interpolation according to the output value shifted in the shift step The second table is referred to by an address generated based on a determination step for determining a field and an interpolation coefficient, and the grid number and the tetrahedron determined in the determination step. And having an output step of outputting a value, an interpolation step of interpolating the output value by the interpolation factor.

In order to achieve the above object, the data conversion apparatus of the present invention is configured to reduce the range of the input value in the input value of each component corresponding to the grid divided at non-uniform intervals between the minimum interval and the maximum interval. the upper bits of the input value corresponding to the entry is divided at intervals as the input of the first table, the input value converting means for converting the grid numbers corresponding to the input value and the its grid spacing, said in the input value Shift means for shifting lower bits corresponding to the maximum interval by a shift amount corresponding to the grid interval converted by the first conversion means, and four surfaces used for interpolation according to the output value shifted by the shift means The second table is referred to by an address generated based on a determination means for determining a field and an interpolation coefficient, and the grid number and the tetrahedron determined in the determination step. And having output means for outputting a value, an interpolation means for interpolating the output value by the interpolation factor.

  According to the present invention, data conversion of non-uniformly spaced grids can be performed without increasing the mounting cost compared to the case of performing data conversion of equally spaced grids.

Data conversion method of the present invention, the data conversion equipment, embodiments of the program and the storage medium will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described with reference to FIGS.

  For the sake of specific explanation, the input value is assumed to be 8 bits and 3 components. Further, the grid interval of the unequal interval grid supported by the present invention is a power-of-two size, but here, three types of grid intervals of 4, 8, and 16 are supported.

  FIG. 1 is a block diagram showing a configuration of a data conversion apparatus according to the first embodiment of the present invention. This data conversion apparatus basically divides a range of each component of an input value into grids, Data conversion is performed by a look-up table that holds output values corresponding to the grid and an interpolation calculation means.

  In FIG. 1, 101, 102, and 103 are input values, each represented by 8 bits. For example, when the input values 101 to 103 are RGB image data, each of them is an R (red) component, G ( Green) component and B (blue) component are shown. Reference numerals 104, 105, and 106 denote input value conversion units (input value conversion means), 107 denotes a table address generation unit, 108 denotes a lookup table (LUT), 109 denotes a tetrahedron determination unit, and 110 denotes an interpolation calculation unit (interpolation calculation means). It is.

  In the case of the conventional data conversion apparatus shown in FIG. 12, the input values 1201, 1202, and 1203 are directly input to the table address generation unit 1204 and the tetrahedron determination unit 1206, but the data conversion according to this embodiment is performed. In the apparatus, the input values 101 to 103 are first converted into 9-bit data by the input value converters 104, 105, and 106. Details of this data conversion processing will be described later with reference to FIGS.

  The input value conversion units 104, 105, and 106 enable data conversion corresponding to grids that are divided at unequal intervals by converting input values to the data conversion means for grids that are equally divided.

  The table address generation unit 107 receives the upper 5 bits of the 9-bit value after the data conversion process, and generates an address for the lookup table 108. The operation of the table address generation unit 107 is basically the same as the operation of the table address generation unit 1204 in the case of the conventional data converter shown in FIG. 12, but the number of bits of the input value increases from 4 bits to 5 bits. Therefore, it is necessary to increase the number of bits used for calculation accordingly. In addition, since the number of grids of equally spaced grids (17 × 17 × 17 in FIG. 12) and the number of grids of unequally spaced grids do not always match each other, the number of grids is variable between a plurality of values.

  The look-up table 108 is the same as FIG. 12 except that the data content is data in the case of an unequal interval grid and the number of grids may not be the same as in the case of an equidistant grid. This lookup table 108 holds output values corresponding to the grid. Further, the tetrahedron determination unit 109 and the interpolation calculation unit 110 have the same functions as the tetrahedron determination unit 1206 and the interpolation calculation unit 1207 in FIG.

  Next, in the data converter according to the present embodiment, the input value converters 104, 105, and 106 which are different from the conventional data converter shown in FIG. 12 or FIG. I will explain.

  FIG. 2 is a block diagram showing the configuration of the input value conversion units 104 to 106 in the data conversion apparatus according to the present embodiment. As shown in the figure, the input value conversion units 104 to 106 include the grid number / grid. It consists of an interval table 201 and a shift unit (shift means) 202.

  The grid number / grid interval table 201 is referred to by a plurality of upper bits of the input value. The shift unit 202 shifts the lower bits of the input value according to the grid interval.

  In FIG. 2, among the 8-bit inputs input to the input value conversion units 104 to 106, the upper 6 bits are input to the grid number / grid interval table 201, and the lower 4 bits are input to the shift unit 202.

  The upper 6 bits and the lower 4 bits have an overlap of 2 bits.

  The grid number / grid interval table 201 has as many entries (64 in this example) as the number of input values divided by the minimum grid interval (4 in this example), and each entry is a component of one input value. 5 bits indicating the grid number to which the corresponding input value belongs, and 2 bits indicating the grid interval of the grid (in this example, distinction between 4, 8, and 16).

  FIG. 4 is a diagram illustrating an example of the grid number / grid interval table 201.

  In FIG. 4, the grid interval is indicated by values of 4, 8, and 16, but the grid number / grid interval table 201 stores a 2-bit code for distinguishing these.

  As can be seen from FIG. 4, since one entry of the grid number / grid interval table 201 corresponds to the range 4 of the input value range, in the case of the grid interval 16, the same grid number has four consecutive entries. When the interval is 8, two entries are continuous.

  The shift unit 202 uses the grid interval information obtained by referring to the grid number / grid interval table 201 and shifts the lower 4 bits of the input value to the left by an amount determined by the grid interval information, thereby generating 4-bit data. Output as. The number of bits (4 in this example) of data input to the shift unit 202 corresponds to the maximum grid interval (16 in this example). The 5-bit grid number output from the grid number / grid interval table 201 and the 4-bit output from the shift unit 202 are finally combined and output from the input value conversion units 104 to 106 as a 9-bit output value. The

  FIG. 3 is a diagram showing data in each unit along the flow of processing of the input value conversion units 104 to 106 in FIG. 2. In FIG. 3, the 8-bit input value 301 is an overlap of 2 bits. The upper bit and the lower bit are divided and input to the table reference unit 302 and the left shift unit 305, respectively. The reference processing result of the table reference unit 302 is a 5-bit grid number 303 and a code 304 indicating a 2-bit grid interval. The code 304 indicating the grid interval controls the operation of the left shift unit 305 according to the formula in the figure. This processing takes out the bit corresponding to the offset in the grid from the input value (lower 4 bits at grid interval 16, lower 3 bits at grid interval 8, lower 2 bits at grid interval 4), and the MSB is the maximum grid This corresponds to a process of shifting so as to correspond to the bit position in the case of the interval (16 in this example).

  The reason for performing such shift processing is that, as described with reference to FIG. 1, the data conversion processing operation following the input value conversion units 104 to 106 basically supports only conversion with respect to an equidistant grid. This is a process for pretending that an equally-spaced grid is input at a grid interval.

  The case where the input value (5, 33, 54) is input to the data conversion apparatus according to the present embodiment will be described. For the input value 5 of the first component, the upper 6 bits 0 and the lower 4 bits 5 Therefore, the grid number 0 and the grid interval 16 from the grid number / grid interval table 201 are not shifted by the shift unit 202, and the output of the lower bits is 5. Together with the grid number 0, the output value for the first component is 5.

  Next, since the input value 33 of the second component is the upper 6 bits 8 and the lower 4 bits 1, the grid number 2 and the grid interval 8 from the table are shifted by 1 bit in the shift unit 202. The output of the lower bit is 2. Together with grid number 2, the output value for the second component is 34.

  Furthermore, since the input value 54 of the third component is the upper 6 bits 13 and the lower 4 bits 6, the grid number 5 and the grid interval 4 from the grid number / grid interval table 201 and 2 in the shift unit 202. Since only the lower 4 bits are used after being bit-shifted, the output of the lower bits is 8. Together with the grid number 5, the output value for the third component is 88.

  In this way, the data converted by the input value converters 104 to 106 is regarded as a case of an equidistant grid having the maximum grid size (16 in this example) in the subsequent data converters. By performing the above, it is possible to perform data conversion processing in the case of a desired unequal interval grid.

  When the data conversion apparatus according to the present embodiment is compared with the conventional data conversion apparatus shown in FIG. 14, the data conversion apparatus according to the present embodiment requires less lookup table lookup, and Since the size of the uptable is small, the mounting cost can be suppressed.

  In the data conversion apparatus according to the present embodiment, the table address is generated in the case of the equidistant grid except that the number of bits of the grid number is increased and the number of grids is different from that of the equidistant grid. As in the case of the address generation unit 1411 in the conventional data conversion apparatus shown in FIG. 14, there is no need to add the base address and the offset.

  Further, when the data conversion device according to the present embodiment is compared with the data conversion device of Patent Document 2, the number of times of reference of the lookup table is not changed, but the data conversion device according to the present embodiment is more similar to the lookup table. The size of the table is small, and the implementation cost in a data conversion device with limited resources can be suppressed. Further, the data conversion apparatus according to the present embodiment also supports address calculation not disclosed in Patent Document 2.

  In the present embodiment, for convenience of explanation, the number of components of the input value, the number of bits of each data, the number of grids, grid intervals, etc. have been described as examples, but the present invention is The present invention can be applied without being limited to specific numerical values in this description.

  Also, a common grid number / grid interval table can be used for each component of the input value, or a different grid number / grid interval table can be used for each component.

  Also, the number of grids may be the same for each component of the input value, or may be different for each component, but it should be noted that the mounting cost increases as the degree of freedom increases. .

  Furthermore, in the present embodiment, the interpolation method has been described using tetrahedral interpolation, but the present invention can also be applied to other similar interpolation methods such as rectangular parallelepiped interpolation.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.

  The present embodiment relates to a processor capable of performing data conversion processing at high speed, and has a dedicated instruction (lookup table address calculation / interpolation coefficient calculation instruction and input value conversion instruction), which will be described later, at equal intervals. Data conversion processing corresponding to the grid and data conversion processing corresponding to the unequal interval grid can be performed at high speed.

  The processor according to the present embodiment can perform data conversion processing by a lookup table that divides a range of each component of an input value into grids and holds an output value corresponding to the grid, and an interpolation operation. is there.

  First, the data conversion process corresponding to an equidistant grid is demonstrated using FIGS.

  FIG. 5 is a flowchart showing an operation flow when the processor according to the present embodiment performs data conversion processing corresponding to an equidistant grid.

  When the input data is prepared, first, in step S501, each 8-bit, 3-component input value is read. In step S502, an address for referring to the lookup table and a coefficient used for interpolation are calculated. In step S503, a table output value is obtained by referring to the lookup table using the address obtained in step S502. Next, in step S504, interpolation calculation processing is performed using the table output value obtained in step S503 and the interpolation coefficient obtained in step S502. Next, in step S505, the output value is written, and in the next step S506, it is determined whether or not the number of output components (the number of output colors in the case of color space conversion) has reached a predetermined number. If it is determined that the number of output components does not reach the predetermined number, the process returns to step S503. If it is determined that the number of output components reaches the predetermined number, the processing operation ends.

  The processor according to the present embodiment has a dedicated instruction described below in steps S502 and S504 in order to perform the data conversion processing as described above at high speed.

  FIG. 6 is a diagram showing the processing operation of the LUT address / interpolation coefficient calculation command when processing 17 grids at equal intervals. This LUT address / interpolation coefficient calculation command performs data conversion for grids divided at equal intervals. It is for high speed. In addition, in order that the LUT address / interpolation coefficient calculation command corresponds to the output of the input value conversion command described later, “input is accepted and each component of the input value is in a range wider than the range of the input value at the time of equally spaced grid division. The number of grids corresponding to is variable.

  In FIG. 6, 601 is an input value, 602 is an upper bit, 603 is a lower bit, 604 is a tetrahedron base address calculation unit, 605 is a ternary magnitude comparison unit, 606 is an address offset calculation unit for three points of a tetrahedron, and 607 is An interpolation coefficient calculation unit, 608 is a three-point base address offset addition unit, 609 is a tetrahedral address output, and 610 is an interpolation coefficient output.

  In FIG. 6, “8-bit, 3-component input value 601” is divided into “4-bit, 3-component high-order bit 602” and “4-bit, 3-component low-order bit 603”. Used as an offset in the grid. The upper bits 602 are input to the tetrahedral base address calculation unit 604, and an address corresponding to the base point of tetrahedral interpolation is calculated and output. The lower bits 603 are input to the ternary magnitude comparison unit 605, and the comparison result of the three-component offset values in the grid is output. Since this comparison result determines which tetrahedron is used for interpolation, the offset of the other three points with respect to the base point of the tetrahedron interpolation is calculated by the address offset calculation unit 606 for the next three tetrahedrons. This offset is added to the base address by the next three-point base address offset adding unit 608 and output as an output tetrahedral address output 609 corresponding to the four vertices of tetrahedral interpolation. The comparison result of the value of the lower bits 603 and the ternary magnitude comparison unit 605 is also input to the interpolation coefficient calculation unit 607, and an interpolation coefficient output 610 used in the subsequent interpolation calculation processing is output.

  FIG. 7 is a flowchart showing the flow of the processing operation of the interpolation calculation command.

  In FIG. 7, input values are 8 bits, 4 sets of tetrahedral LUT value inputs 700, and 4 sets of interpolation coefficient inputs 701 previously calculated by the LUT address / interpolation coefficient calculation command shown in FIG.

  The interpolation calculation process is a process of multiplying and adding four sets of tetrahedral LUT values by corresponding interpolation coefficients. In FIG. 7, multiplications 702, 703, 704, and 705 indicate multiplication of four sets of values, Addition 706 indicates addition of multiplication results. The rounding process 707 is a process of rounding the number of effective bits increased by the multiplication / addition process according to the number of bits of the interpolation output value 708.

  By performing these series of processes with dedicated instructions, the data conversion process can be greatly accelerated.

  However, the way of sharing the processing of the dedicated instruction is not limited to the processing shown in FIGS. 6 and 7, and the instruction may be further divided from the mounting cost.

  Next, processing when data conversion of an unequal interval grid is performed will be described with reference to FIGS.

  FIG. 8 is a flowchart showing an operation flow when the processor according to the present embodiment performs data conversion processing corresponding to an unequal interval grid.

  In FIG. 8, steps S801 and S803 to 807 are the same as steps S501 to S506 in FIG.

  In FIG. 8, after the process of step S801 is completed, an input value conversion process is performed in step S802, and then the process proceeds to step S803.

  In step S802, since processing is performed with a dedicated instruction as described later, the data conversion processing can still be performed at a high speed although there is a slight decrease in processing speed compared to the case of the equidistant grid.

  The LUT address / interpolation coefficient calculation command will be described below because there are some differences from the case of the equidistant grid, but the interpolation calculation command is the same as the case of the equidistant grid and unequal spacing grid. The description is omitted.

  FIG. 9 is a diagram showing the processing operation of the LUT address / interpolation coefficient calculation command in the case of an unequal interval grid. In the figure, the lower bit 903, the three-value magnitude comparison unit 905, the interpolation coefficient calculation unit 907, and three points The base address offset adding unit 908, the tetrahedral address output 909, and the interpolation coefficient output 910 are the low-order bits 603, the ternary magnitude comparison unit 605, the interpolation coefficient calculating unit 607, the three-point base address offset adding unit 608, and the tetrahedron in FIG. Since it is the same as the address output 609 and the interpolation coefficient output 610, detailed description thereof is omitted.

  In FIG. 9, 901 is an input value, 902 is an upper bit, 903 is a lower bit, 904 is a tetrahedron base address calculation unit, 905 is a ternary magnitude comparison unit, 906 is an address offset calculation unit for three tetrahedrons, and 907 is An interpolation coefficient calculation unit, 908 is a three-point base address offset addition unit, 909 is a tetrahedral address output, 910 is an interpolation coefficient output, and 911 is the number N of grids.

  The number of grids in the case of unequal spacing grids is N (N ≦ 33) common to each input component. The first difference between FIG. 6 and FIG. 9 is that each component of the input value 901 is 9 bits by the input value conversion, and as a result, the upper bits 902 are increased to 5 bits and 3 components, The accuracy of the input bits of the body base address calculation unit 904 is increased.

  The second difference between FIG. 6 and FIG. 9 is that the number N of grids is usually different from that in the case of equidistant grids. Therefore, this is set to a settable value 911, and the tetrahedron base address calculation unit 904, tetrahedron 3 The calculation is given to the point address offset calculation unit 906. The grid number N911 can be set to an arbitrary value of 33 or less, but it is also conceivable to select from a plurality of selectable values determined in advance for the convenience of mounting cost.

  FIG. 10 is a diagram showing the processing operation of the input value conversion command when the grid is unequal.

  This input value conversion command converts the input value corresponding to the LUT address / interpolation coefficient calculation command, thereby enabling data conversion corresponding to the grid divided at unequal intervals. The input value conversion instruction refers to the grid number / grid interval table by a plurality of upper bits of the input value and shifts a plurality of lower bits of the input value according to the grid interval.

  The contents of the processing of the input value converter in the data converter according to the present embodiment and the contents of the grid number / grid interval table to be used are the input value converter in the data converter according to the first embodiment and This is the same as the grid number / grid interval table, and the 8-bit input value 1001 is divided into the upper bit 6 bits 1002 and the lower bit 4 bits 1003 in an overlapping manner for processing. The upper bits 1002 are input to the grid table reference unit 1004, and a 5-bit grid number 1006 and a 2-bit grid interval code 1007 are output with reference to the grid number / grid interval table 1005. The lower bit 1003 is input to the left shift unit 1008 and subjected to the shift processing described with reference to FIG. 3 in the first embodiment in accordance with the grid interval code 1007, and as a 4-bit lower bit shift result 1009. Is output. Finally, the grid number of 5 bits and the lower bits of 4 bits are combined and output as a 9-bit output value 1010.

  In the description of FIG. 10, since processing is performed on one component of the input value, when the input value conversion processing step S802 of FIG. 8 is realized using the input value conversion command shown in FIG. Since an input value conversion command is called for each component, a total of three command calls are required.

  If the mounting cost permits, it is possible to further increase the speed of the data conversion processing by performing the processing for a plurality of input value components in parallel in FIG.

  Also in the present embodiment, as in the first embodiment described above, specific numerical values such as the number of components of the input value, the number of bits of each data, the number of grids, the grid interval, and the like have been described as examples. The present invention is not limited to the specific numerical values in this description.

(Other embodiments)
The above is the description of the embodiments of the present invention. However, the present invention is not limited to these embodiments, and may be configured to achieve the functions shown in the claims or the functions of the configurations of the embodiments. Anything is applicable.

  Another object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to a system or apparatus, and store the computer (or CPU, MPU, etc.) of the system or apparatus. Needless to say, this can also be achieved by reading and executing the program code stored in the medium. In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium and program storing the program code constitute the present invention.

  As a storage medium for supplying the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. it can.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

It is a block diagram which shows the structure of the data converter which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the input value conversion part in the data converter which concerns on the 1st Embodiment of this invention. It is a figure which shows the process of the data by the input value conversion part in the data converter which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the grid number / grid space | interval table in the data converter which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of a processing operation of the processor at the time of equidistant grid processing in the data converter which concerns on the 2nd Embodiment of this invention. It is a figure which shows the processing operation of the LUT address / interpolation coefficient calculation command at the time of equidistant grid processing in the data converter which concerns on the 2nd Embodiment of this invention. It is a figure which shows the processing operation | movement of the interpolation calculation command at the time of the equidistant grid process in the data converter which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the flow of the processing operation of the processor at the time of the unequal-interval grid process in the data converter which concerns on the 2nd Embodiment of this invention. It is a figure which shows the processing operation | movement of the LUT address / interpolation coefficient calculation command at the time of the unequal-interval grid process in the data converter which concerns on the 2nd Embodiment of this invention. It is a figure which shows the processing operation | movement of the input value conversion command at the time of the unequal-interval grid process in the data converter which concerns on the 2nd Embodiment of this invention. It is a figure explaining general equal interval grid division. It is a block diagram which shows the structure of the data converter at the time of the conventional equal interval grid division | segmentation. It is a figure explaining general non-uniform spacing grid division. It is a block diagram which shows the structure of the data converter at the time of the conventional unequal-interval grid division | segmentation.

Explanation of symbols

101 Input Value 102 Input Value 103 Input Value 104 Input Value Conversion Unit (Input Value Conversion Unit)
105 Input value conversion unit (input value conversion means)
106 Input value converter (input value converter)
108 Look-up table 201 Grid number / grid interval table 202 Shift section (shift means)
301 Input value 306 Output value 601 Input value 901 Input value

Claims (4)

In the input value of each component corresponding to the grid divided at unequal intervals between the minimum interval and the maximum interval, the upper bits of the input value corresponding to the entry obtained by dividing the range of the input value at the minimum interval are As an input to the table of 1, an input value conversion step for converting the grid number corresponding to the input value and its grid interval ;
A shift step of shifting lower bits corresponding to the maximum interval in the input value by a shift amount corresponding to the grid interval converted in the first conversion step;
A determination step of determining a tetrahedron and an interpolation coefficient to be used for interpolation according to the output value shifted in the shift step;
An output step of outputting an output value by referring to a second table with an address generated based on the grid number and the tetrahedron determined in the determination step;
An interpolating step of interpolating the output value with the interpolating coefficient . In the input value of each component corresponding to the grid divided at unequal intervals between the minimum interval and the maximum interval, the upper bits of the input value corresponding to the entry obtained by dividing the range of the input value at the minimum interval are As an input of the table of 1, an input value conversion means for converting into a grid number corresponding to the input value and its grid interval ;
Shift means for shifting lower bits corresponding to the maximum interval in the input value by a shift amount corresponding to the grid interval converted by the first conversion means;
Determining means for determining a tetrahedron used for interpolation and an interpolation coefficient in accordance with the output value shifted by the shifting means;
An output means for outputting an output value by referring to a second table with an address generated based on the grid number and the tetrahedron determined in the determination step;
Interpolation means for interpolating the output value with the interpolation coefficient . Computer readable program order to realize the data conversion method according to the computer to claim 1. Computer-readable storage medium storing the order of the program to realize the data conversion method in a computer according to claim 1.

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