JPH08137451A - Data conversion device - Google Patents

Abstract

PURPOSE: To enhance operational precision without increasing the number of lattice points even when nonlinearlity of a function to be approximated is large by providing a secondary interpolation operation means as an interpolation operation means. CONSTITUTION: When (X', Y', Z') are imparted as input signals, the signals (X, Y, Z) of 24 bits are obtained through one-dimensional look-up tables(LUT) 101-103. The signals (XS, YS, ZS) consisting respectively of high-order 4 bits, in total 12 bits, of the respective signals (X, Y, Z) are sent to an address generator 104 to be converted to lattice point addresses A0 -A10 of 15 bits in the address generator 104. Then, the address signals A0 -A10 outputted from the address generator 104 are converted to corresponding lattice point values ϕ0 -ϕ10 by an LUT 106 to be inputted to an interpolation operation 105 together with a 12 bits signal consisting of a low-order (x, y, z). Further, the interpolation operation part 105 performs calculation using values of respective inputted signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion device for performing data conversion using a look-up table (hereinafter referred to as LUT) and an interpolation operation, and more specifically, for example, a digital color hard copy device (digital color image output). The present invention relates to a data conversion device applicable to color conversion processing of equipment and various image processing.

[0002]

2. Description of the Related Art A conventional example in which data conversion is performed by combining an LUT and a linear interpolation operation is an 8-point interpolation using a cube as an example applied to a color conversion device (for example, Japanese Unexamined Patent Application Publication No. 6-58242).
No. 3-162248), six-point interpolation using a triangular prism (for example, Japanese Patent Laid-Open No. 5-46750), four-point interpolation using a triangular pyramid (for example, Japanese Patent Publication No. 58-16180), and the like. ing. All of these known techniques are examples using a three-dimensional input space. Next, a conventional apparatus will be described by taking 8-point interpolation as a typical example.

A color conversion device using 8-point interpolation is usually shown in FIG.
It is configured as shown in. The input signal is 8 bits for each color, and the number of space divisions is 16 for each axis. Input signal (X,
Y, Z) is divided into upper 4 bits (X _S , Y _S , Z _S ) and lower 4 bits (x, y, z). (At this time, the upper 4 bits (X _S , Y _S , Z _S ) correspond to the origin coordinates of the partial interpolation space, and the lower 4 bits (x, y, z) correspond to the local coordinates of the interpolation target point in the partial interpolation space. These coordinates will be described later.) Of the divided signals, 1 consisting of (X _S , Y _S , Z _S )
The 2-bit signal is used as a region selection signal and is input to the address generators 2-9. The outputs of these address generators 2 to 9 are the coordinates taken by the eight vertex coordinates P0 to P7 of the partial interpolation space (x, y, z) system shown in FIG. 5 in the entire space (X, Y, Z) system. Is consistent with. Further, the LUTs 10 to 17 in the subsequent stage of the address generators 2 to 9 are three-dimensional LUTs in which output values to be taken are stored at 17∧3 grid points in the entire space, and the same contents are applied to all eight surfaces. It is assumed to be remembered.

Therefore, the output values at the eight vertices of the target partial interpolation space can be simultaneously obtained from the eight addresses output from the address generators 2-9 through the LUTs 10-17.

The output thus obtained is represented by Φ _i (i = 0,
1, ..., 7). As is clear from the explanations so far,
Φ0 to Φ7 indicate output values at the eight vertices P0 to P7 of the partial interpolation space shown in FIG. 5, respectively.

On the other hand, 12 bits consisting of (x, y, z)
Signal is input to the interpolation calculation block 1 together with the output signals of Φ0 to Φ7. The interpolation calculation block 1 is usually composed of a plurality of adders and multipliers, and performs an operation represented by the following equation (1) using these input signals.

[0007]

[Equation 1]

Here, S _i (x, y, z) is an interpolation function attached to eight grid points of the interpolation grid, and is common to all input spaces.

The correspondence between the interpolation space and the equation (1) will be described here. In FIG. 5, the cube O0. ． O7 represents the entire input space and is the cube P0. ． P7 represents a partial interpolation space. The origin coordinate P0 of the partial interpolation space is P0: (X _S , Y
_S , Z _S ). The coordinates of the interpolation target point are R =
(X, Y, Z), and the local coordinates in the partial interpolation space from these coordinates

[0010]

[Number 2] R '= (x, y, z) = (XX S, YY S, ZZ S) ... (2) is obtained.

On the other hand, the interpolation function associated with each grid point is shown in FIG.
From the above, it can be seen that Expression (1) is calculated by the interpolation function of FIG. 6 using the coordinate values in the input space of FIG. Thus, by using linear interpolation, it is possible to approximate an arbitrary function having the input space as a variable.

[0012]

However, in the above conventional example, since the linear interpolation method is used, there is a drawback that the interpolation error increases when the non-linearity of the approximated function is large. Further, if the number of grid points is increased in order to improve the approximation accuracy, the capacity of the memory increases accordingly, and the cost increases. For example, when the approximated function is a quadratic function, in order to reduce the interpolation error to 1/4, it is necessary to double the grid points in each axis, and in three dimensions, it is necessary to double the grid points. It will be.

The present invention has been made in view of the above points, and an object of the present invention is to increase the number of lattice points without increasing the number of grid points even when the non-linearity of the approximated function is large. Another object of the present invention is to provide a data conversion device capable of further increasing the calculation accuracy.

[0014]

In order to achieve the above object, the present invention provides a data conversion device for performing a data conversion process using a lookup table and an interpolation calculation means,
A quadratic interpolation calculation means is provided as the interpolation calculation means.

Further, in one aspect of the present invention, preferably, the quadratic interpolation operation of the quadratic interpolation operation means is performed using eleven grid points in a three-dimensional space obtained from a three-dimensional lookup table. Can be characterized.

Further, the present invention is preferably another embodiment.
The quadratic interpolation calculation of the quadratic interpolation calculation means may be performed by being divided into a linear interpolation calculation and a non-linear interpolation calculation.

Further, the present invention can be preferably characterized as having a switching means for switching between the linear interpolation calculation and the non-linear interpolation calculation according to the operating frequency of the system.

Further, in another aspect of the present invention, preferably, color conversion processing of a digital color printer is performed as the data conversion processing.

[0019]

In the present invention, the calculation accuracy is improved by providing the secondary interpolation calculation means.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows the configuration of the first embodiment of the present invention. In the figure, 101 to 103 are
This is a one-dimensional LUT provided for accommodating the input signals (X ', Y', Z ') within a predetermined bit length. Reference numeral 105 denotes an interpolation calculation unit that performs a secondary interpolation calculation. Reference numeral 104 is an address generator that generates the coordinates of the lattice points used for interpolation from the upper bits of the signal (X, Y, Z). Also, 106
Is a three-dimensional LUT for storing values corresponding to grid points used for interpolation.

In this example, the signals (X, Y, Z) are each 8
Given below, it is assumed that the upper (X _S , Y _S , Z _S ) is 4 bits and the lower (x, y, z) is 4 bits.

When (X ', Y', Z ') is given as an input signal, 2 through the one-dimensional LUTs 101-103.
A 4-bit signal (X, Y, Z) is obtained. At this time, 1
The conversion characteristics of the dimension LUTs 101 to 103 can be defined quite arbitrarily, but the upper limit of (X, Y, Z) is 1 for each.
It can be suppressed to 1101111. The upper 4 bi of each of the signals (X, Y, Z) thus obtained
t, signal composed of 12 bits in total (X _S , Y _S , Z _S )
Is sent to the address generator 104, and the address generator 1
In 04, it is converted into 15-bit lattice point addresses A _{0 to} A ₁₀ .

The grid point addresses A _{0 to} A ₇ have the same contents as those described in the block with reference numerals 2 to 9 in FIG. 4, and A _{8 to} A ₁₀ are represented as follows. It

[0025]

(Equation 3)

The address represented by the equation (3) is, for example, X
_{When S} = 0, A ₈ = (-1, Y _S , Z _S ) and a negative number is generated, but in binary 4 bits, -1 is 100
Considering that it is represented as 0, it is possible to easily perform mapping. That is, it suffices to prepare the grid points corresponding to when the address becomes -1 as shown in FIG. Note that FIG. 2 is shown in two dimensions for simplicity.

Here, it should be noted that the domain of the input space is an area where the address is positive, and the negative part is added only for the convenience of calculation. Therefore, the grid point value stored in the negative part needs to be determined so as not to cause a contradiction in the result obtained by the interpolation calculation.

The address signals A _{0 to} A ₁₀ output from the address generator 104 are converted into corresponding grid point values φ _{0 to} φ ₁₀ by the LUT 106, and together with the lower 12-bit signal consisting of (x, y, z). It is input to the interpolation calculation unit 105.

The LUT 106 has all the lattice point values (4b
In the case of it division, 16 ³ + 3 × 16 ² −6 × 16 = 47
(68 pieces) are stored on the 11th surface of the three-dimensional LUT, and each table corresponds to the signals A _{0 to} A ₁₀ .

The interpolation calculation unit 105 uses the values of these input signals to perform the calculation represented by the following equation (4).

[0031]

[Equation 4]

In equation (4), S _i of the interpolation function is equal to S _{i in} equation (1), and the element of the quadratic interpolation is the second
It is the part from the fourth term to the fourth term.

(Second Embodiment) FIG. 3 shows the configuration of the second embodiment of the present invention. In the figure, 1 of 101-103
The dimensional LUT and the address generator of 104 are the same as the parts with the same reference numerals in FIG. 1 of the first embodiment.

Further, the linear operation unit for performing the primary interpolation operation of 1 is the same as the part with the same reference numeral in FIG.

Reference numeral 301 denotes a three-dimensional LUT, which is composed of a table 8 surface including all grid point values. Also, 3
Reference numeral 02 is an 8-point data latch, and 303 is a 3-point data latch. Reference numeral 304 is a non-linear calculation unit that performs two-dimensional interpolation calculation, 305 is a switch, 306 is an adder, and 307 is a selector.

In this embodiment, two operation modes are switched and used by opening / closing the switch 305 and operating the selector 307. That is, when the operating frequency of the system is slow, the data is read from the LUT 301 twice to enable the quadratic interpolation. On the other hand, when the operating frequency of the system is fast, the data is read from the LUT 301 by 1 time.
Ordinary linear interpolation calculation is performed by limiting the number of times. Below, these 2
Each case will be described.

(1) Quadratic interpolation calculation mode In the first operation cycle, among the data φ _{0 to} φ ₁₀ obtained through the LUT 301 from the address signals A _{0 to} A ₁₀ output from the address generator 104, Data of 8 points of φ _{0 to} φ ₇ are selected by the selector 307, and data latch 3
It is stored in 02. Similarly, in the second operation cycle, data φ ₀ to φ ₁₀ to φ ₈ obtained from the LUT 301 are similarly obtained.
The data of three points of φ ₁₀ are selected by the selector 307 and stored in the data latch 303.

In the final operation cycle, the linear interpolation calculation unit 1 performs the calculation of the equation (1) using the data of the latch 302, and at the same time, the nonlinear interpolation calculation unit 304 performs the data latch 3 operation.
The data of No. 03 is used to perform the operations of the second to fourth terms of the equation (4), and the results of these operations are added by the adder 306 to obtain the output F. At this time, the switch 305 is closed (O
N). The output F thus obtained is (4)
Gives exactly the same result as the expression.

(2) Linear interpolation calculation mode In this mode, the processing of the second operation cycle in the quadratic interpolation calculation mode of the above (1) is omitted, and only the first operation cycle and the final operation cycle are executed. Then, the output F becomes equivalent to the expression (1). At this time, the switch 305 is open (OFF).

As described above, by dividing the operation mode into two, the same effect as that of the first embodiment can be obtained and the memory capacity can be further reduced.

[0041]

As described above, according to the present invention,
It is possible to suppress an increase in cost due to an increase in memory and improve the calculation accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a graph for explaining mapping of LUT 106 in FIG.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a diagram for explaining a partial interpolation space in an input space.

FIG. 6 is a diagram showing an interpolation function used for interpolation calculation in 8-point interpolation.

[Explanation of symbols]

1 Linear Interpolation Operation Unit (Interpolation Operation Block) 101 to 103 One-dimensional LUT (Lookup Table) 104 Address Generator 105 Interpolation Operation Unit 106, 301 Three-dimensional LUT 302, 303 Data Latch 304 Nonlinear Interpolation Operation Unit 305 Switch 306 Adder 307 Selector

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Claims (5)

[Claims] 1. A data conversion device for performing a data conversion process using a lookup table and interpolation calculation means, wherein the data conversion device has a quadratic interpolation calculation means as the interpolation calculation means. 2. The quadratic interpolation calculation of the quadratic interpolation calculation means is performed by using eleven grid points in a three-dimensional space obtained from a three-dimensional lookup table. Data converter. 3. The data conversion apparatus according to claim 1, wherein the quadratic interpolation calculation of the quadratic interpolation calculation means is performed by being divided into a linear interpolation calculation and a non-linear interpolation calculation. 4. The data conversion apparatus according to claim 3, further comprising switching means for switching between the linear interpolation calculation and the non-linear interpolation calculation according to the operating frequency of the system. 5. The data conversion device according to claim 1, wherein a color conversion process of a digital color printer is performed as the data conversion process.