JP3364813B2 - Color inverse conversion processing device and video signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverse color conversion processing device and a video signal processing device.

[0002]

2. Description of the Related Art FIG. 16 is a block circuit diagram showing a conventional color conversion processing apparatus and color inverse conversion processing apparatus. In the figure, 96 and 97 are three-dimensional lookup tables (hereinafter,
"LUT").

The operation will be described. NTSC (National Television System Commit)
tee) method, PAL (Phase Alternation by Line) method, SECA
There is an M (Sequential a Memoire) system. For example, a method of converting an RGB color space signal in the NTSC system into a CIE 1976 L ^* a ^* b ^* uniform perceptual color space signal will be described below. CIE1
The 976 L ^* a ^* b ^* uniform perceptual color space is defined by the International Commission on Illumination (Commis
sion Internationalede l'Eclairage (CIE) is 197
It is a color space with a perceptually nearly uniform rate recommended in 6 years. First, as shown in the following equations (1), (2), and (3), the NTSC RGB signal is converted into XYZ. X = 0.6069R + 0.1739G + 0.209B …… (1) Y = 0.2991R + 0.5870G + 0.1139B …… (2) Z = 0.0000R + 0.0660G + 1.1169B …… (3)

The reference white color in the NTSC system is a C light source (chromaticity coordinate x = 0.3101, y = 0.3163: correlated color temperature of about 6770K),
The tristimulus value X ₀ Y ₀ Z ₀ of the C light source is expressed by _equations (4), (5), and (6) when Y ₀ is 100%. X ₀ = 98.072 …… (4) Y ₀ ＝ 100.000 …… (5) Z ₀ ＝ 118.225 …… (6)

L ^* a ^* b ^* with XYZ as a reference white light source as C light source
Convert to. ^{L * = 116 (Y / Y} 0) 1/3 -16: Y / Y 0> 0.008856 ...... (7) L * = 903.29 (Y / Y 0): Y / Y 0 <= 0.008856 ...... (8) ^{a * = 500 (X'-Y} ') ...... (9) b * = 200 (Y'-Z') ...... (10) X '= (X / X 0) 1/3: X / X 0> 0.008856 …… (11) X '= 7.787 (X / X ₀ ) +16/116: X / X ₀ <= 0.008856 …… (12) Y' = (Y / Y ₀ ) ^1/3 : Y / Y ₀ > 0.008856 …… (13) Y '＝ 7.787 (Y / Y ₀ ) +16/116 ： Y / Y ₀ <= 0.008856 …… (14) Z' ＝ (Z / Z ₀ ) ^1/3 ： Z / Z ₀ > 0.008856 …… (15) Z '＝ 7.787 (Z / Z ₀ ) +16/116 ： Z / Z ₀ <= 0.008856 …… (16)

From the conversion formulas (1) to (16),
The RGB color space signal in the NTSC system is converted to CIE 1976 L ^* a
^* b ^* Performs non-linear conversion into a signal in the uniform perceptual color space. Then CIE
The method of inversely converting the 1976 L ^* a ^* b ^* uniform perceptual color space into an RGB color space signal is shown below. First, as shown in the following equations (17) to (20), L ^{* using the} reference white light as the C light source ^.
Convert a ^* b ^* to XYZ. X = X ₀ {(L ^* + 16) / 116 + a ^* / 500} ³ (17) Y = Y ₀ {(L ^* + 16) / 116} ³ : L ^* > = 8.0 ...... (18 ) Y = Y ₀ · L ^* /903.29: L ^* <8.0 …… (19) Z = Z ₀ {(L ^* +16) / 116-b ^* / 200} ³ …… (20)

XYZ is converted into an NTSC type RGB signal. R = 1.9106X-0.5335Y-0.2893Z (21) G = -0.9848X + 1.9983Y-0.0266Z (22) B = 0.0582X-0.1181Y + 0.8969Z (23)

From the conversion formulas (1) to (16), L ^* , a ^* , and b ^* for all R, G, and B are calculated, and the converted values are stored in the three-dimensional LUT 96. From equation (17), (2
From the inverse transformation of equation 3), all R, G, for L ^* , a ^* , b ^*
B is calculated and the converted value is stored in the three-dimensional LUT 97.
FIG. 17 shows a conceptual diagram of the three-dimensional LUT 96. Three-dimensional LU
The output signal L ^* (Ri, Gi, Bi), a ^* (Ri, Gi, Bi), b ^* (Ri, Gi, Bi) located at the lattice point of the input signal Ri, Gi, Bi is obtained by T96. . FIG. 18 shows a conceptual diagram of the three-dimensional LUT 97. The 3-dimensional LUT97, the input signal Li ^*, ai ^*, bi ^* output signal located at a lattice point ^{R (Li *, ai *,} bi *), G (Li *, ai *, bi *), B
(Li ^* , ai ^* , bi ^* ) is obtained.

Three-dimensional L used for these forward and reverse transformations
The greater the number of UT grid points, the higher the conversion accuracy. The method of directly obtaining the output signals for all the input signals by the LUT is called the direct mapping method. By using the direct mapping method, it is possible to perform high-speed and high-precision conversion regardless of any complicated conversion method.

However, for example, if the input signals R, G, B and the output signals L ^* , a ^* , b ^* are each 8 bits, the capacity of the three-dimensional LUT 96 used for this normal conversion becomes 384 Mbits, and a large scale memory is required. It is not practical because it requires means. In general, a method is used in which several nearby values are obtained by a direct mapping method using an upper signal of an input signal and an output signal is interpolated from several neighboring values using a lower signal of the input signal.

Another conventional technique will be described. FIG. 19
`` ITEJ Technical Report Vol.16, No.31, pp.25-3
FIG. 10 is a block circuit diagram showing another conventional color conversion processing device shown in “0”. In the figure, 30 is a three-dimensional LUT, 3
Reference numeral 1 is an interpolation coefficient generation circuit, 32 to 39 are multipliers, 46 is a 15-bit shift circuit, and 98 is an addition circuit.

The upper signals Rn, Gn, Bn of the input signals Ri, Gi, Bi are set to 3
Input to the dimension LUT 30. Also, the lower signals of Ri, Gi, Bi
The r, g and b are input to the interpolation coefficient generation circuit 31. Three-dimensional LU
The outputs d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ of T30 are respectively multiplied by a multiplier 3
Input to 2, 33, 34, 35, 36, 37, 38, 39. Output of the interpolation coefficient generation circuit 31 w ₀ , w ₁ , w ₂ , w ₃ , w ₄ , w ₅ ,
w ₆ and w ₇ are respectively multiplied by multipliers 32, 33, 34, 35, 36, 3
Input to 7,38,39. Multipliers 32, 33, 34,
The outputs of 35, 36, 37, 38, 39 are input to the adder circuit 98. The output of the adder circuit 98 is input to the 15-bit shift circuit 46, and the output d is obtained.

The operation will be described. Input signal Ri, Gi, Bi
Are m-bit signals, and upper n bits of the input signals Ri, Gi, Bi are Rn, Gn, Bn, respectively. However, m> n. Three
Eight-point unit cubic lattice (Rn, Gn, Bn), (Rn + Dn, Gn, Bn), (Rn + Dn, Gn, Bn + D) near the input signals Ri, Gi, Bi from the dimension LUT 30
n), (Rn, Gn, Bn + Dn), (Rn, Gn + Dn, Bn), (Rn + Dn, Gn + Dn, Bn), (R
n + Dn, Gn + Dn, Bn + Dn), located at (Rn, Gn + Dn, Bn + Dn) d ₀ , d ₁ ,
Get d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ . However, Dn is a three-dimensional LUT
The length of one side of the 30 unit cubic lattice is 2 ^mn .

Next, the interpolation method will be described. As shown in FIG. 20, the output signals located in the unit cubic lattice of eight points near the input signals Ri, Gi, Bi are d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ The lower m-n bits of the input signals Ri, Gi, Bi are respectively r, g,
b, the length of one side of the unit cubic lattice is Dn. Input signal Ri,
3 about R axis direction, G axis direction and B axis direction with Gi and Bi as the center
The volume of a rectangular parallelepiped that is divided into eight parts in each direction is w ₀ , w ₁ , w ₂ , w ₃ ,
and _{w 4, w 5, w 6} , w 7. The output signal d for the input signals Ri, Gi, Bi is interpolated as shown in Expression (24). d = d ₀ w ₀ + d ₁ w ₁ + d ₂ w ₂ + d ₃ w ₃ + d ₄ w ₄ + d ₅ w ₅ + d ₆ w ₆ + d ₇ w ₇ (24) This interpolation method Then, each of L ^* , a ^* , and b ^* is interpolated.

The same applies to the inverse transformation. FIG. 21 shows
It is a block circuit diagram which shows a color reverse conversion processing apparatus. In the figure, 1 is a three-dimensional LUT, 2 is an interpolation coefficient generation circuit, 3 to 10 are multipliers, 17 is a 15-bit shift circuit, and 99 is an addition circuit.

Upper signal Ln ^* , an ^* , b of input signals Li ^* , ai ^* , bi ^*
Input n ^* into the three-dimensional LUT1. Further, the low order signals l ^* , a ^* , b ^* of Li ^* , ai ^* , bi ^* are input to the interpolation coefficient generation circuit 2. Three
The outputs p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇ of the dimensional LUT ₁ are input to the multipliers ₃ , ₄ , ₅ , ₆ , ₇ , 8, 9, 10, respectively. The outputs v ₀ , v ₁ , v ₂ , v ₃ , v ₄ , v ₅ , v ₆ , v ₇ of the interpolation coefficient generation circuit 2 are respectively applied to the multipliers ₃ , ₄ , ₅ , ₆ , ₇ , 8, 9, 10. input. The outputs of the multipliers 3, 4, 5, 6, 7, 8, 9, 10 are input to the adder circuit 99. The output of the adder circuit 99 is input to the 15-bit shift circuit 17, and the output p is obtained.

The operation will be described. Input signal Li ^* , ai ^* ,
Each m-bit signal bi ^*, the input signal Li ^*, ai ^*, each Ln ^* the upper n bits of bi ^*, an ^*, and bn ^*. However, m> n
Is. Eight-point unit cubic lattice (Ln ^* , an ^* , bn ^* ), (Ln ^* , an ^* + Dn, bn) near the input signals Li ^* , ai ^* , bi ^* from the three-dimensional LUT1
^* ), (Ln ^* , an ^* + Dn, bn ^* + Dn), (Ln ^* , an ^* , bn ^* + Dn), (Ln ^* + Dn, an
^* , bn ^* ), (Ln ^* + Dn, an ^* + Dn, bn ^* ), (Ln ^* + Dn, an ^* + Dn, bn ^* + Dn),
Located at (Ln ^* + Dn, an ^* , bn ^* + Dn) p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ ,
get p ₇ . However, Dn is 2 ^mn, which is the length of one side of the unit cubic lattice of the three-dimensional LUT 1.

Next, the interpolation method will be described. As shown in FIG. 22, the input signal ^{Li *, ai *, bi *} p 0 the output signal is located in the unit cubic lattice of eight points in the vicinity _{of, p 1, p 2, p} 3, p 4, p 5, p ₆ , p ₇
And The lower mn bits of the input signals Li ^* , ai ^* , and bi ^* are respectively l ^* , a ^* , and b ^* , and the length of one side of the unit cubic lattice is Dn.
Input signals Li ^*, ai ^*, L ^* axial direction about the bi ^*, a ^* axis direction, b ^* 8 divided rectangular parallelepiped volume with 3 axis direction, each _{v 0, v 1, v 2} , v Let ₃ , v ₄ , v ₅ , v ₆ , v ₇ . Input signal Li ^* , ai ^* , b
The output signal p for i ^* is interpolated as in equation (25). p = p ₀ v ₀ + p ₁ v ₁ + p ₂ v ₂ + p ₃ v ₃ + p ₄ v ₄ + p ₅ v ₅ + p ₆ v ₆ + p ₇ v ₇ (25)

[0019]

Since the conventional color conversion processing device and color inverse conversion processing device are configured as described above, it is possible to perform color conversion in real time or at a speed equivalent thereto. There was a problem.

First, if output signals for all input signals are obtained by the direct mapping method, highly accurate conversion is possible, but a large capacity LUT is required.

Second, in order to reduce the capacity of the LUT,
Using the upper signal of the input signal, several neighboring values are obtained by the direct mapping method, and by using the lower signal of the input signal,
In the method of interpolating the output signal from several neighboring values, the conversion accuracy is high in 8-point interpolation using 8-point unit cubic lattice, but many multipliers are required and the circuit scale becomes large.
Further, if the circuit scale is reduced by reducing the number of data used for interpolation such as 6-point interpolation, 5-point interpolation, and 4-point interpolation, the number of multipliers decreases but the conversion accuracy also decreases.

Further, in the conventional video signal processing apparatus, for example, in the image represented by the RGB signal, the aperture correction is performed on each of R, G, B, or the RGB signal is subjected to a matrix operation to obtain a luminance signal Y, an RY color difference signal, Aperture correction is performed by converting to a BY color difference signal and controlling the gains of the brightness signal Y, the RY color difference signal, and the BY color difference signal in the high frequency portion of the brightness signal Y. However, the RGB color space is a color space of mixed colors and is not a uniform space for human visual characteristics, and has the following problems.

First, in the former method, aperture correction is performed so that the gains of R, G, and B signals are changed at a constant ratio in the high-frequency portion of the image represented by RGB signals. The color balance is lost and the color reproducibility is deteriorated.

Second, in the latter method, the luminance signals Y and R are
By performing aperture correction on the −Y color difference signal and the BY color difference signal, it is possible to enhance the brightness and saturation separately, but since the space is not a uniform perceptual color space, color reproducibility deteriorates.

The color reversal conversion processing device of the present invention is made to solve the above-mentioned problems, and it is possible to perform color conversion with the same accuracy as the conventional one in a small circuit scale at real time or at a speed corresponding to it. With the goal.

Further, the video signal processing device of the present invention is made in order to solve the above-mentioned problems, and human visual characteristics such as CIE 1976 L ^* a ^* b ^* uniform perceptual color space from the RGB color space. Converted to a uniform perceptual color space that is uniform for L ^* , a
By performing aperture correction on ^* and b ^* respectively,
The purpose is not to disturb the balance of lightness and saturation and to reduce the color reproducibility.

[0027]

According to a first aspect of the present invention, there is provided an inverse color conversion processing apparatus which uses a first three-dimensional color space represented by first, second and third color signals as a fourth and a fifth color space. A color inverse conversion processing device for inversely converting a color signal nonlinearly converted into a second three-dimensional color space represented by a sixth color signal into first, second and third color signals, The fifth and sixth color signals are respectively denoted by m (m
Is a natural number) bit and is input as a digital signal of 8 bits in the vicinity of the first, second and third color signals corresponding to the input signal.
Storage means for outputting the first, second, and third color signals that are assumed to be located or located in the unit cubic lattice of points, and for multiplying the first, second, and third color signals at the eight points Interpolation coefficient generating means for generating an interpolation coefficient of
First, second, and third color signals that include a fifth color signal and are located in a unit plane lattice of four points when the sixth color signal has upper n (n is a natural number and m> n) bits And means for outputting a first interpolated signal obtained by multiplying and adding each of the interpolation coefficients,
Similarly, the first, second, and third positions, which include m-bit fourth and fifth color signals and are located on the unit plane lattice of four points when the sixth color signal is increased by 1 for the upper n bits. Means for outputting a second interpolated signal obtained by multiplying each of the color signals by the above interpolation coefficient and adding them together, and a first interpolated signal obtained by subtracting the sixth color signal for the lower mn bits from 2 ^n. An interpolation processing unit for calculating the first, second, and third color signals by multiplying and adding the product of the sixth color signal of the lower mn bits to the second interpolation signal Is.

According to a second aspect of the present invention, there is provided an inverse color conversion processing device, wherein a unit plane of which side is 2 ^mn bits is used as a fourth color centering on the fourth and fifth color signals of lower m−n bits. 4 when divided into 4 in the axial direction of the signal and the axial direction of the fifth color signal
An interpolation coefficient generating means for outputting the area of the plane as an interpolation coefficient is provided.

The color inverse conversion processing device according to the third aspect of the present invention inputs the fourth and fifth color signals of the lower mn bits and is required to calculate the first interpolation signal and the second interpolation signal. The interpolation coefficient generation means for outputting the four interpolation coefficients is composed of four storage means.

A color inverse conversion processing device according to a fourth aspect of the present invention inputs the fourth and fifth color signals of the lower mn bits and is necessary for calculating the first interpolation signal and the second interpolation signal. Storage means for outputting one of the four interpolation coefficients, and interpolation coefficient generation means for calculating the other three interpolation coefficients from the output signal of the storage means, the plurality of adders, and the plurality of bit shift circuits. Be prepared.

According to a fifth aspect of the present invention, there is provided an inverse color conversion processing apparatus, which outputs first, fourth and fifth color signals and outputs first,
One side of the unit cubic lattice at the central portion of the storage means for storing the second and third color signals is set to 2 ^mn, and one side of the unit cubic lattice at the end portion of the storage means is 2 ^{m-n + p} (p Is a natural number and n> p).

According to a sixth aspect of the present invention, there is provided a video signal processing device which comprises a fourth color signal and a fifth color signal having color information in a three-dimensional color space represented by the first, second and third color signals. , A video signal processing device for converting into a three-dimensional uniform perceptual color space of a color-developing system represented by a sixth color signal having lightness information to perform aperture correction, the first, second and third color signals Are respectively inputted as m-bit digital signals, and the fourth, fifth, and sixth colors are located in the unit cubic lattice of eight points near the fourth, fifth, and sixth color signals corresponding to the input signals. A memory means for outputting a signal, an interpolation coefficient generation means for generating an interpolation coefficient for multiplying the eight-point fourth, fifth, and sixth color signals, and m-bit first and second color signals 4th, 5th, and 4th, which are included in the unit plane lattice of 4 points when the third color signal includes the upper n bits. Means for outputting a first interpolated signal obtained by multiplying each of the color signals by the above interpolation coefficient and adding them together, and similarly including m-bit first and second color signals, wherein the third color signal is the upper n bits. Means for outputting a second interpolated signal obtained by multiplying each of the fourth, fifth, and sixth color signals located in the unit plane lattice of four points when 1 is added to the minute by multiplying by the interpolation coefficient, and Multiply the first interpolation signal by 2 ⁿ minus the third color signal for the lower mn bits, and multiply the second interpolation signal by the third color signal for the lower mn bits. In addition, interpolation processing means for calculating the fourth, fifth, and sixth color signals, first gain control means for controlling the gain of the high-frequency component of the sixth color signal in an arbitrary pixel, and in that pixel Second gain control means for controlling the gains of the fourth and fifth color signals, and the gain-controlled fourth, fifth and fifth gain control means. In order to inversely convert the six color signals into the first, second, and third color signals, the storage means, the interpolation coefficient generation means, and the interpolation processing means having the same configuration as described above are provided.

According to a seventh aspect of the present invention, in the video signal processing device, the first gain control means for controlling the gain of the high frequency component of the sixth color signal in any pixel, and the fourth and fifth colors in the pixel. The second gain control means for controlling the gain of the signal is composed of a plurality of adders, a plurality of multipliers, and a plurality of 1-pixel delay circuits.

According to the eighth aspect of the present invention, in the video signal processing device, the first gain control means for controlling the gain of the high frequency component of the sixth color signal in any pixel, and the fourth and fifth colors in the pixel. The second gain control means for controlling the gain of the signal is constituted by a plurality of adders, a plurality of multipliers and a plurality of horizontal scanning period delay circuits.

[0035]

According to the first aspect of the present invention, the memory means of the color inverse conversion processing device uses the fourth, fifth and sixth color signals representing the three-dimensional color space as digital signals of m (m is a natural number) bits. The first, second, and third color signals that are input or are assumed to be located or located on the unit cubic lattice of eight points near the first, second, and third color signals corresponding to the input signal Output,
The interpolation coefficient generating means generates an interpolation coefficient for multiplying the eight-point first, second and third color signals, and the means for outputting the first interpolation signal is an m-bit fourth and fifth bit. A first color signal, a second color signal, and a third color signal, which include a color signal and are located in a unit plane lattice of four points when the sixth color signal is for upper n (n is a natural number and m> n) bits, The means for outputting the first interpolation signal obtained by multiplying and adding the interpolation coefficient and outputting the second interpolation signal also include m-bit fourth and fifth color signals,
A sixth color signal is obtained by multiplying the first, second and third color signals located in the unit plane lattice of four points by adding 1 to the upper n bits and multiplying them by the interpolation coefficient. 2 interpolation signals are output, and the interpolation processing means outputs 2 ⁿ to the first interpolation signals.
Is multiplied by a value obtained by subtracting the sixth color signal for the lower mn bits from the above, and the second interpolation signal is multiplied by the sixth signal for the lower mn bits.
Since the first, second, and third color signals are calculated by adding the color signals multiplied by, the color conversion is realized with a small circuit scale in real time or at a speed equivalent thereto, and color conversion by linear interpolation is performed. It is possible to improve accuracy.

The interpolation coefficient generating means of the color inverse conversion processing device according to the second aspect of the present invention comprises the fourth and fifth lower mn bits.
The unit plane of which the side is 2 ^mn bits centering on the color signal of is, in the axial direction of the fourth color signal and the axial direction of the fifth color signal,
Since the areas of the four planes in the case of four divisions are output as the interpolation coefficient, it is possible to perform highly accurate color conversion by the small-capacity storage means and interpolation processing means, and it is possible to reduce the circuit scale.

The interpolation coefficient generating means of the color inverse conversion processing device according to the third aspect of the present invention is the fourth and fifth lower mn bits.
The color signal is input and the four interpolation means required to calculate the first interpolation signal and the second interpolation signal are output. Therefore, the number of multipliers is reduced and the circuit scale is reduced. It is possible to make it smaller.

The interpolation coefficient generating means of the color inverse conversion processing device according to the fourth aspect of the present invention comprises the fourth and fifth lower mn bits.
Of the four interpolation coefficients necessary for the calculation of the first interpolation signal and the second interpolation signal by the storage means, and outputs one interpolation coefficient, and the output signal of the storage means and a plurality of adders. Since the other three interpolation coefficients are calculated from the plurality of bit shift circuits, the number of multipliers can be reduced and the circuit scale can be reduced.

According to a fifth aspect of the present invention, in the storage means of the color inverse conversion processing device, one side of the central unit cubic lattice is 2 ^mn and one side of the end unit cubic lattice is 2 ^{m-n + p.} Since (p is a natural number, n> p), it is possible to improve the color conversion accuracy with respect to the capacity of the storage unit.

The storage means of the video signal processing apparatus according to the present invention inputs the first, second and third color signals representing the three-dimensional color space as m-bit digital signals,
The fourth, fifth, and sixth color signals located in the unit cubic lattice of eight points near the fourth, fifth, and sixth color signals corresponding to the input signal are output, and the interpolation coefficient generating means, Fourth of the 8 points,
Generate interpolation coefficients for multiplying the fifth and sixth color signals,
The means for outputting the first interpolation signal is composed of m-bit first and second bits.
4th, 5th, and 6th color signals including the above color signals and located in the unit plane lattice of 4 points in the case where the 3rd color signal corresponds to the upper n bits, and are multiplied by the interpolation coefficient and added. The means for outputting the first interpolation signal and the second interpolation signal also include m-bit first and second color signals, and the third color signal is obtained by adding 1 to the upper n bits. In this case, the fourth, fifth, and sixth color signals located on the unit plane grid of four points are multiplied by the interpolation coefficients and added, and a second interpolation signal is output. ²ⁿ to lower ^{order mn in the} interpolation signal
The third, fourth, and fifth bits of the bit are subtracted from each other, and the second interpolated signal is multiplied by the third color signal of the lower mn bits, thereby adding the fourth, fifth, and fifth signals. The first gain control means controls the gain of the high frequency component of the sixth color signal in an arbitrary pixel, and the second gain control means calculates the fourth color signal in the pixel. The gain of the signal is controlled, and the fourth, fifth, and sixth color signals whose gains are controlled by the storage unit, the interpolation coefficient generation unit, and the interpolation processing unit having the same configuration as described above are first, second, and third. Since it is inversely converted to the color signal of, the balance of the first, second, and third color signals is not disturbed,
It is possible to perform aperture correction without degrading color reproducibility.

The first gain control means for controlling the gain of the high frequency component of the sixth color signal in any pixel of the video signal processing device according to the seventh aspect of the present invention, and the fourth gain control means in the pixel,
The second gain control means for controlling the gain of the fifth color signal is composed of a plurality of adders, a plurality of multipliers, and a plurality of 1-pixel delay circuits, so that it is possible to perform horizontal aperture correction. Becomes

A first gain control means for controlling the gain of the high frequency component of the sixth color signal in an arbitrary pixel of the video signal processing device according to the eighth aspect of the invention, and a fourth gain control means in the pixel,
Since the second gain control means for controlling the gain of the fifth color signal is composed of a plurality of adders, a plurality of multipliers and a plurality of horizontal scanning period delay circuits, it is necessary to perform vertical aperture correction. Is possible.

[0043]

【Example】

Example 1. First Embodiment FIG. 1 is a block circuit diagram showing a color inverse conversion processing device according to a first embodiment of the present invention. In the figure, 1 is a three-dimensional LUT in which the conversion value is expanded to 10 bits, 2 is an interpolation coefficient generation circuit, 3 to 12 are multipliers, 13 and 14 are addition circuits, 15 is an adder, 16 is a bit inversion circuit, 17 Is 1
It is a 5-bit shift circuit.

Upper signal Ln ^* , an ^* , b of input signals Li ^* , ai ^* , bi ^*
Input n ^* into the three-dimensional LUT1. The lower signals a ^* and b ^* of ai ^* and bi ^* are input to the interpolation coefficient generation circuit 2, and the lower signal l ^* of Li ^* is input to the bit inverting circuit 16. Three-dimensional LUT1
Output p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇ respectively into multipliers 3, 4,
Input to 5,6,7,8,9,10. The outputs T ₀ , T ₁ , T ₂ , T ₃ of the interpolation coefficient generation circuit 2 are input to the multipliers 3, 4, 5, 6 and 7, 8, 9, 10, respectively. Multipliers 3, 4, 5, 6
Input to the adder circuit 13, and the multipliers 7, 8, 9, 1
The output of 0 is input to the adder circuit 14. Bit inversion circuit 1
Output pt output and the adding circuit 13 for 6 input to the multiplier 11, receives the output pt 'of Li ^* lower signal l ^* and the adding circuit 14 to the multiplier 12. The outputs of the two multipliers 11 and 12 are input to the adder 15. The output of the adder 15 is input to the 15-bit shift circuit 17, and the output p is obtained.

The operation will be described. Input signal Li ^* , ai ^* ,
Each bi ^* is 8 bits. Input signals Li ^*, ai ^*, bi ^* of each upper 3 bits Ln ^*, an ^*, enter the bn ^* on the three-dimensional LUT 1, the input signal Li ^*, ai ^*, the unit cubic eight points in the vicinity of bi ^* lattice
(Ln ^* , an ^* , bn ^* ), (Ln ^* , an ^* + Dn, bn ^* ), (Ln ^* , an ^* + Dn, bn ^* + D
n), (Ln ^* , an ^* , bn ^* + Dn), (Ln ^* + Dn, an ^* , bn ^* ), (Ln ^* + Dn, an ^* + D
n, bn ^* ), (Ln ^* + Dn, an ^* + Dn, bn ^* + Dn), (Ln ^* + Dn, an ^* , bn ^* + Dn)
The output signals p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p _{7 located at} are obtained.
However, Dn is 2 ⁵ which is the length of one side of the unit cubic lattice of the three-dimensional LUT 1. Also, the lower 5 bits a ^* and b ^* of the input signals ai ^* and bi ^* are input to the interpolation coefficient generation circuit 2, and the interpolation coefficients T ₀ , T ₁ , T ₂ and T ₃ as shown in FIG. obtain. FIG. 2 shows an upper surface (unit plane composed of p ₄ , p ₅ , p ₆ , p ₇ points) and a lower surface (unit plane composed of p ₀ , p ₁ , p ₂ , p ₃ points) of a unit cubic lattice of the three-dimensional LUT ₁ . ) And the position of the input signal Li ^{* on} the L ^* axis. T ₀ , T ₁ , T ₂ , T ₃ are unit planes each having ²⁵ bits on one side with a point located at a ^* , b ^* for the lower 5 bits of the input signals ai ^* , bi ^* as a center. Interpolation coefficient corresponding to 4 planes when divided into 4 in the ^* axis direction and b ^* axis direction. T ₀ ＝ (Dn-a ^* ) ・ (Dn-b ^* ) …… (26) T ₁ ＝ a ^*・ (Dn-b ^* ) …… (27) T ₂ ＝ a ^*・ b ^* …… (28 ) T ₃ = (Dn-a ^* ) ・ b ^* …… (29)

FIG. 3 is a block circuit diagram showing the configuration of the interpolation coefficient generating circuit 2. In the figure, 18 and 19 are bit inversion circuits, and 20 to 23 are multipliers. Since Dn is the length of one side of the unit cubic lattice, when the upper 3 bits of the 8 bits of the input signal are input to the 3D LUT 1, Dn
= 2 ⁵ . Therefore, Dn-r is the inversion of all bits of r. Similarly, Dn-b is also an inversion of all bits of b. Using the above, the bit inversion circuit 1
The operations of the equations (26), (27), (28), and (29) can be realized by the eight and nineteen and the multipliers 20, 21, 22, and 23.

The first interpolation signal pt is calculated by using the multipliers 3, 4, 5, 6 and the adder circuit 13. In addition, the multiplier 7,
The second interpolated signal p
Calculate t '. The respective calculation formulas are formulas (30) and (3
It is represented by 1). pt = p ₀ T ₀ + p ₁ T ₁ + p ₂ T ₂ + p ₃ T ₃ (30) pt '= p ₄ T ₀ + p ₅ T ₁ + p ₆ T ₂ + p ₇ T ₃ ...... (31) In the equations (30) and (31), the signals at the respective lattice points are multiplied by the areas located point-symmetrically with respect to the input signals ai ^* and bi ^* as interpolation coefficients to obtain a ^* and b. ^* Two interpolation signals on the plane are calculated. By interpolating these two interpolation signals pt, pt 'on the L ^* axis, 3
Realize dimensional interpolation. When the length of one side of the unit cubic lattice is Dn, the output signal p is calculated as in Expression (32). p = {pt '· l ^* + pt · (Dn-l ^* )} / Dn ³ …… (32)

However, l ^* is the lower 5 bits of the input signal Li ^* , and is divided by Dn ³ in order to normalize the interpolation coefficient to 1. Here, Dn ³ is to become a 2 ^15, in fact can be calculated by lowering 15 bits of digits. The calculation of Expression (32) is realized by the multipliers 11 and 12, the adder 15, and the bit inverting circuit 16. The lower 5 bits l ^* of the input signal Li ^* are input to the multiplier 12 and the bit inverting circuit 16.
The first interpolation signal pt and the second interpolation signal pt ′ are respectively multiplied by a multiplier 11,
Enter in 12. The output signals of the multipliers 11 and 12 are input to the adder 15, and the output of the adder 15 is digit-reduced by 15 bits by the 15-bit shift circuit 17 to obtain the output signal p. Interpolation processing of R, G and B is performed by the same calculation method.

The inverse transform needs to restore the positively transformed CIE 1976 L ^* a ^* b ^* uniform perceptual color space to the original RGB color space, and a three-dimensional LUT for inverse transform that completely includes the original RGB color space. Need. Therefore, the three-dimensional LUT for inverse transformation includes negative R, G, B (imaginary color that does not actually exist) and R, G, B exceeding the maximum value. When the number of grid points of the three-dimensional LUT for the input value is sufficiently large, the color conversion accuracy is greatly affected by any value converted to a color that does not exist in the original RGB color space. Because there is no
Negative R, G, B is rounded to 0, and R, G, B exceeding the maximum value are rounded to the maximum value. However, when the number of grid points of the three-dimensional LUT for the input value is small and simple linear interpolation is performed, rounding the conversion value to a color that does not exist in the original RGB color space to 0 or the maximum value increases the color conversion accuracy. Influence.

For example, consider the case where 8-bit L ^* , a ^* , b ^* is inversely converted into 8-bit R, G, B. 33 There is little deterioration of color conversion accuracy if the inverse conversion is performed by using 3D LUT that has ³ grid points and the conversion value of each grid point is rounded to 8 bits with 0 and 255 (maximum value) and linear interpolation. , 5 In case of ³ grid points, the color conversion accuracy deteriorates significantly. Such deterioration of the color conversion accuracy occurs when several conversion values used for interpolation include points existing in the original RGB color space and points not existing in the original RGB color space. This is because the linear interpolation is performed using the converted value rounded with a value of 0 to 255, and this is because an error occurs between the originally obtained value and the interpolated value. When the number of lattice points of the three-dimensional LUT is sufficiently large, such an error is unlikely to occur, and the error itself is small, so that there are few problems. However, if the number of grid points is reduced in order to reduce the circuit scale, an error is more likely to occur and the error itself becomes large, which is a problem.

In the present invention, negative R, G, B (imaginary colors that do not actually exist) or R, G, B exceeding the maximum value are stored in the three-dimensional LUT as conversion values, and linear interpolation is performed. To improve color conversion accuracy. For example, by expanding the conversion value to 10 bits and storing the values from -512 to +511 in the three-dimensional LUT, it is possible to improve the color conversion accuracy.

Example 2. The configuration of the color inverse conversion processing device according to the second embodiment of the present invention is the same as that of FIG. 1, but the signal processing in the interpolation coefficient generation circuit 2 is different.

The operation will be described. Input signal Li ^* , ai ^* ,
Each bi ^* is 8 bits. Input signals Li ^*, ai ^*, bi ^* of each upper 3 bits Ln ^*, an ^*, enter the bn ^* on the three-dimensional LUT 1, the input signal Li ^*, ai ^*, the unit cubic eight points in the vicinity of bi ^* Output signals p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇ located on the grid are obtained.
Further, the lower 5 bits a ^* and b ^* of the input signals ai ^* and bi ^* are input to the interpolation coefficient generation circuit 2, and the interpolation coefficients T ₀ , T ₁ and T ₂ corresponding to the areas shown in FIG. 2 are input. , Get T ₃ . FIG. 4 is a diagram showing the configuration of the interpolation coefficient generation circuit 2 in this embodiment. 6
Reference numerals 2, 63, 64 and 65 are multiplication circuits, and 66 and 67 are bit inversion circuits. Multiplier circuits 62, 63, 64, 6
5 is the equations (26), (27), (2) for the inputs a ^* and b ^* .
8), T ₀ , T ₁ , T ₂ , T ₃ shown in (29) are output. Input a ^* ,
Since b ^* is 5 bits and outputs T ₀ , T ₁ , T ₂ , T ₃ are 10 bits, if the multiplication circuits 62, 63, 64, and 65 are configured by LUTs, the total capacity is 40 kbits. With this capacity,
The circuit scale is smaller when four multipliers are used. Therefore, the LUT is reduced by dividing the input signal into an upper signal and a lower signal and multiplying them. As shown in the equations (33) and (34), the inputs a ^* and b ^* are connected to the upper signals a _H ^* and b _H ^* and the lower signals a _L.
^When divided into ^* and b _L ^* , T ₂ is represented by the equation (35). a ^* ＝ a _H ^*・ 2 ^K + a _L ^* …… (33) b ^* ＝ b _H ^*・ 2 ^K + b _L ^* …… (34) T ₂ ＝ a ^*・ b ^* ＝ a _H ^* b _H ^*・ 2 ^2K + (a _H ^* b _L ^* + a _L ^* b _H ^* ) ・ 2 ^K + a _L ^* b _L ^*
(35) Since a ^* and b ^* are 5-bit signals, K is set to 3, and a ^* and b ^* are divided into upper 2 bits and lower 3 bits. As a result, 16 LUTs with 3 bits for input and 6 bits for output are required, but the capacity can be reduced to 6k bits. As is clear from the equation (35), twelve adders are required in total, but the circuit scale is smaller than when four multipliers are used.

FIG. 5 shows a multiplication circuit 6 for realizing the equation (35).
4 is the configuration. In the figure, 68, 69, 70, 71
Is an LUT for outputting a 6-bit multiplication result with respect to 3-bit input, 72, 73, and 74 are adders, 75 is a 6-bit shift circuit, and 76 is a 3-bit shift circuit. LUT6
8, 69, 70, 71, a _H ^* b _H ^* , a _H ^* b _L ^* , a _L ^* b _H ^* , a
And calculates the _L ^* b _L ^*. By the adder ^{_{72, a H * b L *}} + a L * b H * is calculated, and a _H ^* b _H ^* was raised six bits of digits by 6-bit shift circuit 75, a by 3-bit shift circuit 76 _H ^* b _L ^*
Carry + a _L ^* b _H ^* by 3 bits and add these signals by adders 73 and 74 to calculate T ₂ . Multiplication circuit 6
2, 63 and 65 can be configured with the same circuit configuration.

In FIG. 1, the output of the interpolation coefficient generation circuit 2
T ₀ , T ₁ , T ₂ , T ₃ are input to the multipliers 3, 4, 5, 6 and the multipliers 7, 8, 9, 10 respectively, and the outputs of these multipliers are added to the adder circuit 13, respectively. It is input to 14, and the first interpolation signal pt and the second interpolation signal pt 'are calculated. Three-dimensional interpolation is performed by interpolating the two interpolation signals on the L ^* axis as shown in Expression (32), and the output signal p is obtained. Interpolation processing for each of R, G, and B is performed by the same calculation method.

Example 3. The configuration of the color inverse conversion processing device according to the third embodiment of the present invention is the same as that of FIG. 1, but the signal processing in the interpolation coefficient generation circuit 2 is different.

The operation will be described. Input signal Li ^* , ai ^* ,
Each bi ^* is 8 bits. Input signals Li ^*, ai ^*, bi ^* of each upper 3 bits Ln ^*, an ^*, enter the bn ^* on the three-dimensional LUT 1, the input signal Li ^*, ai ^*, the unit cubic eight points in the vicinity of bi ^* Output signals p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇ located on the grid are obtained.
Further, the lower 5 bits a ^* and b ^* of the input signals ai ^* and bi ^* are input to the interpolation coefficient generation circuit 2, and the interpolation coefficients T ₀ , T ₁ and T ₂ corresponding to the areas shown in FIG. 2 are input. , Get T ₃ . Only the interpolation coefficient T ₂ calculated by the equation (28) is obtained from the multiplication circuit 64, and the other interpolation coefficients T ₀ , T ₁ , T ₃ are given by T as shown in equations (36), (37), (38). Calculate using ₂ . Since Dn is ²⁵ , the formula (3
6), (37) and (38) can be realized by a combination of an adder and a bit shift circuit. T ₀ = (Dn-a ^* ) ・ (Dn-b ^* ) ＝ Dn ^2- (a ^* + b ^* ) ・ Dn + T ₂ …… (36) T ₁ ＝ a ^*・ (Dn-b ^* ) ＝ a ^*・ Dn-T ₂ …… (37) T ₃ ＝ (Dn-a ^* ) ・ b ^* ＝ b ^*・ Dn-T ₂ …… (38)

FIG. 6 is a diagram showing the configuration of the interpolation coefficient generating circuit 2 in this embodiment. In the figure, 77, 78,
79 is a 5-bit shift circuit, 80, 81, 82, 83,
84 is an adder. The interpolation circuit T ₂ is calculated by the multiplication circuit 64. The a ^* is input to the 5-bit shift circuit 77 to obtain the output a ^* · ²⁵ , and the adder 80 subtracts T ₂ from the a ^* · ²⁵ to obtain the interpolation coefficient T ₁ . Similarly, the 5-bit shift circuit 78 and the adder 81 obtain the interpolation coefficient T ₃ . Also, enter the result of the addition by the adder 84 and a ^* and b ^* in the 5-bit shift circuit 79, (a ^* + b ^*) · 2 ⁵ give, two ¹⁰ and T ₂ are added by the adder 82 From the output of the adder 82 by the adder 83
(a ^* + b ^* ) · ²⁵ is subtracted to obtain the interpolation coefficient T ₀ . Compared to the case where four multipliers are used, the interpolation coefficient generation circuit 2 can be realized by a LUT having a total capacity of 1.5 kbits and eight adders by the above-described calculation method, and the circuit scale can be reduced. It will be possible.

In FIG. 1, the output of the interpolation coefficient generation circuit 2
T ₀ , T ₁ , T ₂ , T ₃ are input to the multipliers 3, 4, 5, 6 and the multipliers 7, 8, 9, 10 respectively, and the outputs of these multipliers are added to the adder circuit 13, respectively. It is input to 14, and the first interpolation signal pt and the second interpolation signal pt 'are calculated. Three-dimensional interpolation is performed by interpolating the two interpolation signals on the L ^* axis as shown in Expression (32), and the output signal p is obtained. Interpolation processing for each of R, G, and B is performed by the same calculation method.

Example 4. FIG. 7 is a block circuit diagram showing a color inverse conversion processing device according to a fourth embodiment of the present invention. In the figure, the same parts as those in FIG. 24 is an L ^* axis LUT, 25 is an a ^* axis LUT, 2
6 is a b ^* axis LUT, and the configuration of the three-dimensional LUT 1 is shown in FIG.
Is different from.

The input signals Li ^* , ai ^* , and bi ^* are respectively LUT for L ^* axis
24, a ^* axis LUT25, b ^* axis LUT26,
Get the output Li ^* ', ai ^* ', bi ^* '. This output signal Li ^* ', a
Input i ^* ', bi ^* ' into the three-dimensional LUT1. Also, ai ^* , bi
^* Lower signal a ^*, and b ^* input to the interpolation coefficient generation circuit 2, Li ^*
The lower-order signal l ^* of is input to the bit inverting circuit 16. The outputs p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇ of the three-dimensional LUT ₁ are input to the multipliers ₃ , ₄ , ₅ , ₆ , ₇ , 8, 9, 10, respectively. . The outputs T ₀ , T ₁ , T ₂ , T ₃ of the interpolation coefficient generation circuit 2 are respectively multiplied by multipliers 3, 4,
Input to 5,6 and 7,8,9,10. Multiplier 3,
The outputs of 4, 5, 6 are input to the adder circuit 13, and the multiplier 7,
The outputs of 8, 9, and 10 are input to the adder circuit 14. Inputs the output pt output and the adding circuit 13 of the bit inversion circuit 16 to the multiplier 11, receives the output pt 'of Li ^* lower signal l ^* and the adding circuit 14 to the multiplier 12. These two multipliers 1
The outputs of 1 and 12 are input to the adder 15. The output of the adder 15 is input to the 15-bit shift circuit 17, and the output p is obtained.

The inverse conversion requires that the CIE 1976 L ^* a ^* b ^* uniform perceptual color space that has been positively converted is returned to the original RGB color space, and a three-dimensional LUT for inverse conversion that completely includes the original RGB color space. Need. Therefore, negative R, G, B (imaginary colors that do not actually exist) are included in the conversion values of this three-dimensional LUT for inverse conversion.
Or R, G, B exceeding the maximum value are included.

For example, consider a three-dimensional LUT in which the maximum value to the minimum value of each of L ^* , a ^* , and b ^* for the original NTSC RGB color space is input. Evenly dividing the number of grid points from the minimum value to the maximum value of each axis into 33, the total number of grid points of the three-dimensional LUT becomes 35937 points, but the number of grid points returning to the original NTSC RGB color space is 8357 points. Is. The remaining 27580 points are points at which negative R, G, B or R, G, B exceeding the maximum value are output.

The conversion value of the portion that does not exist in the original NTSC RGB color space is not directly used,
If the number of grid points of the three-dimensional LUT for the input value is sufficiently large, the possibility of being used for interpolation becomes very low. Therefore, it can be said that the color conversion accuracy is not significantly lowered even if only the number of grid points in the portion including negative R, G, B and R, G, B exceeding the maximum value is reduced. Many colors that do not exist in the original RGB color space of the NTSC system exist in the areas where L ^* , a ^* , and b ^* are close to the maximum value or the minimum value, respectively. By calculating the output value by interpolation, it is possible to improve the color conversion accuracy with respect to the capacity of the three-dimensional LUT.

The 8-bit input signals Li ^* , ai ^* , bi ^* are respectively set to L ^*
Axis LUT 24, a ^* axis LUT 25, b ^* axis LUT 26
To enter. These three LUTs have their input signals
Input signal 32 between 0 and 63 and between 192 and 255
For each, or if the input signal is between 64 and 191, the order from the beginning when the input signal is divided into 16 is output. That is, the input signals Li ^* , ai ^* , bi ^* (input is 0,32,64,80,96,11
Every 2,128,144,160,176,192,224,255 output 0,1,2,3,
4,5,6,7,8,9,10,11,12) are converted into Li ^* ', ai ^* ', bi ^* 'and input to the three-dimensional LUT 1 to obtain converted values. In this way, the number of grid points at the end of the three-dimensional LUT 1 is halved from the center.

CIE 1976 L ^* a ^* b ^{* From} uniform perceptual color space to original N
FIG. 8 shows a conceptual diagram of a three-dimensional LUT 1 for inverse conversion into the TSC method RGB color space. The side of the unit cubic lattice at the center of the three-dimensional LUT 1 in FIG. 8 is 2 ⁴ , and the side of the unit cubic lattice at the end is 2 ⁵ , so that the converted value at the center is large and the converted value at the end is small. is doing. The other signal processing is described in the first embodiment.
Similar to the above, the interpolation coefficient generation and interpolation processing are L ^* , a ^* , b ^*.
The lower signal l ^* , a ^* , b ^{* of} is used. By using such a three-dimensional LUT for inverse conversion, it is possible to improve the color conversion accuracy with respect to the storage capacity.

Example 5. FIG. 9 is a block circuit diagram showing a video signal processing device according to a fifth embodiment of the present invention. In the figure, 27 is a color conversion processing device, 28 is an aperture correction circuit, and 29 is a color inverse conversion processing device.

The input signals Ri, Gi, Bi are input to the color conversion processing device 27, and the output signals Li ^* , ai ^* , bi ^* are obtained. Li ^* , ai ^* , bi ^* are input to the aperture correction circuit 28 to obtain aperture-corrected outputs Li ^* ', ai ^* ', bi ^* '. Ri ^* , ai ^* ', bi ^* ' is input to the inverse color conversion processor 29, and aperture corrected Ri ', G
Get i ', Bi'.

A block circuit diagram of the color conversion processing device 27 is shown in FIG. In the figure, 30 is a three-dimensional LUT, 31 is an interpolation coefficient generation circuit, 32 to 41 are multipliers, and 42 and 43.
Is an adder circuit, 44 is an adder, 45 is a bit inversion circuit, 4
6 is a 15-bit shift circuit.

The operation of the color conversion processing device 27 will be described. The input signals Ri, Gi, Bi are each 8 bits. input signal
Ri, Gi, Bi high-order 3 bits Rn, Gn, Bn for each three-dimensional LUT
Input to 30 and input unit Ri, Gi, Bi near 8 points unit cubic lattice (Rn, Gn, Bn), (Rn + Dn, Gn, Bn), (Rn + Dn, Gn, Bn + Dn) , (R
n, Gn, Bn + Dn), (Rn, Gn + Dn, Bn), (Rn + Dn, Gn + Dn, Bn), (Rn + Dn,
Gn + Dn, Bn + Dn), the output signal d ₀ , located at (Rn, Gn + Dn, Bn + Dn)
Get d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ . Dn is 2 ⁵ by the length of one side of the unit cubic lattice of 3-dimensional LUT 30. Also the input signal
The lower 5 bits r and b of Ri and Bi are interpolated by the interpolation coefficient generation circuit 31.
, And interpolation coefficients S ₀ , S ₁ , S ₂ , S ₃ as shown in FIG. 11 are obtained. FIG. 11 shows an upper surface (a unit plane consisting of d ₄ , d ₅ , d ₆ , d ₇ points) and a lower surface (d ₀ , d ₁ , d of a unit cubic lattice of the three-dimensional LUT 30.
_{2 is} a unit plane consisting of ₂ and d ₃ points) and the position of the input signal Gi on the G axis. S ₀ , S ₁ , S ₂ , S ₃ are input signals R
Interpolation corresponding to 4 planes when a unit plane whose side is ²⁵ bits is divided into 4 in the R-axis direction and the B-axis direction, centering on the point located at the lower 5 bits of i, Bi It is a coefficient. S ₀ = (Dn-r) ・ (Dn-b) …… (39) S ₁ ＝ r ・ (Dn-b) …… (40) S ₂ ＝ r ・ b …… (41) S ₃ ＝ (Dn -r) ・ b …… (42)

FIG. 12 is a diagram showing a block circuit diagram of the interpolation coefficient generating circuit 31. In the figure, 47 and 48 are bit inversion circuits, and 49 to 52 are multipliers. Since Dn is the length of one side of the unit cubic lattice, when inputting the upper 3 bits of the 8 bits of the input signal to the three-dimensional LUT 30, Dn = ²⁵ . Therefore, Dn-r is the inversion of all bits of r. Similarly, Dn-b is also an inversion of all bits of b. By utilizing the above, the operations of the expressions (39), (40), (41) and (42) can be realized by the bit inverting circuits 47 and 48 and the multipliers 49, 50, 51 and 52.

Multipliers 32, 33, 34, 3 shown in FIG.
5. Using the adder circuit 42, the first interpolation signal ds is calculated. Further, the multipliers 36, 37, 38, 39 and the adder circuit 4
3 is used to calculate the second interpolation signal ds'. Each,
The calculation formulas are represented by formulas (43) and (44). ds ＝ d ₀ S ₀ + d ₁ S ₁ + d ₂ S ₂ + d ₃ S ₃ …… (43) ds' ＝ d ₄ S ₀ + d ₅ S ₁ + d ₆ S ₂ + d ₇ S ₃ …… (44) In the equations (43) and (44), the signals at the respective grid points are multiplied by the areas located symmetrically with respect to the input signals Ri and Bi as the interpolation coefficients to obtain two interpolations on the RB plane. The signal is being calculated. Three-dimensional interpolation is realized by further interpolating these two interpolation signals ds, ds' on the G axis. When the length of one side of the unit cubic lattice is Dn, the output signal d is calculated as in equation (45). d = {ds' · g + ds · (Dn-g)} / Dn ³ (45) where g is the lower 5 bits of the input signal Gi, and dividing by Dn ³ is the interpolation coefficient This is to normalize 1 to 1. Here, Dn ³ is to become a 2 ^15, in fact can be calculated by lowering 15 bits of digits. The calculation of the equation (45) is performed by the multipliers 40 and 41, the adder 44, and the bit inverting circuit 45.
Will be realized in. The lower 5 bits g of the input signal Gi is multiplied by 4
1 and the bit inversion circuit 45, the first interpolation signal ds is input to the multiplier 40, and the second interpolation signal ds ′ is input to the multiplier 41. The output signals of the multipliers 40 and 41 are input to the adder 44, and the output of the adder 44 is digit-reduced by 15 bits by the 15-bit shift circuit 46 to obtain the output signal d. Interpolation processing of L ^* , a ^* , and b ^* is performed by the same calculation method.

Li ^* , ai ^* , bi ^* obtained by the above method is input to the aperture correction circuit 28 to perform aperture correction.
Get Li ^* ', ai ^* ', bi ^* '. FIG. 13 shows a block circuit diagram of the aperture correction circuit 28. In the figure, 53 to 56 are 1-pixel delay circuits (DLY), 57 to 61 are 1 horizontal scanning period delay circuits (1 HDLY), 85 to 87 are multipliers, and 88 to 95 are adders.

The operation of the aperture correction circuit 28 will be described. Input signal Li ^* (h,
It is assumed that v), ai ^* (h, v), bi ^* (h, v) are input to the aperture correction circuit 28. The input signal Li ^* (h, v) is input to the 1-pixel delay circuit 53 and the adder 88. The 1-pixel delay circuit 53 obtains the signal Li ^* (h-1, v) one pixel before, and this Li ^* (h-1, v) is input to the 1-pixel delay circuit 54 and the adder 89. The 1-pixel delay circuit 54 obtains the signal Li ^* (h-2, v) two pixels before,
This Li ^* (h-2, v) is input to the adder 88. The lower 1 bit of the output Li ^* (h, v) + Li ^* (h-2, v) of the adder 88 is truncated,
Input to the adder 89. As a result, the output of the adder 89 is as shown in equation (46). Li ^* (h-1, v)-{Li ^* (h, v) + Li ^* (h-2, v)} / 2 (46) The gain control signal C _H is input to the multiplier 85, The output signal is input to the delay circuit 59 for one horizontal scanning period to obtain the horizontal aperture control signal AP _H as shown in equation (47). A waveform diagram of the horizontal aperture control signal AP _H is shown in FIG. AP _H = C _H · [Li ^* (h-1, v-1)-{Li ^* (h, v-1) + Li ^* (h-2, v-1)} / 2] …… (47)

Further, the output signal Li of the one-pixel delay circuit 53
^* (h-1, v) is a horizontal scanning period delay circuit 57 and an adder 90
To enter. The signal Li ^* (h-1, v-1) one horizontal scanning period before is obtained by the one horizontal scanning period delay circuit 57, and this Li ^* (h-1, v-1) is obtained.
Is input to the delay circuit 58 for one horizontal scanning period. The 1 horizontal scanning period delay circuit 58 causes the signal Li 2 horizontal scanning periods before
^* (h-1, v-2) is obtained, and this Li ^* (h-1, v-2) is input to the adder 90. The lower 1 bit of the output Li ^* (h-1, v) + Li ^* (h-1, v-2) of the adder 90 is truncated and input to the adder 91. As a result, the output of the adder 91 is as shown in equation (48). Li ^* (h-1, v-1)-{Li ^* (h-1, v) + Li ^* (h-1, v-2)} / 2 (48) The gain control signal C _V is multiplied by It is input to 86 to obtain the vertical aperture control signal AP _V as shown in equation (49). A waveform diagram of the vertical aperture control signal AP _V is shown in FIG. AP _v = C _v · [Li ^* (h-1, v-1)-{Li ^* (h-1, v) + Li ^* (h-1, v-2)} / 2] …… (49)

The horizontal aperture control signal AP _H and the vertical aperture control signal AP _V are input to the adder 92, and equation (50)
An aperture control signal AP as shown in is obtained. AP = AP _H + AP _v (50) The output Li ^* (h-1, v-1) of the horizontal scanning period delay circuit 57 and the aperture control signal AP are input to the adder 93, and equation (51) is used.
An aperture correction signal Li ^* '(h-1, v-1) shown in is obtained. Li ^* '(h-1, v-1) ＝ Li ^* (h-1, v-1) + AP …… (51)

Aperture control signal AP and gain control signal C
_{The S} is input to the multiplier 87 to obtain the aperture control signal AP _S. The aperture control signal AP _S is input to the adders 94 and 95.

The input signal ai ^* (h, v) is input to the delay circuit 60 for one horizontal scanning period. The signal ai ^* (h, v-1) one horizontal scanning period before is obtained by the one horizontal scanning period delay circuit 60, and this ai ^* (h, v-
1) is input to the 1-pixel delay circuit 55. 1 pixel delay circuit 5
5, the signal ai ^* (h-1, v-1) one pixel before is obtained, and ai ^* (h-1, v-1) is obtained.
v-1) is input to the adder 94, and the aperture correction signal ai ^* '
Get (h-1, v-1). ai ^* '(h-1, v-1) ＝ ai ^* (h-1, v-1) + AP _S …… (52)

The input signal bi ^* (h, v) is input to the delay circuit 61 for one horizontal scanning period. A signal bi ^* (h, v-1) one horizontal scanning period before is obtained by the one horizontal scanning period delay circuit 61, and this bi ^* (h, v-
1) is input to the 1-pixel delay circuit 56. 1 pixel delay circuit 5
6, the signal bi ^* (h-1, v-1) one pixel before is obtained, and bi ^* (h-1, v-1) is obtained.
v-1) is input to the adder 95, and the aperture correction signal bi ^* '
Get (h-1, v-1). bi ^* '(h-1, v-1) ＝ bi ^* (h-1, v-1) + AP _S …… (53)

The structure of the color inverse conversion processing device 29 is the same as that shown in FIG. Conventionally, an image represented by an RGB signal is subjected to aperture correction for each of R, G, and B, or the RGB signal is converted into a luminance signal Y, an RY color difference signal, and a BY color difference signal by a matrix operation to obtain a luminance signal. Aperture correction is performed by controlling the gains of the luminance signal Y, the RY color difference signal, and the BY color difference signal in the high frequency portion of Y. The RGB color space is a color space of mixed colors,
It is not a uniform space for human visual characteristics. Therefore, like the former case, when the aperture correction that changes the gains of the R, G, and B signals at a constant ratio is performed in the high-frequency portion of the image represented by the RGB signals, the balance of hue, lightness, and saturation is lost, Color reproducibility deteriorates. Further, like the latter, by performing aperture correction on the luminance signal Y, the RY color difference signal, and the BY color difference signal, it is possible to emphasize the brightness and the saturation separately, but in the uniform perceptual color space. Therefore, the color reproducibility is deteriorated. R as in this embodiment
CIE 1976, which is uniform from the GB color space to human visual characteristics
By converting to L ^* a ^* b ^* uniform perceptual color space and performing aperture correction on each of L ^* , a ^* , and b ^* , it becomes possible to emphasize the high-frequency part of the image by dividing into lightness and saturation. At the same time, the balance of hue, brightness, and saturation is not disturbed, and the color reproducibility is not deteriorated.

In the first embodiment described above, the input signal of m bits is input.
In the case of Li ^* signal, ai ^* signal, and bi ^* signal, the unit plane with 2 ^mn bits on each side of the a ^* signal and b ^* signal for the lower ^mn bits is the axis of the a ^* signal. And b ^* 4 in the axial direction of the signal
Although the areas of the four planes in the case of division are used as the interpolation coefficients, other interpolation coefficients may be used in consideration of the conversion characteristics of the color space before conversion and the color space after conversion.

In the third embodiment, the CIE is calculated from the RGB color space.
1976 L ^* a ^* b ^* conversion to the uniform perceptual color space, aperture correction, and reverse conversion to the RGB color space were shown.
CIE1976 L ^* u ^* v ^* Aperture correction may be performed in the uniform perceptual color space, or aperture correction may be performed in another color space having the same hue, lightness, and saturation.

Storage means and LUT in the above embodiment
Is a ROM (Read Only Memory), RAM (Random Acc
It may be configured by a semiconductor element such as an ess memory) or other high-speed storage means. Further, in the above embodiment, the conversion method from the RGB color space to the CIE 1976L ^* a ^* b ^* uniform perceptual color space, the CIE 1976 L ^* a ^* b ^* uniform perceptual color space to the RGB
Although the inverse conversion method to the color space has been shown, conversion to another color space may be used.

[0084]

The present invention converts video information from a color space dependent on one image input / output device to a color space dependent on the other image input / output device, and has the following effects. .

According to the color inverse conversion processing device of the invention of claim 1, the first three-dimensional color space represented by the first, second, and third color signals is converted into the fourth, fifth, and sixth colors. Second represented by signal
For inversely converting the color signals non-linearly converted into the three-dimensional color space into the original first, second and third color signals, and the original three-dimensional color is stored in the storage means which is a component of the color inverse conversion processing device. By storing the conversion value outside the color space, it is possible to improve the color conversion accuracy by linear interpolation. Number of grid points is 729
Point, conversion value is 10 bits, CIE 1976 L ^* a ^* b ^* three-dimensional LUT for forward conversion using C light source as a reference light source of uniform perceptual color space,
Image simulation was performed using a three-dimensional LUT for inverse transformation. The image used for evaluation is ITE Color Match
ing Chart (a girl with carnation). For evaluation,
After forward transform into L ^* a ^* b ^* from RGB, using color difference between the processed image and the original image obtained by inverse conversion from the L ^* a ^* b ^* to RGB. The color difference was calculated in the CIE 1976 L ^* a ^* b ^* uniform perceptual color space, not in the RGB color space. The color difference of 8-point interpolation which is the conventional method is
1.34, color difference of 6-point interpolation is 1.42, color difference of 5-point interpolation is 2.29,
Color difference of 4-point interpolation is 1.48, color difference without interpolation is 2
It became 7.40. According to the present invention, the color difference is 1.31, and the color conversion accuracy is the highest.

According to the color inverse conversion processing device of the second aspect of the present invention, since the color inverse conversion is performed by the small-capacity storage means and the interpolation processing means, for example, the input signal is stored in the storage means as an 8-bit digital signal. When inputting the upper 3 bits of the input signal and performing the interpolation processing with the lower 5 bits of the input signal, the number of multipliers required from 72 in the conventional interpolation method can be reduced to 30 and the circuit scale can be reduced. It becomes possible.

According to the color inverse conversion processing device of the third aspect of the present invention, for example, multiplication of a 5-bit signal is performed by a 384-bit LUT.
It can be realized with four, two bit shift circuits and three adders,
4 multipliers required for interpolation signal generation are used for L with a total capacity of 6k bits.
Since it can be realized by the UT, eight bit shift circuits, and twelve adders, the circuit scale can be reduced.

According to the color inverse conversion processing device of the present invention, the interpolation coefficient generation circuit can be realized by a plurality of LUTs, a plurality of bit shift circuits and a plurality of adders, and the interpolation coefficient generation circuit has a total capacity of 1.5k. Since it can be realized by a bit LUT, five bit shift circuits, and eight adders, the circuit scale can be reduced.

According to the color inverse conversion processing device of the fifth aspect of the present invention, it is possible to improve the color conversion accuracy with respect to the storage capacity of the storage means which is a component of the color inverse conversion processing device.

According to the video signal processing device of the present invention, the fourth color signal and the fifth color signal of the color information from the three-dimensional color space represented by the first, second and third color signals. , By converting into the three-dimensional uniform perceptual color space of the color-developing system represented by the sixth color signal of the lightness information and performing aperture correction,
It is possible to emphasize the high-frequency part of the image by dividing it into lightness and saturation, and it is possible to maintain the balance of hue, lightness, and saturation without lowering the color reproducibility.

According to the video signal processing device of the seventh aspect of the invention, the aperture correction means is composed of a plurality of adders, a plurality of multipliers and a plurality of one-pixel delay circuits. With this gain, it becomes possible to perform horizontal aperture correction of the image.

According to the video signal processing device of the eighth aspect of the invention, since the aperture correction means is composed of a plurality of adders, a plurality of multipliers and a plurality of one horizontal scanning period delay circuits, the control signal is made variable. This makes it possible to perform vertical aperture correction of the image with an arbitrary gain.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a color inverse conversion processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an interpolation method in the color inverse conversion processing device according to the first embodiment.

FIG. 3 is a block circuit diagram showing a configuration of an interpolation coefficient generation circuit 2 in the first embodiment.

FIG. 4 is a block circuit diagram showing a configuration of an interpolation coefficient generation circuit 2 in Embodiment 2 of the present invention.

FIG. 5 is a block circuit diagram showing a configuration of a multiplication circuit 64 according to the second embodiment.

FIG. 6 is a block circuit diagram showing a configuration of an interpolation coefficient generation circuit 2 in Embodiment 3 of the present invention.

FIG. 7 is a block circuit diagram showing a color inverse conversion processing device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a conceptual diagram of a three-dimensional LUT 1 in Example 4.

FIG. 9 is a block circuit diagram showing a video signal processing device according to a fifth embodiment of the present invention.

FIG. 10 is a block circuit diagram showing a color conversion processing device 27 according to a fifth embodiment.

FIG. 11 is a diagram illustrating an interpolation method in the color conversion processing device 27 according to the fifth embodiment.

FIG. 12 is a block circuit diagram showing a configuration of an interpolation coefficient generation circuit 31 in the fifth embodiment.

FIG. 13 is an aperture correction circuit 28 according to the fifth embodiment.
3 is a block circuit diagram showing the configuration of FIG.

FIG. 14 is an aperture correction circuit 28 according to the fifth embodiment.
6 is a waveform diagram of a horizontal aperture correction signal AP _H generated in FIG.

FIG. 15 is an aperture correction circuit according to the fifth embodiment.
6 is a waveform diagram of a vertical aperture correction signal AP _V generated in FIG.

FIG. 16 is a block circuit diagram showing a conventional color conversion processing device and conventional color inverse conversion processing device.

FIG. 17 is a diagram showing a conceptual diagram of a three-dimensional LUT 96.

FIG. 18 is a diagram showing a conceptual diagram of a three-dimensional LUT 97.

FIG. 19 is a block circuit diagram showing a conventional color conversion processing device.

FIG. 20 is a diagram showing an interpolation method in a conventional color conversion processing device.

FIG. 21 is a block circuit diagram showing a conventional color inverse conversion processing device.

FIG. 22 is a diagram showing an interpolation method in a conventional color inverse conversion processing device.

[Explanation of symbols]

1, 30, 96, 97 Three-dimensional LUT, 2, 31 Interpolation coefficient generation circuit, 3 to 12, 20 to 23, 32 to 41, 4
9-52, 85-87 Multiplier, 13, 14, 42, 4
3,98,99 adder circuit, 17,46 15-bit shift circuit, 15, 44, 72-74, 80-84, 88
~ 95 adder, 16, 18, 19, 45, 47, 4
8, 66, 67 bit inversion circuit, 24 L ^* axis LU
T, 25 a ^* axis LUT, 26 b ^* axis LUT, 27
Color conversion processing device, 28 aperture correction circuit, 29 color inverse conversion processing device, 53-56 1 pixel delay circuit, 57-
61 1 horizontal scanning period delay circuit, 62 to 65 multiplication circuit, 68
~ 71 LUT, 75 6-bit shift circuit, 76 3-bit shift circuit, 77
~ 795 bit shift circuit.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-4-21264 (JP, A) JP-A-4-145792 (JP, A) JP-A-4-242372 (JP, A) JP-A-4- 336876 (JP, A) JP-A-6-1001 (JP, A) JP-A-6-30300 (JP, A) JP-A-6-105132 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9/44-9/78 H04N 1/46 H04N 1/60

Claims (8)

(57) [Claims] 1. A first three-dimensional color space represented by first, second, and third color signals is non-linear to a second three-dimensional color space represented by fourth, fifth, and sixth color signals. In a color inverse conversion processing device for inversely converting the converted color signal into first, second, and third color signals, the fourth, fifth, and sixth color signals are digital signals of m (m is a natural number) bits. As the first, second, and third color signals, which are assumed to be located on or located in a unit cubic lattice of eight points near the first, second, and third color signals corresponding to the input signal. Storage means for outputting
Interpolation coefficient generating means for generating an interpolation coefficient for multiplying the first, second and third color signals of the point, and the m-bit fourth and fifth
The first, second and third color signals located in the unit plane lattice of four points when the sixth color signal includes the upper n (n is a natural number and m> n) bits. Means for outputting a first interpolated signal that is obtained by multiplying and adding each of the interpolation coefficients, and similarly includes m-bit fourth and fifth color signals, and the sixth color signal adds 1 to the upper n bits. In the case of four points, the first, second, and third color signals located in the unit plane grid are multiplied by the respective interpolation coefficients, and are added to output a second interpolation signal. By multiplying 2 ⁿ by subtracting the sixth color signal of lower mn bits, and adding the second interpolation signal by multiplying the sixth color signal of lower mn bits, An inverse color conversion processing device comprising an interpolation processing means for calculating first, second and third color signals. 2. A unit plane having a side of 2 ^mn bits centering on the fourth and fifth color signals corresponding to the lower ^mn bits,
2. The color according to claim 1, further comprising: an interpolation coefficient generating unit that outputs, as an interpolation coefficient, an area of four planes when the color signal is divided into four in the axial direction of the color signal and the axial direction of the fifth color signal. Inverse conversion processing device. 3. An interpolation coefficient generation means for inputting fourth and fifth color signals of lower m-n bits and outputting four interpolation coefficients necessary for calculating the first interpolation signal and the second interpolation signal. 4
The color inverse conversion processing device according to claim 1, wherein the color inverse conversion processing device is configured by one storage means. 4. The fourth and fifth color signals for the lower mn bits are input and one of the four interpolation coefficients necessary for calculating the first interpolation signal and the second interpolation signal is set. The storage means for outputting and an interpolation coefficient generating means for calculating other three interpolation coefficients from the output signal of the storage means, a plurality of adders and a plurality of bit shift circuits are provided. Color inverse conversion processing device. 5. One side of the unit cubic lattice at the central portion of the storage means for storing the output first, second and third color signals for the input fourth, fifth and sixth color signals is 2 ^mn , One side of the unit cubic lattice at the end of the storage means is 2 ^{m-n + p} (p is a natural number n
> P), The inverse color conversion processing device according to claim 1. 6. A four-dimensional color signal having color information, a fifth color signal having a color information, and a sixth color signal having lightness information in a three-dimensional color space represented by first, second and third color signals. In a video signal processing device for performing aperture correction by converting into a three-dimensional uniform perceptual color space of a represented color system, first, second, and third
Color signals are input as m-bit digital signals, and the fourth, fifth, and fourth unit cubic lattices located in the vicinity of the fourth, fifth, and sixth color signals corresponding to the input signals are located at eight points. 6
Storage means for outputting the color signal of, the interpolation coefficient generation means for generating an interpolation coefficient for multiplying the fourth, fifth, and sixth color signals of the eight points, and the m-bit first and second colors Signal, and the fourth, fifth, and sixth color signals, which are located on the unit plane lattice of four points when the third color signal is for the upper n bits, are multiplied by the interpolation coefficient and added. A unit for outputting one interpolation signal, and similarly, including m-bit first and second color signals, the third color signal is positioned on the unit plane lattice of four points when 1 is added to the upper n bits. Means for outputting a second interpolated signal obtained by multiplying the fourth, fifth, and sixth color signals by the above-mentioned interpolating coefficient and adding them together, and ²ⁿ to the lower order m for the first interpolated signal.
-N bits of the third color signal is subtracted and multiplied, and the second interpolation signal is multiplied by the lower mn bits of the third color signal to add the fourth, fifth, Interpolation processing means for calculating the sixth color signal, first gain control means for controlling the gain of the high frequency component of the sixth color signal in an arbitrary pixel, and gains of the fourth and fifth color signals in the pixel. A second gain control means for controlling, and a memory having the same configuration as described above for inversely converting the gain-controlled fourth, fifth, and sixth color signals into first, second, and third color signals. An image signal processing apparatus comprising: a means, an interpolation coefficient generating means, and an interpolation processing means. 7. A first gain control means for controlling a gain of a high frequency component of a sixth color signal in an arbitrary pixel, and a second gain control means for controlling a gain of a fourth and fifth color signal in the pixel. 7. The video signal processing device according to claim 6, wherein the video signal processing device comprises a plurality of adders, a plurality of multipliers, and a plurality of 1-pixel delay circuits. 8. A first gain control means for controlling a gain of a high frequency component of a sixth color signal in an arbitrary pixel, and a second gain control means for controlling a gain of a fourth and fifth color signal in the pixel. 7. A plurality of adders, a plurality of multipliers, and a plurality of 1 horizontal scanning period delay circuits are included in the circuit.
The described video signal processing device.