JP2016165076A - Data processing device, control method of the same, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently load lattice point data constituting a lookup table to a plurality of bank memories.SOLUTION: The data processing device for performing data processing by loading lattice point data constituting one lookup table to a plurality of bank memories receives the lattice point data, which is a load target, and a register address, and transforms the received register address to bank designation and a memory address on the basis of the number of pieces of the lattice point data stored in each bank memory. According to the bank designation and the memory address obtained by the transformation, the data processing device stores load target lattice point data to the plurality of bank memories.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data processing apparatus having a lookup table and a control method thereof.

  In recent years, scanners, digital cameras, digital video cameras, and the like have become widespread as color image input devices. On the other hand, as color image output devices, various color printers using methods such as ink jet and electrophotography have become widespread. Each of these input / output devices has a unique color space. For example, when a color image obtained by a scanner is transferred to another color printer and printed as it is, the color of the printed color image hardly matches the color of the original color image read by the scanner. In order to solve such a problem of color reproducibility between devices for a color image or the like, a process of converting the color space of the input device to the color space of the output device (referred to as color space conversion) is required. Therefore, in order to improve the color reproducibility of the input / output device, a color space conversion function is installed in the input / output device.

  The color space conversion specifically refers to the entire series of image processing such as input gamma correction, luminance density conversion, masking, black generation, output gamma correction, or a part of the processing. For example, in color space conversion, digital images of three colors (for example, red, green, and blue (RGB)) of an input device are simultaneously referred to and three colors (for example, cyan, magenta, and yellow (CMY)) of an output device are referred to. To digital image signal. Alternatively, the digital image signals of three colors of RGB are converted into digital image signals of four colors (for example, cyan, magenta, yellow, and black (CMYK)).

  As a method for realizing color space conversion, a conversion result is stored in advance in a memory as a lookup table (hereinafter referred to as LUT), and the conversion result is output by referring to the LUT for an input image signal. There is. In this color space conversion method using the LUT, an interpolation operation is generally used together to reduce the memory of the LUT. That is, the data of the conversion color (YMC or YMCK) corresponding to the representative point of the color to be converted (RGB) is stored in the memory, and the interpolation calculation is performed based on the conversion color data of several points stored in the memory. A simple conversion color data is calculated. The smaller the representative points on the axes such as RGB, the higher the conversion accuracy, but the more memory capacity is required. On the other hand, if the representative points are rough, the conversion accuracy decreases, but the required memory capacity decreases. Hereinafter, the representative point on the axis is called a grid point (grid), and the number of representative points on the axis is called the number of grid points per axis. As the number of lattice points per axis, a number from 8 to 33 is generally used. The fact that the number of grid points per axis is x may hereinafter be described as an x grid (for example, the case where the number of grid points per axis is 33 is described as a 33 grid).

  The number of grid points referenced to obtain a YMC (YMCK) value corresponding to a certain RGB value varies depending on the interpolation method. For example, interpolation calculation is performed with reference to eight lattice points in the case of cubic interpolation and four lattice points in the case of tetrahedral interpolation. Since the conversion color data of grid points is stored in the memory, in order to refer to the conversion color data of a plurality of grid points, multiple accesses to the memory occur. Processing performance cannot be improved. In view of this, a method has been proposed in which the memory is divided into a plurality of parts, and a plurality of memory accesses for reading data at a plurality of grid points are simultaneously performed to improve the processing performance.

  In Patent Document 1, in order to execute three-dimensional cube interpolation at high speed, 32 grid conversion color data is stored in eight memories and read out in parallel to increase the speed. Japanese Patent Application Laid-Open No. H10-228561 discloses a method of storing LUT conversion color data that cannot be represented by a power of 2 in terms of the number of grid points per axis, divided into memories. As an example, a method is described in which converted color data of 33 grids is divided into 8 memories and the addresses are generated with 13 bits. Both Patent Documents 1 and 2 are common in that even and odd coordinates of each axis store the same representative point in the same memory. That is, in the case of a three-dimensional LUT in which the colors to be converted are three colors of RGB, eight (even, even, even), (even, even, odd), ..., (odd, odd, odd) High-speed processing is possible by dividing and storing in this memory.

U.S. Pat. No. 4,837,722 JP 2001-36755 A

  In Patent Document 1, a memory capable of storing a total of 32768 (= 32 * 32 * 32) representative point conversion color data (hereinafter referred to as grid point data) is required to perform processing on 32 grids. In Patent Document 2, a memory capable of storing 35937 (= 33 * 33 * 33) pieces of grid point data is required in order to perform processing with 33 grids. Since the required memory capacity is different between the case of 32 grids and the case of 33 grids, it is necessary to divide the memory according to the largest capacity in order to cope with the number of types of grids. Further, when the number of grids is an odd number, if the memory is divided into eight (or four), the capacity of the grid point data stored in each memory varies depending on the even / odd combination of each axis. Therefore, when grid point data is stored in a memory in order to set an LUT, it is necessary to store the data in consideration of the number of grid point data for each memory. Alternatively, in order to eliminate such control, it is necessary to add and store unnecessary data in accordance with the memory having the largest capacity.

  The present invention has been made in view of the above problems, and an object of the present invention is to efficiently store lattice point data constituting a lookup table in memories of a plurality of banks.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention comprises the following arrangement. That is,
A data processing apparatus that loads grid point data constituting one lookup table into a plurality of banks of memory and executes data processing,
Receiving means for receiving the grid point data to be loaded and the register address;
Conversion means for converting the register address received by the receiving means into bank designation and memory address based on the number of grid point data stored in the memory of each bank;
Storage means for storing the grid point data to be loaded in the memories of the plurality of banks according to the bank designation and memory address obtained by the conversion means.

  According to the present invention, lattice point data constituting a lookup table can be efficiently stored in the memories of a plurality of banks.

The block diagram which shows the structural example of the image process part in 1st Embodiment. The figure which shows the format of a command. The figure which shows the bank division | segmentation according to a grid, and the number of data. The figure which shows the memory map according to grid mode. 5 is a flowchart showing the operation of an address decoder used in the first embodiment. The block diagram which shows the structural example of the image process part in 2nd Embodiment. The figure which shows the data storage number of each bank after LUT setting. 9 is a flowchart showing the operation of an address decoder used in the second embodiment. The block diagram which shows the structure of the image process part in 3rd Embodiment. 10 is a flowchart showing the operation of an address decoder used in the third embodiment. The block diagram which shows the structural example of the data processor by embodiment.

  Hereinafter, the present invention will be described in detail based on preferred embodiments with reference to the accompanying drawings. Note that the configurations shown in the following embodiments are merely examples, and the present invention is not limited to the illustrated configurations.

<First Embodiment>
FIG. 11 is a block diagram illustrating an example of a control configuration of the data processing apparatus 10 (for example, a printing apparatus) according to the first embodiment. CPU11 controls the operation | movement of each part of a data processor by executing the program stored in ROM12 or RAM112. The transfer unit 111 provides various commands and input data 114 input by the input unit 113 to the data processing unit 100 under the control of the CPU 11. The input data 114 is image data for printing, for example, and is obtained by communication with an external device or reading from the external storage device 14. The data processing unit 100 processes input data (image data), and the processed data is output (for example, printed) by the output unit 13. Note that at least some of the functions of the components such as the transfer unit 111, the input unit 113, and the data processing unit 100 may be realized by the CPU 11 executing a predetermined program.

  FIG. 1 is a block diagram illustrating a configuration example of the data processing unit 100 according to the first embodiment. The data processing unit 100 includes a control unit 101, a processing unit 102, and a storage unit 103 having a plurality of memories (bank 0 to bank 7: a difference in height indicates a difference in capacity). The control unit 101 receives from the transfer unit 111 a register command for register setting and LUT setting, and a data command storing data to be processed. In the present embodiment, an image processing apparatus in which image data (RGB data) is processed by the data processing unit 100 is exemplified, but the data to be processed is not limited to this.

  The control unit 101 analyzes the received command and determines whether the command is a register command or a data command. When the received command is a register command, the control unit 101 sets a value in a register or memory (not shown) according to the address stored in the command. For example, when the received command is a register command and the address stored in the command is a register address as shown in FIG. 4A, the control unit 101 stores a lookup table (LUT) in the memory of the storage unit 103. ) Is stored. As described above, the data processing unit 100 according to the present embodiment executes data processing by loading lattice point data constituting one look-up table into a plurality of banks of memory.

  If the received command is a data command, data (eg, image data) is extracted from the data area of the command and input to the processing unit 102. For example, when RGB data is stored in the data command, the control unit 101 extracts the RGB data from the data command and inputs it to the processing unit 102. For example, the processing unit 102 performs predetermined processing including conversion processing (for example, processing for converting RGB data into CMYK data) with reference to the LUT in the storage unit 103 for the input RGB data. Data processed by the processing unit 102 is input to the control unit 101 again. When receiving the processed data from the processing unit 102, the control unit 101 outputs the data command format again to the outside. Note that the processing unit 102 determines, for example, the number of LUT lattice points and the type of interpolation processing (for example, tetrahedral interpolation processing) used for data conversion processing with reference to the LUT by referring to the set register value. It may be. The register value in this case is set by the register command described above. The above is a general flow of image processing according to the present invention. Next, the operation of each component will be described in detail.

  As described above, the control unit 101 performs setting of a register to be referred to by the processing unit 102, setting of the storage unit 103, data exchange with the processing unit 102, and the like according to a command input from the transfer unit 111. First, the control unit 101 analyzes an input command and determines whether the command is a register command or a data command. FIG. 2 shows a command format. FIG. 2A shows a register command, and FIG. 2B shows a data command. By referring to the register / data determination flag 201 located at the most significant bit of the command, it can be determined whether the command is a register command or a data command. For example, if the register / data discrimination flag 201 is 1, it is a register command, and if it is 0, it is a data command. When the control unit 101 determines that the received command is a register command, the control unit 101 accesses the storage unit 103 in accordance with the address 203 stored in the command, or registers in the control unit 101 or the processing unit 102 ( Determine whether to access (not shown). The register command has an RW flag 202 indicating whether the access is a read operation or a write operation, and the write access and the read access are switched according to the value. Further, setting data 204 exists in the register command, and in the case of a write operation, a value stored therein is set in the register in the control unit 101 or the processing unit 102 or the storage unit 103. On the other hand, when the control unit 101 determines that the received command is a data command, the control unit 101 sends the data stored in the data command (image data 205 in this embodiment) to the processing unit 102.

  Next, image processing performed by the processing unit 102 will be described. As an example of processing in the processing unit 102, an example of converting data using tetrahedral interpolation processing with reference to a three-dimensional LUT having 17 grids (for example, processing for converting RGB data into YMCK data) will be described. The 17-grid LUT is an LUT having 17 grid points per axis. In the case of a 17-grid LUT, there are 17 grid points from 0 to 16, so the total number of grid points in three dimensions is 17 * 17 * 17 = 4913. Is loaded into the storage unit 103 and stored. The processing unit 102 accesses the storage unit 103 according to the input data (RGB data), reads a plurality of grid point data (YMCK data), performs interpolation processing using them, and obtains conversion data (YMCK data).

In the case of tetrahedral interpolation, it is necessary to read out the grid point data of four adjacent points from the storage unit 103. Therefore, the processing unit 102 speeds up data processing by dividing the memory in the storage unit 103 into a plurality of banks to enable parallel access and simultaneously reading out a plurality of lattice point data used for processing. In this embodiment, it is possible to simultaneously read out the four grid point data necessary for the interpolation processing by dividing the storage destination memory (bank) by the even number and odd number of coordinate values of each axis of the grid point coordinates. ing. That is,
9 * 9 * 9 = 729 pieces of data corresponding to lattice points with coordinates (even, even, even) are stored in bank 0 of the memory in the storage unit 103.
・ 9 * 9 * 8 = 648 pieces of data corresponding to grid points with coordinates (even, even, odd) are stored in bank 1,
・ 9 * 8 * 9 = 648 pieces of data corresponding to grid points with coordinates (even, odd, even) are stored in bank 2,
...
8 * 8 * 8 = 512 pieces of data corresponding to lattice points with coordinates (odd, odd, odd) are stored in the bank 7;
Thus, it is stored in a memory divided into eight banks.

  FIG. 3A shows the number of grid point data stored in the memory of each bank when a 17-grid LUT is referenced. Each of the memories in the banks 0 to 7 shown in FIG. 1 has a size for storing the number of grid point data shown in FIG. Since the number of grid point data stored for each bank differs, the control unit 101 needs to appropriately select and store the storage destination bank when storing the grid point data in the storage unit 103. The operation performed by the control unit 101 to classify data into different numbers of grid point data and store them in a plurality of banks of memory will be described in detail.

  When the control unit 101 receives a register command for performing register setting to the processing unit 102, the control unit 101 sets a value in the control unit 101 or a register (not shown) of the processing unit 102. When the control unit 101 receives a register command for setting grid point data, the control unit 101 stores the setting data 204 in the memory of the storage unit 103. Whether the register command is register setting or grid point data setting is determined by the address 203 in the command. For example, if the command is a register command, the RW flag 202 indicates a write operation, and one of the register addresses shown in FIG. In the case of a register command for setting grid point data, grid point data (for example, CMYK data) at one grid point coordinate is stored as the setting data 204. The control unit 101 stores the memory in the storage unit 103 in accordance with the register command including the grid point data to be loaded and the register address. In this embodiment, one grid point data consumes four register addresses as data handled in units of 4 bytes, and the register command address 203 stores the head address of the four register addresses. Is done.

  Note that a register command for loading LUT lattice point data may be generated by the CPU 11 and loaded via the transfer unit 111, for example. In this case, for example, the CPU 11 reads out the grid point data stored in the external storage device 14 in order of even and odd grid point coordinates, assigns consecutive register addresses from 0x0000 to 0x4CC0, and sends a register command. Generate. Alternatively, the CPU 11 may sequentially generate the grid point data from the matrix coefficients in the order of even and odd grid point coordinates, and assign consecutive register addresses from 0x0000 to 0x4CC0 to generate a register command. Alternatively, the transfer unit 111 may transfer the lattice point data stored in the RAM 112 to the control unit 101 by assigning consecutive register addresses from 0x0000 to 0x4CC0 as transfer destination addresses. In this case, the CPU 11 stores the grid point data on the RAM 112 in the order of the even and odd grid point coordinates. Then, the transfer unit 111 sequentially reads the grid point data on the RAM 112, assigns consecutive register addresses from 0x0000 to 0x4CC0, and generates a register command. As described above, a register address is assigned to the grid point data constituting one lookup table, and a register command is generated. The register command setting data 204 for loading the lookup table stores grid point data (for example, CMYK data) corresponding to one grid point coordinate.

  The control unit 101 uses the address decoder 104 to convert a register address (address 203) in the register command into a memory bank designation and address in the storage unit 103 according to a predetermined memory map. Then, the control unit 101 writes the grid point data (setting data 204) stored in the register command to the memory of the designated bank. The address decoder 104 converts the register address stored in the received register command into a bank designation and a memory address based on the number of grid point data stored in the memory of each bank. The control unit 101 stores the grid point data to be loaded stored in the register command in a plurality of banks of memory according to the bank designation and memory address obtained by the address decoder 104. Hereinafter, this process will be described in detail.

  FIG. 4A shows a memory map used for processing in the 17 grid. Following 729 grid point data from (0, 0, 0) to (16, 16, 16) with grid point coordinates (even, even, even), the grid point coordinates are (even, even, odd) ) 648 lattice point data from (0, 0, 1) to (16, 16, 15). These 729 lattice point data and 648 lattice point data are continuously stored, and unnecessary data for adjusting to the maximum number of lattice point data 729 before, during and after 648 lattice point data. There is no area. That is, the register addresses are assigned so that all the grid point data constituting one look-up table are continuous, and the grid point data group classified into each of the plurality of banks is continuous. The first 729 lattice point data are stored in the bank 0 memory, and the subsequent 648 lattice point data are stored in the bank 1 memory. The register addresses are continuous as they are, and the grid point data from (1, 1, 1) to (15, 15, 15) whose grid point coordinates are (odd, odd, odd) are appropriate. Mapped to bank memory. Thus, the register address stored in the register command is converted into a bank and memory physical address and stored in each memory of the storage unit 103 as shown in FIG. In FIG. 4A, the register address starts from 0x0000, but is not limited to this. All grid point data in a 17-grid LUT may be allocated to a continuous address space.

  FIG. 5 is a flowchart showing the operation of the address decoder 104. Hereinafter, the operation of the address decoder 104 will be described with reference to the flowchart of FIG. As described above, since one grid point data is handled in units of 4 bytes and consumes four register addresses, first, in step S601, it is checked whether the register address stored in the register command is a multiple of four. . If it is not a multiple of 4 (the lower 2 bits are not 0), the process is terminated without accessing the memory in the storage unit 103. In step S602, the register address is divided by 4 to obtain a value A (that is, a value A obtained by shifting the address to the right by 2 bits). Then, by comparing the value A with a predetermined threshold (steps S603, S605, S607, S609, S611, S613, S615, S617), the bank and memory address are determined as described below (steps S604, S606). , S608, S610, S612, S614, S616, S618).

(1) When 0 ≦ A <729, the bank outputs 0 and the memory address outputs A (S603, S604).
(2) When 729 ≦ A <1377, the bank outputs 1 and the memory address outputs A-729 (S605, S606).
(3) When 1377 ≦ A <2025, the bank outputs 2 and the memory address A-1377 (S607, S608)
(4) When 2025 ≦ A <2601, the bank outputs 3 and the memory address A-2025 (S609, S610)
(5) When 2601 ≦ A <3249, the bank outputs 4 and the memory address A-2601 (S611, S612).
(6) When 3249 ≦ A <3825, the bank outputs 5 and the memory address outputs A-3249 (S613, S614).
(7) When 3825 ≦ A <4401, the bank outputs 6 and the memory address A-3825 (S615, S616)
(8) When 4401 ≦ A <4913, the bank outputs 7 and the memory address outputs A-4401 (S617, S618).
(9) When 4913 ≦ A, the memory is not accessed.

Note that the thresholds used for bank selection are
729 = 9 * 9 * 9
1377 = 729 + 9 * 9 * 8
2025 = 1377 + 9 * 8 * 9
2601 = 2020 + 9 * 8 * 8
3249 = 2601 + 8 * 9 * 9
3825 = 3249 + 8 * 9 * 8
4401 = 3825 + 8 * 8 * 9
4913 = 4401 + 8 * 8 * 8
More demanded. The threshold is determined by the number of grid point data stored in the memory of each bank. The number of grid point data stored in the memory of each bank is 2 ⁿ +1 grid points per grid of the LUT (grid), the number of dimensions is m, and the number of odd coordinates among the coordinate values of each axis is p. In this case, (2 ⁿ⁻¹ +1) ^p × (2 ⁿ⁻¹ ) ^m−p .

  By operating the address decoder as described above, the register address can be converted into the bank and the memory address in the storage unit 103 where the lattice point data is stored. Note that the address decoder implementation method is not limited to this method, and another method such as calculation using a calculation formula may be used. In this way, the necessary grid point data is continuously mapped to the memory without excess or deficiency, thereby reducing the required memory capacity, the number of commands for setting the grid point data, and the ROM capacity for storing the firmware. It becomes possible.

  Note that the reading of the lattice point data stored in the memories of the plurality of banks 0 to 7 can be performed, for example, as follows. For example, when the number of grid points on each axis of the three-dimensional lookup table is 17 grids, the grid point coordinates of the LUT are configured by 5-bit coordinate values (r, g, b) for each axis. Assume that grid point coordinates (r, g, b) are obtained based on the input RGB data. Since the bank is determined by an odd number or even number of coordinate values of each axis, the information specifying the bank is the LSB of each of r, g, and b (r [0], g [0], b [0]). Are obtained by concatenating, that is, 4 × r [0] + 2 × g [0] + b [0]. The memory address of the storage unit 103 is derived from the 4-bit data values r [4... 1], g [4 ... 1], b [4 ... 1] obtained by removing the LSB from the 5 bits r, g, and b. can get. That is, r [4 ... 1] × (9−g [0]) × (9−b [0]) + g [4 ... 1] × (9−b [0]) + b [4 ... 1] The memory address of the point is obtained. The processing unit 102 acquires a plurality of grid point data corresponding to RGB data as input data by the above processing, and performs interpolation processing using them to output data corresponding to input data (for example, RGB data). (For example, CMYK data) is obtained. The processing unit 102 performs interpolation processing based on the grid point data and the RGB data read in this way, and converts the RGB data into corresponding YMCK data.

  As described above, in the present embodiment, the setting operation of the grid point data is performed by the control unit 101 according to the memory map in which the grid point data necessary for the 17 grid processing is arranged without excess or deficiency. Therefore, only necessary data and commands for setting the memory capacity and grid point data of the storage unit 103 need be prepared, and the number of circuits can be reduced. In the above embodiment, a 17-grid three-dimensional LUT is illustrated, but the present invention is not limited to this. For example, the number of dimensions of the LUT may be two or more. Further, the number of grids (number of grid points per axis) is not limited to 17. When the number of grids is an even number, the number of grid point data stored in the memory of each bank is equal. In the case of an LUT having an odd number of grids, the number of grid point data assigned to each bank is different as in the above embodiment, but the number of grid point data assigned to each bank is held at successive addresses. The memory capacity can be reduced.

  Since the number of grid points of the bank 7 is 512, if writing to the memory is prohibited when any of the bits higher than the ninth bit of the memory address of the bank 7 is '1' in step S618, Comparison with the threshold 4913 (step S617) is unnecessary. In this case, step S618 is executed when NO is determined in step S615.

Second Embodiment
In the first embodiment, it has been shown that the memory capacity of the storage unit 103 and the capacity of the ROM storing the firmware can be reduced by providing the control unit 101 with a function of appropriately allocating the storage location of the grid point data. . In the second embodiment, an example is shown in which a single processing unit 102 is provided with a plurality of types of processing functions and is selectively used depending on register settings.

  FIG. 6 shows a block diagram of an image processing apparatus according to the second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. Hereinafter, the control unit 701 and the processing unit 702 that operate differently from the first embodiment will be described. In the second embodiment, a register address is converted into a bank designation and a memory address in accordance with instruction information indicating one of a plurality of types of lookup tables having different numbers of grids per axis, and in accordance with the instruction information, The processing unit 702 operates.

  The processing unit 702 performs 16 grid processing in addition to the 17 grid processing described in the first embodiment. Which grid number is used for processing is set by the register value of the register 703. Hereinafter, a mode for processing with 17 grids is referred to as a 17 grid mode, and a mode for processing with 16 grids is referred to as a 16 grid mode. The control unit 701 includes a register 703 that stores “17 GridMode”, and the processing unit 702 refers to the register 703 to switch between the 16 grid mode and the 17 grid mode. When “17 GridMode” of the register 703 is set to “0”, the processing unit 702 operates in the 16 grid mode, and when set to “1”, the processing unit 702 operates in the 17 grid mode. As described above, “17GridMode” is used as instruction information for instructing the LUT used for processing. Note that the setting of 17GridMode in the register 703 is realized by a register command input from the transfer unit 111.

The 16 grid mode is a processing mode that uses an LUT having 16 grid points per axis. When operating in the 16 grid mode, there are 16 grid points from 0 to 15, so the total number of grid points of a three-dimensional LUT such as RGB is 16 * 16 * 16 = 4096. Data corresponding to the lattice points is read from the memory divided according to the even and odd combinations of the lattice point coordinates. That is,
Read out 8 * 8 * 8 = 512 grid point data corresponding to grid points with coordinates (even, even, even) from bank 0 of the memory in the storage unit 103;
Read 512 grid point data corresponding to grid points with coordinates (even, even, odd) from bank 1,
...
Read 512 pieces of data corresponding to lattice points with coordinates (odd, odd, odd) from the bank 7 and so on, and so on. FIG. 3B shows the number of grid point data stored for each bank when processing with 16 grids.

  The 16 grid mode and the 17 grid mode differ in the amount of grid point data stored in the storage unit 103. In the present embodiment, in order to perform arithmetic processing in two modes with the same image processing module, the storage unit 103 includes a memory that matches the capacity of 17 grids with a large capacity. That is, the memory configuration is the same as in the first embodiment.

  Next, processing of the control unit 701 will be described. The control unit 701 includes a register 703 for setting a processing mode (17 GridMode). First, the control unit 701 receives a register command for setting the register 703. Upon receiving a register command for setting the processing mode (17GridMode), the control unit 701 sets the register 703 and inputs a setting value to the processing unit 702. Necessary settings for the processing unit 702 other than 17GridMode are also input as commands at this time. There is no regulation in the register setting order, and the setting order may be changed.

  Next, a register command for setting grid point data is input to the control unit 701. The control unit 701 receives a register command for setting lattice point data necessary for image processing in the storage unit 103. Since the number of grid point data in the LUT differs depending on whether the processing is performed in the 16 grid mode or the 17 grid mode, the number of register commands for setting the grid point data received by the control unit 701 is also different. That is, when processing in the 16 grid mode, 4096 grid point data setting register commands are received, while when processing in the 17 grid mode, 4913 grid point data setting register commands are received.

  When the control unit 701 receives a register command for setting grid point data, the control unit 701 refers to an address stored in the command and stores the grid point data in an appropriate memory of the storage unit 103. As described above, since the number of grid point data stored in the storage unit 103 is different between the 16 grid mode and the 17 grid mode, the control unit 701 needs to distribute the grid point data to the appropriate bank memory according to the grid mode setting. There is. FIG. 4B shows a memory map in the 16 grid mode. The control unit 701 refers to the 17 GridMode of the register 703 that has already been set, and determines which of the memory maps in FIGS. 4A and 4B is to be followed.

  As shown in FIG. 6, the control unit 701 includes an address decoder 704 in the same manner as the control unit 101, and the 17GridMode setting in the register 703 can be referred to from the address decoder 704. When 17GridMode in the register 703 is “0”, that is, 16 grid mode is indicated, the register address is converted into the bank and the memory address according to the memory map of FIG. 4B, and the lattice point data is written into the memory. Go.

  As shown in FIG. 4B, consecutive register addresses are assigned to the grid point data of the 16-grid LUT. That is, following the 512 grid point data from (0, 0, 0) to (14, 14, 14) whose grid point coordinates are (even, even, even), (even, even, odd) A continuous register address is assigned to 512 grid point data from (0, 0, 1) to (14, 14, 15). Thus, consecutive register addresses are assigned to grid point data, and unnecessary data areas for adjusting to the maximum memory capacity (capacity of 729 grid point data) before, after and in the middle of 512 grid point data. Does not exist. In this way, consecutive register addresses are assigned up to 512 lattice point data from (1, 1, 1) to (15, 15, 15) whose lattice point coordinates are (odd, odd, odd).

  Then, as shown in FIG. 4B, the address decoder 704 has 512 points from (0, 0, 0) to (14, 14, 14) whose lattice point coordinates are (even, even, even). Are sequentially mapped from the address 0 of the memory (memory 0) of the bank 0. Subsequently, the address decoder 704 stores 512 lattice point data from (0, 0, 1) to (14, 14, 15) having lattice point coordinates (even, even, odd) in the memory of the bank 1. Mapping to (memory 1). In this way, consecutive register addresses are mapped to a plurality of banks of memory, and 512 data from grid point coordinates (1, 1, 1) to (15, 15, 15) are mapped to the memory of the bank 7 (memory 7). Is done.

  On the other hand, the operation when the 17GridMode of the register 703 is “1”, that is, the 17 grid mode is the same as that of the first embodiment, and the grid point data is mapped to each memory of the storage unit 103 according to the memory map of FIG. Is done.

  As described above, the control unit 701 includes the address decoder 704 for converting the register address into the data storage destination bank and the memory address in the same manner as in the first embodiment, and performs the mapping of the grid point data as described above. Realize. FIG. 8 is a flowchart showing the operation of the address decoder 704 of the second embodiment. Steps having the same operations as those in the flowchart of FIG. Hereinafter, the operation of the address decoder 704 will be described with reference to the flowchart of FIG.

  First, in step S601, the address decoder 704 checks whether the register address is a multiple of four. If it is not a multiple of 4, the process is terminated without accessing the memory. If it is a multiple of 4, the process proceeds to step S602, and the address decoder 704 divides the register address by 4 to obtain a value A. Next, in step S901, it is determined whether 17GridMode of the register 703 is set to “1”. If it is set to 1, the process proceeds to step S918. Step S918 is processing to load the grid point data of the 17-grid LUT into the storage unit 103, and the specific processing content is the same as that of the first embodiment (steps S603 to S618 in FIG. 5).

On the other hand, if 17GridMode of the register 703 is set to “0”, the process advances to step S902 to execute memory mapping corresponding to the 16 grid LUT. That is, by comparing the value A with a predetermined threshold (steps S902, S904, S906, S908, S910, S912, S914, S916), the bank and the memory address to be selected are determined as described below (step S903). , S905, S907, S909, S911, S913, S915, S917), and the lattice point data are mapped.
(1) When 0 ≦ A <512, the bank outputs 0 and the memory address outputs A (S902, S903).
(2) When 512 ≦ A <1024, the bank outputs 1 and the memory address outputs A-512 (S904, S905).
(3) When 1024 ≦ A <1536, the bank outputs 2 and the memory address A-1024 (S906, S907)
(4) When 1536 ≦ A <2048, the bank outputs 3 and the memory address A-1536 (S908, S909)
(5) When 2048 ≦ A <2560, the bank outputs 4 and the memory address A-2048 (S910, S911).
(6) When 2560 ≦ A <3072, the bank outputs 5 and the memory address A-2560 (S912, S913).
(7) When 3072 ≦ A <3584, the bank outputs 6 and the memory address A-3072 (S914, S915)
(8) When 3584 ≦ A <4096, the bank outputs 7 and the memory address outputs A−3584 (S916, S917).
(9) When 4096 ≦ A, the memory is not accessed.

  As a result of storing the grid point data in the storage unit 103 as described above, set values are stored in the eight memories of the storage unit 103 as shown in FIG. FIG. 7A shows the result of storing the grid point data in the 17 grid mode, and FIG. 7B shows the result of storing the grid point data in the 16 grid mode. In the fractions described in each bank in the figure, the denominator represents the capacity of each memory (the maximum number of grid point data that can be stored), and the numerator represents the number of stored grid point data. In the 17 grid mode, all the areas are used in all the memories (memory 0 to memory 7) of the storage unit 103. However, in the 16 grid mode, only the grid point data necessary for the 16 grid interpolation process is obtained. Stored in each memory.

  Next, the control unit 701 receives a data command. Image data to be subjected to image processing is extracted from the data commands input to the control unit 701 and input to the processing unit 702. The processing unit 702 performs predetermined image processing on the received image data in accordance with a set register value (value of 17GridMode). That is, if 17GridMode is set to 1, the processing unit 702 performs processing in the 17 grid mode, and if it is set to 0, the processing unit 702 performs processing in the 16 grid mode. The processing unit 702 inputs the processed data to the control unit 701 again. The control unit 701 generates a data command from the received processed data and outputs it.

  The above is the flow of image processing in the image forming system of the second embodiment. As described above, the processing mode (17GridMode) is first set in the register, and then, when setting the grid point data, grid point data suitable for image processing in the set processing mode is stored in the storage unit 103. Image processing. By performing register settings and grid point data settings in such a procedure, even an image processing module having a single storage unit 103 consisting of eight memories can perform multiple types of image processing. It becomes.

  Since the number of stored grid point data for each bank in the 16 grid mode is 512, the address decoder 704 may generate the bank and memory address by extracting predetermined bits from the register address. For example, the bits 13 to 11 of the register address (MSB: 13, LSB: 0) may be extracted as a bank, and the bits 10 to 2 of the register address may be extracted as a memory address.

<Third Embodiment>
In the second embodiment, it is shown that data can be stored in a memory according to image processing in the set processing mode by setting the processing mode (17 GridMode) in the register 703 when setting the register. . Here, the control unit 701 is configured to select a threshold value possessed in advance according to the set value of 17GridMode in the register 703 and output a bank and an address to be stored according to the threshold value. That is, since the configuration is selected from a plurality of modes prepared in advance (17 grid and 16 grid in the second embodiment), selectable modes are limited. In the third embodiment, a data processing unit 100 that can set a threshold set in a register, that is, can change the threshold set according to a lookup table to be used, and can be applied to a wider range of processing modes. I will provide a.

  FIG. 9 is a block diagram of an image processing apparatus according to the third embodiment. The operation of the control unit 1001 is different from that of the second embodiment, and the operation of the control unit 1001 will be described below. The control unit 1001 has a register 1003 for storing threshold values Th0 to Th7. When the control unit 1001 receives a register setting command for setting a threshold value, the control unit 1001 sets a threshold value Th0 to Th7 for switching the storage destination bank at the time of setting the lattice point data in the register 1003. In the register 1005, a processing mode is set. For example, when the control unit 1001 and the processing unit 702 are operated in the 17 grid mode, the control unit 1001 sets the threshold used in the processing illustrated in FIG. That is, the control unit 1001 sets 729, 1377, 2025, 2601, 3249, 3825, 4401, and 4913 as the threshold values Th0 to Th7, respectively. Then, the 17 grid mode is set in the register 1005. The processing unit 702 can recognize the processing mode by referring to the register 1005.

When storing the lattice point data in the storage unit 103 after setting the threshold value in the register 1003, the control unit 1001 obtains the bank and the memory address with reference to the threshold values Th <b> 0 to Th <b> 7, and stores the lattice point data in the storage unit 103. Is stored. The control unit 1001 has an address decoder 1004 for converting register addresses to bank and memory addresses. The address decoder 1004 of the third embodiment operates as shown in the flowchart of FIG. Steps S601 and S602 in FIG. 10 are similar to those in FIG. The address decoder 1004 compares the value A obtained by dividing the register address by 4 with the threshold set in the register 1003 (S1103, S1105, S1107, S1109, S1111, S1113, S1115, S1117). Then, the selected bank and the memory address are determined according to the comparison result (S1104, S1106, S1108, S1110, S1112, S1114, S1116, S1118). More specifically, the bank and memory address are determined as follows.
(1) When 0 ≦ A <Th0, the bank outputs 0 and the memory address outputs A (S1103, S1104).
(2) When Th0 ≦ A <Th1, the bank outputs 1, and the memory address outputs A-Th0 (S1105, S1106).
(3) When Th1 ≦ A <Th2, the bank outputs 2 and the memory address outputs A-Th1 (S1107, S1108).
(4) When Th2 ≦ A <Th3, the bank outputs 3 and the memory address A-Th2 (S1109, S1110).
(5) When Th3 ≦ A <Th4, the bank outputs 4 and the memory address outputs A-Th3 (S1111 and S1112).
(6) When Th4 ≦ A <Th5, the bank outputs 5 and the memory address outputs A-Th4 (S1113, S1114).
(7) When Th5 ≦ A <Th6, the bank outputs 6 and the memory address outputs A-Th5 (S1115, S1116).
(8) When Th6 ≦ A <Th7, the bank outputs 7 and the memory address A-Th6 (S1117, S1118).
(9) When Th7 ≦ A, the memory is not accessed.

  In the above example, the number of banks is eight. However, the present invention is not limited to this. For example, when the processing unit 702 uses only four banks, the unused registers “Th4” to “Th7” are set to “0”. As a result, the processing always branches to NO in steps S1111, S1113, S1115, and S1117, and the lattice point data can be prevented from being stored in the bank. Further, when the processing unit 702 performs processing using a larger number of banks, the storage unit 103 is configured to have a memory of 8 or more banks, and the threshold value Th8 or more is stored in the register 1003. Therefore, the versatility of the control unit can be improved.

  Further, a signal indicating a processing mode to be input to the processing unit 702 (for example, a signal indicating the number of grids) may be automatically generated from a threshold value stored in the register 1003. That is, if the threshold Th0 is 729, the control unit 1001 outputs “17GridMode = 1” to the processing unit 702 as a signal indicating that processing is performed in the 17 grid mode. On the other hand, if the threshold Th0 is 512, the control unit 1001 outputs “17GridMode = 0” to the processing unit 702 as a signal indicating that processing is performed in the 16 grid mode. By doing so, an operation equivalent to the setting of 17GridMode to the register 703 described in the second embodiment can be performed, and the setting of 17GridMode to the register 1005 can be omitted. If there are only two modes that can be set, one of them may be detected. In the present embodiment, it is only necessary to output a predetermined bit of the threshold Th0 as a signal to be processed in the 17 grid mode using the fact that bits other than the MSB become 0 when the threshold Th0 is 512. Here, as the predetermined bit, for example, a bit (excluding the MSB) that becomes 1 with a value 729, that is, any of bits 0, 3, 4, 6, and 7 can be used.

  Even when the processing unit 702 supports only one processing mode such as the 17-grid mode as in the first embodiment, the control unit 1001 proposed in the third embodiment functions effectively. Of course, in this case, it is not necessary to output a signal indicating the processing mode to the processing unit 702.

  As described above, adding a register for setting the memory map to the control unit and setting the register eliminates the need for the control unit to store the memory map at the time of design. Can be improved. Further, regarding the setting of the lookup table data, the lookup table data can be set without adding unnecessary data even if the number of data is not a power of two.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101: Control unit, 102: Processing unit, 103: Storage unit, 104, 704, 1004: Address decoder, 111: Transfer unit, 112: DRAM, 113: Input data, 703, 1003, 1005: Register

Claims (13)

A data processing apparatus that loads grid point data constituting one lookup table into a plurality of banks of memory and executes data processing,
Receiving means for receiving the grid point data to be loaded and the register address;
Conversion means for converting the register address received by the receiving means into bank designation and memory address based on the number of grid point data stored in the memory of each bank;
A data processing device comprising: storage means for storing the grid point data to be loaded in the memories of the plurality of banks in accordance with the bank designation and memory address obtained by the conversion means.   As the register address, a continuous register address is assigned to all grid point data constituting the one look-up table, and a continuous register address is assigned to a grid point data group classified into each of the plurality of banks. The data processing apparatus according to claim 1, wherein the data processing apparatus is assigned in correspondence with grid point coordinates so as to be assigned.   3. The data processing apparatus according to claim 2, further comprising assigning means for assigning a register address to lattice point data constituting the one look-up table.   The conversion means determines the bank designation and the memory address by comparing the register address with a threshold corresponding to the number of grid point data belonging to each of the plurality of banks. The data processing device according to any one of 1 to 3.   The converting means determines the bank designation and the memory address by comparing a value obtained by dividing the register address by the number of register addresses assigned to one grid point data with the threshold value. The data processing apparatus according to claim 4.   6. The data according to claim 1, wherein the memories of the plurality of banks have different capacities according to the number of grid point data belonging to each of the plurality of banks. Processing equipment.   The classification of the grid point data constituting the one lookup table into the plurality of banks is based on a combination of odd and even coordinate values of each axis constituting the grid point coordinates. The data processing apparatus according to any one of 1 to 6.   The converting means switches a method for converting the register address into a bank designation and a memory address according to instruction information indicating one of a plurality of types of lookup tables having different numbers of grids per axis. The data processing apparatus according to claim 1, wherein: The converting means determines the bank designation and the memory address by comparing the register address with a set of threshold values set based on the number of grid point data belonging to each of the plurality of banks,
The data processing apparatus according to claim 8, wherein the set of threshold values is switched according to the instruction information. The converting means determines the bank designation and the memory address by comparing the register address with a set of threshold values set based on the number of grid point data belonging to each of the plurality of banks,
Holding means for holding the set of thresholds;
8. The apparatus according to claim 1, further comprising: a changing unit that changes a set of threshold values held in the holding unit according to a lookup table loaded into the memories of the plurality of banks. The data processing device according to item. Read means for simultaneously reading a plurality of grid point data from the memory of the plurality of banks based on the grid point coordinates obtained based on the input data;
The interpolation means according to any one of claims 1 to 10, further comprising interpolation means for performing an interpolation process using a plurality of grid point data read by the reading means to obtain conversion data for the input data. The data processing apparatus described in 1. A control method of a data processing apparatus for executing data processing by loading lattice point data constituting one lookup table into a plurality of banks of memory,
A receiving process for receiving grid point data and register addresses to be loaded;
A conversion step of converting the register address received in the reception step into a bank designation and a memory address based on the number of grid point data stored in the memory of each bank;
And a storage step of storing the grid point data to be loaded in the memories of the plurality of banks according to the bank designation and the memory address obtained in the conversion step.   A program for causing a computer to execute each step of the control method according to claim 12.

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