JPH0358109A - Lsi initializing circuit - Google Patents

Abstract

PURPOSE:To obtain the LSI initializing circuit which necessitates no external supply of initializing data by constituting this circuit of a nonvolatile memory for registering an initializing data block, a block designating means, and an initializing data unit address generating means. CONSTITUTION:The subject circuit is provided with a nonvolatile memory 2 for registering plural initializing data blocks, and a block designating means 4 for supplying a superordinate address for designating an initializing data block to the nonvolatile memory 2. Also, this circuit is provided with an initializing data access means 8 consisting of an initializing data unit address generating means 6 for supplying successively a subordinate address for an initializing data unit access in each initializing data block to the nonvolatile memory 2 to which the superordinate address is supplied. In this state, an initializing data unit in a bit parallel which is read out successively by the initializing data access means 8 is converted to an initializing data unit in a bit series by a converting part 10. In such a way, initializing data can be set independently and surely.

Description

[Detailed Description of the Invention] [Table of Contents] [Summary] [Field of Industrial Application] [Prior Art] [Problem to be Solved by the Invention] Conventional circuit examples (Figs. 8, 9, and 10) Figure) [Means for solving the problem] [Example] One embodiment of the present invention (Figure 2) Another embodiment of the present invention (Figure 6) Detailed diagram of the initial setting data unit sending control circuit ( (Figure 4) [Effects] [Summary] Initial setting data for each LSI connected to a common bus can be transmitted using two LSI bins without requiring input control for each initial setting data in the initial setting data. Regarding an LSI initialization circuit that can be initialized independently, the present invention includes a nonvolatile memory for registering a plurality of initialization data blocks, and an upper address for specifying each initialization data block to be supplied to the nonvolatile memory. and initial setting data for sequentially supplying lower addresses for each initial setting data unit access in each of the initial setting data blocks to the nonvolatile memory to which the upper addresses are supplied. an initial setting data access means that is controlled from a unit address generation means;
a conversion unit having an output for connection to an initial setting data set element in the LSI, and converting a bit parallel initial setting data unit read out sequentially by the initial setting data access means into a bit serial initial setting data unit; Established and configured.

[Industrial application field]

The present invention makes it possible to independently initialize the initial setting data for each LSI connected to a common bus using two LSI bin numbers without requiring input control for each initial setting data unit in the initial setting data. Related to LSI initial setting circuit.

In an information processing device using a microprocessor, such as a digital exchange, a plurality of LSIs are connected to the microprocessor via a chip bus (7th LSI).
(see figure). One or more registers are provided in these LSIs. In order to operate the information processing apparatus, it is necessary to set initial setting data in these registers prior to operation.

[Conventional technology]

The first conventional technique for setting initial setting data in a register is to use a predetermined number of pins in a register provided for each type of initial setting data to transfer initial setting data to its corresponding register, as shown in FIG. Set to In the second technique, as shown in FIG. 9, initial setting data such as the operating mode is read from a ROM in the microprocessor/device and transferred to the LS via a chip bus.
Set in the register corresponding to the read initial setting data in I. Also, regarding initial setting data such as device number,
The initial setting data, like the initial setting data such as the operating mode, is read by the microprocessor from the ROM in the microprocessor, and is transferred to the local bus.
Similar to the first technique, the LSI
is set in the corresponding register via a predetermined number of pins provided in the register.

In the third technique, as shown in FIG. The output initial setting data is selected in a register corresponding to the initial setting data of the LSI.

[Problem to be solved by the invention]

In the first technique described above, even if each LSI is set to a chip bus, initial setting data can be set to the required registers of each LSI independently, but it is very expensive. A lot of time is spent just setting up various initial setting data. This is L
Lack of economical use of SI. In addition, the second technique mentioned above includes
Although the degree of this has been reduced, the same technical issues as the first technique remain, and since the chip bus is used to set initial setting data such as operation mode to LSI registers, It is highly likely that a fixed failure occurring in the chip bus will make it impossible to set initial setting data such as the operating mode to the LSI register.

Although the third technique has been successfully used to minimize the waste of very expensive pins for setting various initial setting data, the following problem still remains. That is,
This means that unless the initial setting circuit controls the setting of initial setting data to each shift register, initial setting data such as operation mode to the LSI register cannot be set.

The present invention was created in view of such problems, and
It is an object of the present invention to provide an LSI initial setting circuit that does not require external supply of various initial setting data while enjoying the minimization of the number of SI bins.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the first invention includes a non-volatile memory 2 for registering a plurality of initial setting data blocks, and a non-volatile memory 2 for registering a plurality of initial setting data blocks, as shown in FIG. block specifying means 4 for supplying an upper address for access to the nonvolatile memory 2, and a lower address for accessing each initialization data unit in each initialization data block sequentially; an initial setting data access means 8 consisting of an initial setting data unit address generation means 6 for supplying the non-volatile memory 2 to the non-volatile memory 2; and an output for connecting to the initial setting data set element in the LSI; The conversion unit 10 converts the bit-parallel initial setting data unit sequentially read out by the setting data access stage 8 into the bit-serial initial setting data unit. The second invention is the first invention.
As shown in the figure (part 2), there are multiple LSIs on the chip bus.
In an LSI initial setting circuit for a system configured by connecting two or more LSIs, a nonvolatile memory 3 having l or two or more blocks for registering initial setting data for two or more LSIs in corresponding divided areas; A block specifying means 4 for supplying an upper address for specifying an initial setting data block to the nonvolatile memory 3, and a lower address for accessing each initial setting data unit in the divided area corresponding to the LSI, sequentially, It has an initial setting data access means 9 consisting of an initial setting data unit address generation means 7 for supplying the upper address to the nonvolatile memory 3, and an output corresponding to the initial setting data set element in each LSI. and a conversion unit 11 that converts the bit-parallel initial setting data unit read out sequentially by the initial setting data access means 9 into a bit-serial initial setting data unit, and the conversion unit 11 converts the bit-parallel initial setting data unit sequentially read by the initial setting data access means 9 into a bit-serial initial setting data unit, After the generation of the final initial setting data unit address for the inner divided area is completed, it is updated to the read start address of the next divided area within the block specified by the block specifying means 4.

The third invention is, as shown in FIG. 1 (Part 3), in an LSI initial setting circuit for a system configured by connecting a plurality of LSIs to a chip bus, the initial setting for two or more LSIs is performed. A non-volatile memory 3 having one or more blocks for registering data in corresponding divided areas, and block specifying means 4 for supplying upper addresses for specifying each initial setting data block to the non-volatile memory 3.
, and an initial setting data unit address generating means for sequentially supplying lower addresses for accessing each initial setting data unit in the divided area corresponding to the LSI to the nonvolatile memory 3 to which the upper addresses are supplied. 7, and an output corresponding to the initial setting data set element in each LSI. a conversion unit 11 that converts into initial setting data units; and the two or more LSIs.
and a clock supply control unit l2 capable of outputting different clocks for each, and after the initial setting data unit address generating means 7 finishes generating the final initial setting data unit address for the divided area being accessed, the bronch designation is performed. The readout start address of the next divided area within the specified block is updated by the means 4, and the clock supply control section 12 is alerted to output the clock to the next LSI.

[For production]

Initial setting data in the non-volatile memory 2 or 3 designated by the block designation means 4 on an overnight basis access means 6
, or 7, the initial setting data units designated by the initial setting data unit addresses sequentially supplied from the nonvolatile memory 2 are read out in bit parallel from the nonvolatile memory 2 one after another. The bit-parallel initial setting data unit is converted into a bit-serial initial setting data unit in the conversion unit 10 or l1, and the LSI
is provided to and set there to the initialization data set element within. The clock necessary for the setting may be provided independently within the LSI, or may be supplied from the LSI initial setting circuit. In the latter case, when the initial setting data unit address generating means 7 sequentially generates lower addresses for accessing each initial setting data unit in the divided area corresponding to the LSI, a corresponding clock pulse is generated. The supply control unit 12 supplies the serial clock for each initial setting data unit in the divided area corresponding to LSi to the r-s+.

Since the initial setting data unit is supplied to the LSI in series, the number of LSI pins required for setting the initial setting data can be minimized.

To ensure that initial setting data is independently set to each LSI in a plurality of LSIs connected in parallel to a chip bus without being affected by a failure of the chip bus, while minimizing the number of LSI bins. I can do it. To obtain this effect, input control of each initial setting data setting unit in the initial setting data is not required.

〔Example〕

FIG. 2 shows one embodiment of the invention. In this figure, a ROM 21 (nonvolatile memory 2 or 3 in Figure 1) is given its read address from a switch 20 (corresponding to block designation stage 4 in Figure 1) and an initial setting data unit transmission control circuit 2l. . The upper address bits of the read address are applied from the switch 20, and the lower address bits thereof are applied from the initial setting data unit sending control circuit 21. When the switch 20 is closed, an L level (earth level) is applied, and when the switch 20 is opened, an H level is applied to the address input of the ROM 21 corresponding to the closed or opened position. The manner in which these two application levels are applied to each address input represents the upper address bit of the read address. According to the read address, ROM2. The bit-parallel initial setting data unit (DT) read from the initial setting data unit (DT) is inputted to the initial setting data unit sending control circuit 21 via the initial setting data line 24. The bit-serial initial setting data SDT output from the initial setting data unit transmission control circuit 2l is supplied to the registers 34 and 36 of the LSII 32 and LSIn 32 via the initial setting data line 26. register 3
Separate serial clocks SCKI and SCK2 are also supplied to the initial setting data unit sending control circuit 21 via the serial clock line (SCKI) 28 and the serial clock line (SCK2) 30. L
S T 1 3 2, and LSIn 32. ,teeth,
Further, processing data is exchanged with a microprocessor in an information processing device using a microprocessor via a chip bus 38. In addition, various initial setting data are stored in the ROM 2 in units of initial setting data setting for each LSI (a block is composed of two LSIs) in a registered manner as shown in FIG.
A case is shown in which the initial setting data setting unit for I is stored. ) are registered for each.

FIG. 4 shows a detailed diagram of the initial setting data unit sending control circuit 21. As shown in FIG. Differentiator circuit 40 connects power-on notification line 39 and clock input line 37 to its human power. The output of the differentiating circuit 40 is a flip-flop circuit (FF)
46 set input, counter (CTRI) 50 and counter (CTR2) 52 reset input, inverter 54
, and one human power of the OR circuit 4B.

The differentiating circuit 40, the flip-flop circuit 46, the counter 50, and the counter 52 correspond to the initial setting data unit address generation stage 7 in FIG. Counter (CTRI) 50
A clock input line 37 is connected to the clock input of the counter (CTR2) 52. The differentiating circuit 40 generates one pulse as shown in (2) in FIG. 5 when the power-on signal is input. Flip-flop circuit (FF) 4
6 is sent by said one banores. The output of the free flip-flop circuit (FF) 46 is output by a counter (
CTRl) 50 to the enable input (EN). Carry output (Co) of counter (CTRI) 50
is the enable input (EN) of the counter (CTR2) 52
connected to. The count output (QO, Ql, . . . Q7) of the counter (CTR2) 52 is connected to the lower address input of the ROM 2 via the lower address line 22. Carry output (C○
) is connected to the reset input of the flip-flop circuit (FF) 46. The output Q7 of the counter (CTR2') 52 is directly connected to one input of an AND circuit 58 via an inverter 54, and the output Q7 of the counter (CTR2) 52 is directly connected to one input of an AND circuit 60. The clock pulse of the clock input line 37 is supplied to the other input of the AND circuit 58 and the AND circuit 60 via the inverter 56. Inverters 54 and 56 and AND circuits 58 and 60 correspond to the clock supply control section 12 in FIG. The outputs of the AND circuit 58 and the AND circuit 60 are connected to the serial clock lines (SCK
I) 28 and a serial clock line (SCKI) 30. Shift register 25 (conversion unit 1 in FIG.
Corresponds to 0.11. ) is the initial setting data unit set manual DO to D7 in ROM 2. The read data outputs QO to Q7 are connected. shift register 25
A clock input line 37 is connected to the clock input (CP) of , and an output of an OR circuit 48 is connected to the byte (initial setting data unit) set control manual L.

The shift-out output Q of the shift register 25 is connected to the initialization data line 26 described with reference to FIG.

The operation of the above-mentioned configuration circuit will be explained below.

It is assumed that the initial setting data setting unit for the LSI to be initialized is, for example, an initial setting data unit starting from address XO (see (7) in FIG. 5) as shown in FIG. The X in the address XO indicates its upper address, and its O indicates its lower address. In that case, the switch 20 is set so that the upper address X can be supplied to the ROM 2. When the power-on signal (see (2) in Figure 5) is input, a pulse (see (3) in Figure 5) is generated from the differentiating circuit 40, and the flip-flop circuit (FF) 46 is set. ((4) in Figure 5)
), counter (CTRI) 50 and counter (CT
R2) 52 is reset ((3) and
(See (5) in the figure). At that time, counter (CTR2) 5
The initial address O for the lower address output from switch 20 is stored in the ROM together with the upper address X from switch 20.
2, and its ROM 2. Address of XO
The initialization data unit (eg, byte) read from the shift register 25 is sent to the shift register 25. The initial data setting unit set in the shift register 25 is output in bit series (see (7) in Fig. 5) by a clock pulse from the clock input line 37 (see (1) in Fig. 5), and the initial setting is performed. It is supplied to register 34 via data line 26. This bit-serial initialization data unit is set in the register 34 by a serial clock pulse SKCI supplied to the register 34 as follows.

The serial clock pulse SKCI is supplied to the inverter 54.
It is output from an AND circuit 58 which receives the output Q7 of the counter (CTR2) 52 which has passed through the inverter 56 and the clock pulse from the clock input line 37 which has passed through the inverter 56.

Then, at the time when the last bit of the first initialization data unit is shifted out from the shift register 25, a pulse is output from the counter (CTRI) 50. A counter (CTR2) 52 receiving this pulse counts up by one in response to the clock pulse on clock input line 37 and generates a lower address 1 for the next initialization data unit. This lower address 1 and upper address
The subsequent processing operations for the next initialization data unit read from ROM2+ for address X1 consisting of are the same as those described for address XO.

Further, the processing operations for the first and second initialization data units as described above apply in exactly the same manner to the third and subsequent initialization data units.

The processing operation is such that the count of the counter (CTR2) 52 becomes "1" in all outputs QO to Q6, and the setting processing of all initial setting data units for the lower half (with respect to addresses) within one block is completed. Then, in response to the next clock pulse, when the outputs QO to QO6 all become ゜゜0'゛ and the output Q7 becomes ゜゜"1", the serial clock pulse that had been supplied to the LSI until then is transferred to the AND circuit 60. is output as a serial clock pulse scK2 (see (8) in FIG. 5) from the switch 20 to the ROM 2. At this time, the upper address supplied from the switch 20 to the ROM 2 is set to
The operation of the counter (RI) 50 and the counter (CTR2) 52 is
Since the serial clock pulse supplied to SI is generated in the same way as the serial clock pulse SCKI, reading of each initial setting data unit from the ROM 21 and shifting out of each initial setting data unit from the shift register 25 is also possible. Also, the same is true. The read start address in this case is X127. The last address supplied to the ROM 21 when this serial clock pulse SCK2 is output is shown as X255 in (7) of FIG. In response to the clock pulse after the last address is output, a carry signal is output from the counter (CTR2) 52 and supplied to the flip-flop circuit (FF) 46, causing the flip-flop circuit (FF) 46 to be reset.

This completes the reading of one block of the ROM 21. Reading of other blocks is also carried out as described above.

FIG. 6 shows another embodiment of the invention. This embodiment is a ROM2. in one embodiment of the present invention shown in FIG. The block configuration of is used as the initial setting data for one LSI, and its access circuit (corresponding to the initial setting data unit address generation means 6 in FIG. 1) is set as the count value of the counter 52 (QO to Q7) in FIG. The counter 50 should be used in conjunction with the differentiating circuit 40, the flip-flop circuit 46, the counter 50, and the OR circuit 48. There was only one thing. Therefore, in the embodiment of FIG. 6, there is no need to provide the inverter 54, AND circuit 58, and AND circuit 60 as shown in FIG.

In the above embodiment, the case where the types of initial setting data in the block of ROM2+ are 2 and 1 has been explained, but the types may be 3 or more.
It should be obvious from the above. In that case, the registration capacity of the block of ROM2 needs to be sufficient to register three or more initial setting data, and the number of initial setting data units in one type of initial setting data must be set to the above-mentioned number. If the case is the same as the example, it is necessary to change the structure of the AND circuit 58 and the AND circuit 60 as follows. The purpose is to change the serial clock pulse output circuit so as to identify each of the three or more types and output the output of the inverter 56 as a serial clock pulse in accordance with the identification.

Further, the clock for setting the initial setting data to the LSI does not necessarily have to be supplied from the LSI initial setting data.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
To ensure that initial setting data is independently set to each LSI in a plurality of LSIs connected in parallel to a chip bus without being affected by a failure of the chip bus, while minimizing the number of LSI pins. I can do it. To obtain this effect, input control of each initial setting data setting unit in the initial setting data is not required.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a diagram showing one embodiment of the present invention, and Fig. 3 is a block diagram of the principle of the present invention.
FIG. 4 is a detailed diagram of the initial setting data unit sending control circuit, FIG. 5 is a diagram showing the initial setting data unit sending timing, and FIG. 6 is another example of the present invention. FIG. 7 is a diagram showing the configuration of a system in which multiple LSIs are connected in parallel to a chip bus; FIG. 8 is a diagram showing the first conventional LSI initialization circuit; FIG. Figure 10 shows the conventional LSI initial setting circuit of No. 2.
The figure shows a third conventional LSI initial setting circuit. 1, 2, 4 and 6, 2.3 is a non-volatile memory (ROM2+), 4 is a block specifying means (switch 20), and 6.7 is an initial setting data unit address generation means ( Differential circuit 40, flip-flop circuit 46
, counters 50, 52), 8 is an initial setting data access means, 10.11 is a conversion section (shift register 25), and 12 is a clock supply control section (inverters 54, 56, AND circuits 58, 60).

Claims (3)

[Claims] (1) A non-volatile memory (2) for registering a plurality of initial setting data blocks, and a block specifying means for supplying an upper address for specifying each initial setting data block to the non-volatile memory (2). (4), and an initial setting for sequentially supplying lower addresses for each initial setting data unit access in each initial setting data block to the nonvolatile memory (2) to which the upper addresses are supplied; It has an initial setting data access means (8) consisting of a data unit address generation means (6), and an output for connecting to an initial setting data set element in the LSI, and the initial setting data access means (8) sequentially An LSI initialization circuit comprising a conversion section (10) that converts a bit-parallel initialization data unit to be read into a bit-serial initialization data unit. (2) In an LSI initial setting circuit for a system configured by connecting multiple LSIs to a chip bus, one or more blocks are provided for registering initial setting data for two or more LSIs in corresponding divided areas. a non-volatile memory (3) having a non-volatile memory (3); a block specifying means (4) for supplying an upper address for specifying each of the initial setting data blocks to the non-volatile memory (3); Initial setting data comprising initial setting data unit address generation means (7) for sequentially supplying lower addresses for each initial setting data unit access to the nonvolatile memory (3) to which the upper addresses are supplied. and an access means (9), which has an output corresponding to the initial setting data set element in each LSI, and converts a bit-parallel initial setting data unit read out sequentially by the initial setting data access means (9) into a bit-serial initial setting. Conversion unit (11) that converts into data units
and after the initialization data unit generation means (7) finishes generating the final initialization data unit address for the divided area being accessed, the next one in the block specified by the block specification means (4). An LSI initial setting circuit that is updated to a read start address of a divided area. (3) In an LSI initial setting circuit for a system configured by connecting multiple LSIs to a chip bus, one or more blocks are provided for registering initial setting data for two or more LSIs in corresponding divided areas. a non-volatile memory (3) having a non-volatile memory (3); a block specifying means (4) for supplying an upper address for specifying each of the initial setting data blocks to the non-volatile memory (3); Initial setting data comprising initial setting data unit address generation means (7) for sequentially supplying lower addresses for each initial setting data unit access to the nonvolatile memory (3) to which the upper addresses are supplied. and an access means (9), which has an output corresponding to the initial setting data set element in each LSI, and converts a bit-parallel initial setting data unit read out sequentially by the initial setting data access means (9) into a bit-serial initial setting. Conversion unit (11) that converts into data units
and a clock supply control unit (12) capable of outputting separate clocks to the two or more LSIs, the final initial setting for the divided area being accessed by the initial setting data unit generating means (7). After the data unit address has been generated, it is updated to the read start address of the next divided area within the block specified by the block specifying means (4), and the clock supply control section (12) supplies the clock to the next LSI. An LSI initial setting circuit characterized by output.