JPS638983Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an input/output data control circuit used in a magnetic card reader or the like.

For example, when processing asynchronous input data in a magnetic card reader (hereinafter referred to as MCR) for a credit card, etc., conventionally, a buffer is not provided between it and the CPU, and even if it is provided, a 1-bit buffer is provided. It was moderately hot.
However, due to multi-program processing, the CPU
In full-duplex MCRs that send and receive large amounts of data between
At around 1 buffer, the load on the CPU is large. Traditionally, the method used to solve this problem is
It is conceivable to use a FiFo (first-in, first-out) element. That is, it temporarily stores sequentially input data and sends it to the CPU etc. in order from the oldest data. However, the conventionally used FiFo
This poses a problem in terms of reliability because the element can malfunction, such as reading errors in data, depending on temperature conditions and the like.

Furthermore, although there are FiFos that use a CPU and memory, they require two address counters, one for writing and one for reading, making them large, and they have the disadvantage of being complicated to control and putting a load on the CPU.
Furthermore, although there is a memory that is equipped with an address counter that has read/write functions for one memory, this does not maintain the order of data. In other words, with conventional technology, data ordering is maintained, the load on the CPU is small, and moreover, it is possible to reduce the size of the data.
I was unable to configure FiFo.

The present invention solves these conventional problems.It has a simple configuration that can perform virtually the same operation as a FiFo element, reduces the burden on the CPU, and provides a small input/output data buffer. The purpose is to provide circuits.

In other words, the circuit of the present invention includes a shift register that can store a plurality of input data, and a counter that counts up the number of input data input to the shift register and counts down by outputting the input data. . and,
The oldest data in the shift register (first-in, first-in, etc.)
first out).

Hereinafter, the present invention will be explained in more detail along with examples. The drawing is a circuit diagram of the present invention in an embodiment. In the figure, 1 is a shift register, 2 is an up-down counter, 3 is a multiplexer, 4 is a flip-flop circuit, and 5 is an interrupt latch circuit.

Now, when the asynchronous data ASID that can be read and output from the MCR is written into the shift register 1 by one clock signal, the up-down counter 2 counts up by one by this clock signal. As a result, the interrupt latch circuit 5 is activated, and the signal I/O which requests the CPU to read data is activated.
Request iRQ is output. In response to an I/O request, the CPU generates a read pulse RP to read data. In this case, the up-down counter 2 instructs the multiplexer 3 to read out the data stored in the shift register 1. That is, the count value of the counter 2 becomes an address signal, and the first address signal of the shift register 1 is sent to the multiplexer 3.
The bit data is input to the flip-flop 4. The data is sent to the CPU via the flip-flop circuit 4 and processed by the program. On the other hand, if the second data is input before the interrupt processing is performed on the above data, the program processing will not be able to catch up. In such a case, upon arrival of the second data, the up-down counter 2 further counts up by one, and the second data is stored in the first bit position of the shift register 1. The first data is then transferred to the second bit position of shift register 1. The count number of up-down counter 2 is "2" at this point due to the up-count, so the count number "2" indicates the position of the oldest data currently existing in shift register 1. become. Therefore, the multiplexer 3 selects this oldest data, and the first data is still output to the flip-flop circuit 4.
The shift register 1 is capable of storing up to eight pieces of such asynchronous input data. Therefore, data is stored in the shift register 1 as the clock signal is input. For example, if the 5th clock signal is input and no data is read during that time, the first data will be stored in the 5th position in the shift register 1. I'm coming. At this time, the count number of the up-down counter 2 is "5", and the data selected by the multiplexer 3 is still the first data. Next, when the first data is read by the read pulse RP from the CPU, the read/write signal R/W to the up-down counter 2 changes from the "write" state to the "read" state. The updown counter 2 then decrements its contents by one. Therefore, the count number becomes "4" and the second data becomes the next output of the multiplexer 3. Interrupt processing is then executed for the second data. In this way, the interrupt processing progresses and all the input data in shift register 1 becomes read data RD.
When read as , up-down counter 2
returns to the initial state, that is, the count value 0 state. This terminates the operation of the interrupt latch circuit.
Reading ends.

As described above, the circuit of this invention is an asynchronous MCR.
It functions as a FiFo buffer for input data such as, and can be used with conventional programs without any changes. That is, it is compatible with previous programs. Moreover, in the case of MCR, even when performing multi-program processing, simultaneous reading and writing operations are not performed, so the present invention can be used in a wide range of applications by simply considering the peripheral circuitry. Of course, it goes without saying that the circuit of the present invention can be used not only for MCR but also for general input data control circuits, whether asynchronous or synchronous.

[Brief explanation of the drawing]

The drawing shows a block diagram of an embodiment of the invention. In the figure, 1 is a shift register, 2 is an up-down counter, and 3 is a circuit for reading from the shift register.

Claims (1)

[Claims for Utility Model Registration] A shift register that can shift and store multiple input data, a read/write signal line that instructs writing and reading to this shift register, and an operation according to the signal state of the read/write signal line. and an up-down counter that counts up each time data is input to the shift register and counts down the up-counted value when input data is output, and the contents of the counter correspond to the shift position of the shift register. An input/output data control circuit comprising: a circuit that receives an address signal and selectively reads accumulated data at a shift position indicated by the address signal from the shift register.