JPS6217876Y2 - - Google Patents

Description

[Detailed description of the invention] (Related applications) This application is filed in US Patent No. 4151598 (Japanese Patent No. 1263901
No.) This is related to "priority designation device for memory controller."

A. Technical field to which the invention pertains The present invention relates to a memory system used in a data processing device, and more particularly, to a memory system for use in a data processing device, and in particular to a memory system used in a data processing device to store commands, commands, or The present invention relates to a memory controller stack device that accepts and stores data.

B. Description of the Prior Art Modern data processing systems incorporate various subsystems to perform data manipulation, storage, and communication functions. Such systems include, for example, a central processor, memory, a plurality of input/output (I/O) devices, and a controller.
Such data processing systems vary widely in configuration, ie, various functionalities are arranged in different subsystems according to specific design criteria. Similarly, the interface circuits required for communication between the various subsystems differ in both their functionality and operation.

Typically, a central processor operates on data according to a series of decodable instructions called a program. These program instructions are sequentially retrieved by the processor and stored in the storage device along with the data to be manipulated.

Although there are several known types of such storage devices, the most commonly used main storage devices are random access devices with separately addressable storage locations, and Each of the memory locations provides storage for words containing particular fields that may consist of data and/or instructions and may be used in various operations. Generally, when a processor needs data or instructions, it generates a store cycle to provide this address to memory for retrieving the data or word stored at that address.

The sequence of instructions that make up a program is typically loaded into memory at the beginning of each operation and occupies a block of memory, which block typically must not be disturbed or modified until the program is complete.
Data to be manipulated by the processor according to the stored instructions is stored in other parts of the memory;
Searched and replaced according to program instructions.

Communication between the outside world and the data processing system is typically provided by magnetic tape handlers, paper tape readers, punchers, etc.
This is accomplished through the use of multiple I/O devices, including devices such as card readers and remote terminals. To control the transfer of information between I/O devices,
An input/output controller is provided that couples various I/O devices to the processor. The input/output controller coordinates the flow of information to and from the various I/O devices and provides priority when one or more I/O devices attempt to communicate with other parts of the system. This I/O device is typically electromechanical in nature and is therefore characterized by a much slower operating speed than other parts of the data processing system.
The input/output controller provides a buffer so that other parts of the processing system can proceed at their normal speed. In many applications, it is advantageous to use one or more processors and one or more memories. Similarly, such systems typically require a large number of I/O devices and therefore many input/output controllers.

A memory controller is provided to coordinate communications between the processor, storage, and I/O controller. This device receives requests for access to memory as well as specific communication requests for other subsystems. The memory controller coordinates the execution of operations and transfer of information and also provides a means for specifying priorities when requests for access to memory are generated by one or more subsystems.

A typical data processing system includes one memory controller, but multiple computer configurations use several memory controllers.

In environments where more than one memory controller is used, each memory controller is independent of the other and operates simultaneously to provide parallelism in memory system access. Each memory controller temporarily stores requests from processors and input/output controllers and typically services these subsystems according to some priority scheme. Data transfer between various communication devices and memory controllers is in word format,
For example, it is 40 bits. A typical data processing system using a memory controller is described in US Pat. No. 3,413,613, "Reconfigurable Data Processing System."

Instructions and/or instructions and/or data transferred to the memory controller are
The information is received and temporarily stored in a stack of registers until the appropriate destination device is available to process the information. Once stacked, instructions or commands are generally forwarded to the destination device on a first-in, first-out basis. The write counter determines which register on the stack receives the input information, and the read counter selects the register whose contents are then sent to the destination device. The presence of a command in the stack is normally detected by comparing the contents of the write counter with the contents of the read counter. If their contents are not equal, this indicates that the stack contains information to be sent. A write counter is advanced when a request is received by the memory controller, and a read counter is advanced when information is sent from the stack to the destination device. If the destination device corresponding to the next command to be read from the stack is busy,
Other commands occupying positions lower on the stack cannot be forwarded even if their corresponding destination devices are free. Thus, a busy destination device may effectively block commands destined for a free device. This is clearly inefficient and results in undue delays in a technology where speed is paramount.

Furthermore, because the stack has a finite length, the write counter will fill all available storage locations in the stack and cycle through itself, causing the contents of the stack's storage locations to be transferred to its destination device. There is a risk of writing new information to the memory location before it is transferred. If this overflow occurs, the contents of the register(s) in question will be lost, resulting in a system error. Using the methods described above, it is difficult to determine when the stack becomes full with information that has not yet been transferred to each destination device. Furthermore, because this arrangement operates sequentially, it is difficult to determine the actual frequency of use of the stack, or to indicate throughput.

C. OBJECTS OF THE INVENTION It is an object of the invention to provide a stack arrangement for a memory controller in which overflow errors are substantially overcome.

Another object of the invention is to enable easy determination of stack throughput with the stack apparatus of the invention.

D Summary of the invention According to the broad characteristics of the invention, the invention is ordered;
a detection device for determining the lowest unoccupied storage level, i.e. the lowest level number, in a multi-level storage stack consisting of a number of registers which are sequentially numbered for identification; input data to a storage level in a multi-level storage stack comprising a detection device and an enabling device coupled to the stack for loading into the lowest unoccupied storage level (hereinafter simply referred to as level); A storage device is provided.

The foregoing and other objects of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

E. DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a data processing system with a single memory controller configuration. This data processing system includes a data processor 2, storage devices 4 and 6, an input/output controller 10, and a plurality of I/O devices 12, 14, and 16.
The processor, I/O controller and memory are interconnected by a memory controller 8 which controls access to storage devices 4 and 6 and also controls communications between processor 2 and/or I/O controller 10. ing. As previously mentioned, memory controller 8 acts as a data processing coordinator to perform certain functions of its own as well as oversee communication between systems. The stack device is connected to a memory controller 8 for accepting and temporarily storing information of commands, commands, and data destined for one or both of the storage devices 4 and 6 which are unavailable. It is provided.

FIG. 2 is a functional block diagram of a stacking device according to the present invention. Referring to FIG. 2, a four level stack 42 is shown. In this regard, it should be noted that the stack 42 can be of any length;
The use of four levels is for illustration purposes only. Stack 42 actually receives command addresses and data provided for each level of the stack, although only the input for level 0 is shown for simplicity. As soon as the applicable receiving device becomes available, the contents of the corresponding level of the stack are transferred, and if multiple receiving devices become available at the same time, pending U.S. patents filed on the same date as this application. No. 4151598 (Japanese Patent No. 1263901
Items that have been in the stack longer are transferred to the receiving device according to the priority system, which is the subject of ``Priority Designation Device for Memory Controllers.'' Since this is not the subject of this invention, it will not be further explained.

Each level of the stack has an active flip-flop associated with it. In FIG. 2, these are flip-flops 20, 22, 2.
4,26. When a command, address and/or data is stored at one level in the stack, its associated level busy flip-flop is set. When data is read from a corresponding level of the stack by a receiving device, a signal is generated by the receiving device that resets the corresponding level busy flip-flop. Level in use flip-flop 20,
The outputs of 22, 24, and 26 are applied to the inputs of a level-in-use decoder 28, which determines the lowest level (i.e., lowest level number) of the stack that is not occupied by any built-in logic. . If all levels are occupied, that is, all level busy flip-flops are set, the level busy decoder 28 generates a stack busy signal.
This is forwarded to the requesting device, informing the requesting device that the request cannot be processed or accepted at this time.

The output of level busy decoder 28 is used in two ways. First, this output is fed back to the input of multiplexer 18. Requests received from requesting devices are similarly applied to multiplexer 18, which produces an output on the appropriate line to set the level busy flip-flop to the lowest unoccupied level in the stack.
Second, the output of level busy decoder 28 is provided to stack address generator 32.
Address generator 32 generates an enable signal, which is combined with the request signal to enable command, address and/or data entry to the lowest unoccupied level of the stack. This is done via AND devices 34, 36, 38, 40.

As mentioned above, when a stack overflow condition occurs, it is either so frequent that additional higher levels should be added to the stack, or conversely, it is used so infrequently that the current higher levels in the stack are It is desirable to obtain an indication of the frequency of use of a stack in order to determine whether it should be deleted.
This can be accomplished by coupling the output of the level busy flip-flop to a logic device shown as throughput indicator 30 in FIG. This device is the logical device that represents the highest rel in the occupied stack.
The throughput indicator 30 generates a signal that is connected to a stack level controller, which adds and subtracts levels to the stack, and which does not form part of the present invention.

Referring now to FIG. 3, a detailed logic diagram of a stacking device according to the present invention is shown. As in FIG. 2, the stack is limited to four levels solely for convenience of explanation. Levels 0, 1, 2, and 3 of stack 42 are connected to AND devices 66 and 6, respectively.
It becomes usable by the outputs of 8, 70, and 72.
Again, as shown in FIG. 2, commands and/or data are shown as being provided to the first level only. However, it should be understood that command and address data are provided at each level in the stack as well.

Associated with each stack level is a level busy flip-flop. When flip-flop 44 is set, it indicates that level "0" is occupied. flipflop 46,4
8 and 50 perform similar functions for levels 1, 2, and 3, respectively.

AND logic 52, 54, 56, 58 serves to identify the lowest unoccupied level in the stack. For example, AND device 52
is given the Q output of flip-flop 44 on one of its inputs and the output of flip-flop 46 on the other. Therefore, the output of AND device 52 will be high only if level "0" is occupied and level "1" is not. Similarly,
AND, gate 54 outputs when levels "0" and "1" are occupied and level "2" is not occupied.
The level is coupled to the output side of the flip-flop in use to yield f2. The output (f3) of AND device 56 indicates that all levels of the stack except the last level are occupied. These functions (f1, f2, f3) are connected to AND devices 76, 78, respectively.
It is fed back and coupled to the input side of 80. The access request is coupled to second inputs of AND devices 74, 76, 78, 80. Thus, when a request is received and it is determined which is the lowest unoccupied level in the stack, the appropriate level busy flip-flop is set. for example,
If level "1" is the lowest unoccupied level in the stack, f1 goes high causing AND device 76 to send the request to the set input of flip-flop 46. If level "2" is the lowest unoccupied level, f2 causes AND device 78 to send a request to the set input of level busy flip-flop 48. Similarly, if level "3"
If is the lowest terminal occupancy level, f3 gates the request signal to the set input of flip-flop 50.

AND logic device 74 has a first input connected to the request signal and a second input connected to the output of flip-flop 44, which is a level busy flip-flop associated with the first level of the stack. Therefore, if flip-flop 44 is not set to indicate that a level "0" in the stack is not occupied, the request signal is
AND gate 74 is gated to set flip-flop 44.

AND logic device 58 inputs the input level to the Q of each of flip-flops 44, 46, 48, and 50.
is coupled to the output. Therefore, AND device 58
produces an output only when all level-occupied flip-flops are set, ie, when all levels of the stack are occupied. This output is forwarded to the requesting device to notify it that the request cannot be processed. This prevents overflow errors.

At the same time as setting the flip-flop in use at the appropriate level, the command, address and/or
Data is accepted and stored in the lowest unoccupied level of the stack corresponding to its set level busy flip-flop. This is done as follows.

AND device 60 has its inputs coupled with the outputs of AND devices 52 and 56, namely f1 and f3.

AND device 62 has its inputs coupled with the outputs of AND devices 54 and 56, namely f2 and f3. Thus, the four possible combinations (00, 01, 10, 11) of outputs produced by AND devices 60 and 62 are:
It is decoded at address generator 64, which is a 2-bit decoder. When the address corresponding to level "0" of the stack is decoded, an enable signal is transmitted on line 88 to AND device 66, which clocks the command, address and/or data to level "0". It enables the actual request signal to be applied to its second input in order to do so. Similarly, addresses corresponding to levels 1, 2, and 3 result from generation of enable signals by address register 64 on lines 86, 84, and 82, respectively. When information at a certain level of the stack is sent to its appropriate destination device, a reset signal is generated by the destination device on line 91.
via the corresponding level to the busy flip-flop to reset it. Although there is only one line as shown, it will be clear that each destination device has separate access to each level of busy flip-flops so that each can be reset without affecting the others.

By monitoring the outputs of the AND devices 52, 54, 56, 58, an indication of the frequency of use or throughput of the stack to determine whether additional levels should be added to the stack or the current level should be deleted. is obtained. Furthermore, if one level of the stack is failing, bypassing this level will prove to be a relatively simple matter. This can be done by simply forcing the busy flip-flops of the relevant level into the set state.

Although the invention has been described with reference to particularly preferred embodiments, it will be understood that changes may be made in form and detail without departing from the spirit and scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing system using a memory controller according to the prior art, FIG. 2 is a block diagram of a stack device for a memory controller according to the present invention, and FIG. 3 is a block diagram of a stack device for a memory controller according to the present invention. Figure 3 is a more detailed logic diagram of the device; 2...Data process, 4, 6...Storage device, 8...Memory controller, 10...
I/O controller, 12, 14, 16...I/
O device, 18...multiplexer, 20, 22,
24, 26...Flip-flop, 28...Level in use decoder, 30...Throughput indicator, 32...Stack address generator, 34, 36, 38, 40, 52, 54, 5
6, 58, 60, 62, 66, 68, 70, 7
2, 74, 76, 78, 80...AND device, 4
2...Stack, 44, 46, 48, 50...Flip-flop, 64...Address generator, 82, 84, 86, 88, 91...Line.

Claims (1)

[Claims for Utility Model Registration] (1) A memory controller coordinates the transfer of information between at least one storage device and at least one requesting device, and the requesting device provides information. In a data processing system of the type that requests the transfer of information to said storage device at the same time, a stack device for temporarily storing said information when said at least one storage device is unavailable. a plurality of separate storage levels each capable of storing information respectively associated with each of said requests; and associated with each said storage level, said storage level being configured to a display device for displaying information; and a device for loading said information into the lowest unoccupied storage level in response to the state of said display device. (2) said device for loading comprises: a decoding device coupled to said display device for determining a lowest unoccupied storage level; and a decoding device coupled to said display device for determining a lowest unoccupied storage level; a generating device coupled to the device; an enabling device coupled to the generating device for loading the information into the lowest unoccupied storage level; and the display associated with the lowest unoccupied storage level. and a device coupled to said decoding device for changing the device to reflect its occupancy status. (3) said display device is set when information is loaded into its associated storage level and reset when information in its associated storage level is sent to said at least one storage device; 3. A stacking device as claimed in claim 2, characterized in that it comprises a storage level-in-use flip-flop associated with each of the levels. (4) said decoding device having a logic device having an input coupled to an output of said storage level occupied flip-flop, said logic device producing a first output indicative of the lowest unoccupied storage level; ,
the second when all of the storage levels are occupied;
4. The stack device according to claim 3, wherein the stack device generates an output of . (5) the stack comprises first, second, third and fourth storage levels, and the display device comprises first and second storage levels;
and a third and fourth storage level occupied flip-flop, the logic device indicating that the second storage level is the lowest unoccupied storage level; a second device that displays that the storage level is the lowest unoccupied storage level; a third device that displays that the fourth storage level is the lowest unoccupied storage level; 5. A stack device according to claim 4, further comprising a fourth device for indicating that the first, second, third and fourth storage levels are occupied. (6) The first, second, third, and fourth devices are
The stack device according to claim 5, which is an AND device. 7. A stack device according to claim 4, wherein said changing device includes logic device responsive to said first output for setting a busy flip-flop to an appropriate storage level.