JPS61650U - Information processing device with multiple virtual memory method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a conventional multiple virtual memory type information processing device, and FIG. 2 is a block diagram showing an embodiment of this invention. In the figure, 1 is an STP stack;
2 is the next entry designation counter, 3 is the search counter, 4
is the STP valid/invalid flag, 5 is the I flag control circuit, 6 is the counter comparator, 10 is the STP register, 11 is the comparator, 20 is the next entry designation counter input signal, 21 is the next entry designation counter output signal, 22 is s 'rp register input signal, 23 is STP register output signal, 24 is ST
P stack output signal, 25 is STP match signal, 26 is search counter output signal, 27 is I flag output signal, 28
29 is an I flag control circuit output signal, and 29 is a counter completion signal. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] In an information processing device using multiple virtual memory, a table pointer word stack, an entry designation counter that specifies the next position in the table pointer word stack to be registered, a new table pointer word register, and a new table pointer word register are provided. A table pointer comparator that compares stack read data, and a search counter that searches the entire area of the table pointer word stack by counting up the stack number in response to a register input signal and stopping counting based on flag detection. , a counter comparator that compares the values of the entry designation counter and the search counter, and a flag indicating whether or not the table pointer word stack for each entry is invalid based on a match signal from the counter comparator and a match signal from the table pointer comparator. 1. An information processing device using a multiple virtual storage system, comprising: a flag control circuit for determining a table pointer word; and a flag control circuit for determining a table pointer word.