JPH0172648U - - Google Patents

Info

Publication number
JPH0172648U
JPH0172648U JP1987166281U JP16628187U JPH0172648U JP H0172648 U JPH0172648 U JP H0172648U JP 1987166281 U JP1987166281 U JP 1987166281U JP 16628187 U JP16628187 U JP 16628187U JP H0172648 U JPH0172648 U JP H0172648U
Authority
JP
Japan
Prior art keywords
storage means
data
instruction word
delimiter
data storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987166281U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987166281U priority Critical patent/JPH0172648U/ja
Priority to US07/258,153 priority patent/US4975835A/en
Priority to CA000580309A priority patent/CA1308490C/en
Priority to DE3855066T priority patent/DE3855066T2/en
Priority to EP88117758A priority patent/EP0318699B1/en
Priority to KR1019880014095A priority patent/KR920000417B1/en
Publication of JPH0172648U publication Critical patent/JPH0172648U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の機能ブロツク図、第2図、
第3図は一実施例を示し、第2図は全体のブロツ
ク回路図、第3図は指定デリミタあるいは設定バ
イト数に応じて処理されるデータ単位を説明する
為の図である。 11……インストラクシヨンレジスタ、12…
…命令デコーダ、13……アドレス発生回路、1
4……デリミタ検出回路、15……制御回路、1
6……リードバツフア、18……ALU、22…
…カウンタ、23……ゼロ検出回路、MM……主
記憶装置。
Figure 1 is a functional block diagram of this invention, Figure 2,
FIG. 3 shows one embodiment, FIG. 2 is an overall block circuit diagram, and FIG. 3 is a diagram for explaining data units processed according to a specified delimiter or a set number of bytes. 11...Instruction register, 12...
...Instruction decoder, 13...Address generation circuit, 1
4... Delimiter detection circuit, 15... Control circuit, 1
6...Read buffer, 18...ALU, 22...
...Counter, 23...Zero detection circuit, MM...Main memory.

Claims (1)

【実用新案登録請求の範囲】 データ及びこのデータの区切りを示すデリミタ
を記憶するデータ記憶手段に対するアドレスを生
成するアドレス生成手段と、 命令語及びこの命令語に対応して指定されたデ
リミタを記憶する命令語格納手段と、 この命令語格納手段に記憶されている命令語を
解読し、前記アドレス生成手段のアドレス指定に
よつて前記データ記憶手段から順位読み出される
データを前記命令語にしたがつて処理する制御手
段と、 前記命令語格納手段に記憶されているデリミタ
と対応するデリミタが前記データ記憶手段から読
み出されたことを検出した際に検出信号を出力す
る検出手段と、 前記データ記憶手段から読み出されたデータの
数を計数する計数手段と、 を備え、前記制御手段は前記検出信号が入力され
た際あるいは前記計数手段で特定値が計数された
際に、前記命令語にしたがつた処理を終了するこ
とを特徴とする演算処理装置。
[Claims for Utility Model Registration] Address generation means for generating an address for a data storage means for storing data and delimiters indicating the divisions of the data, and storing a command word and a delimiter designated corresponding to the command word. instruction word storage means; decoding the instruction word stored in the instruction word storage means, and processing data read out in order from the data storage means according to the address specification of the address generation means according to the instruction word; a control means for outputting a detection signal when detecting that a delimiter corresponding to a delimiter stored in the instruction word storage means has been read from the data storage means; and a detection means for outputting a detection signal from the data storage means. a counting means for counting the number of read data, and the control means is configured to control the control means according to the command word when the detection signal is input or when the specific value is counted by the counting means. An arithmetic processing device characterized by terminating processing.
JP1987166281U 1987-10-30 1987-10-30 Pending JPH0172648U (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP1987166281U JPH0172648U (en) 1987-10-30 1987-10-30
US07/258,153 US4975835A (en) 1987-10-30 1988-10-14 Variable length data processing apparatus for consecutively processing variable-length data responsive to one instruction
CA000580309A CA1308490C (en) 1987-10-30 1988-10-17 Operation apparatus
DE3855066T DE3855066T2 (en) 1987-10-30 1988-10-25 Surgical device for processing data of arbitrary length
EP88117758A EP0318699B1 (en) 1987-10-30 1988-10-25 Operation apparatus processing data of arbitrary length
KR1019880014095A KR920000417B1 (en) 1987-10-30 1988-10-28 Arithmetic processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987166281U JPH0172648U (en) 1987-10-30 1987-10-30

Publications (1)

Publication Number Publication Date
JPH0172648U true JPH0172648U (en) 1989-05-16

Family

ID=31453527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987166281U Pending JPH0172648U (en) 1987-10-30 1987-10-30

Country Status (1)

Country Link
JP (1) JPH0172648U (en)

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