KR0171771B1 - Address bus lock control apparatus of computer system - Google Patents

Abstract

The present invention relates to a lock controller, comprising: a system bus matching unit 21 for interfacing with a system bus; Receives address and byte enable information from the system bus matching unit and stores them according to the load signal or deletes them according to the delete signal, and newly inputs them through the address and byte enable and the system bus that have been previously If the address and byte enable signal match, the same signal will be output.If the address already has the same address as the newly input address through the system bus, but the byte enable signal is not the same, the over signal will be activated. A lock buffer 22 outputting a flag signal and outputting a flag signal that is activated when an address is stored in the lock buffer; If the transmission type is interlock read from the system matching unit, if the transmission type is interlock read, the load signal is output to search the flag bit of the lock buffer and store the corresponding address at the bottom of the empty buffer, and the lock busy (lock_busy) The lock control signal 23 is generated if the lock type signal is transmitted. If the transfer type is interlock write, the lock control unit 23 for outputting a delete signal to empty the buffer is compared. If the lock buffer is empty, the lock control can be efficiently processed by sequentially using the lowest one.

Description

Address Bus Lockout Control in Computer Systems

1 illustrates an example of a typical multiprocessor computer system.

2 is a flowchart showing an address bus lock control method according to a conventional method.

3 is a block diagram showing another address bus lock controller in accordance with the present invention.

4 is a flowchart showing an address bus lock control method according to the present invention;

* Explanation of symbols for main parts of the drawings

1: System Bus 2: Processor Board

3: memory board 4: input / output control board

5: System control board 21: System bus matching unit

22: lock buffer 23: lock controller

24: upper block

The present invention relates to an address bus lock control technique of a computer system. In particular, in a medium computer system having a multiprocessor structure, a read for write operation, a cache related operation of a processor, is performed without occupying the system bus by searching an address bus. Modify Write) 'relates to a device for controlling a lock operation to perform a cycle.

As shown in FIG. 1, a general multiprocessor system includes a plurality of processor boards 2, a memory board 3, an input / output control board 4, and a system control board 5 that are commonly connected to the system bus 1. The lock operation of the lock controller present in the memory board 3 is a function used to ensure synchronization between processors, and is not accessible to other processors between two cycles of reading and writing memory.

To do this, the contents of the lock address bus of the requestor requesting the lock for the first time are stored in the lock buffer, and priority is given to the requester requesting the funds so as not to allow execution of the lock by another requestor. Therefore, when an interlock read transmission type is performed by another requester, the contents of the corresponding lock address bus are compared with the currently stored lock address byte enable and address tag, and the lock busy signal is returned when the same is matched. Create as upper block.

That is, as an example of the configuration as shown in FIG. 1, in a medium-size computer, the system bus 1 is a HiPi bus as a backplane bus that serves as a path for information transmission, and the processor board 2 is provided with a processor and a cache memory. It is a tightly coupled multiple processor that can scale up to 10 boards on a shared bus. In addition, the memory board 3 is a board that stores programs and data of the operating system and the user, and may have a predetermined storage capacity based on the DRAN, and may be mounted on a shared bus up to eight. In addition, the input / output control board 4 is a board that is responsible for processing and passage role for efficiently processing data transmission between a large-capacity device such as a disk and a tape and a main memory device. It has ROM and local RAM for storage and has a large buffer for temporary storage of transmission data. It is expandable to 4 boards on shared system bus and provides an interface for block I / O devices. In addition, the system control board (5) is in charge of processing and passages for efficiently processing data transmission between character input / output processing devices such as consoles, terminals, printers, communication devices such as LAN and WAN, and main memory devices. And a ROM and a local RAM capable of incorporating a device driver for controlling a communication input / output device. The system also has a TODC and a battery backup RAM as system-wide resources. Up to two such system control boards can be mounted on a shared system bus and provide an interface for connecting text and communication input / output devices.

In the medium computer employing the HiPi bus, the transmission type (TT) is indicated by the transmission type signal line TT3: 0 on the system bus, and the transmission type related to the locking is referred to as' Interlock Read 'and' Interlock Write. ' The lock read transmission belongs to a single transmission and is a transmission for a lock operation. The lock is started by this transmission. The lock read transmission is performed by the same bus operation as a normal read, but the area is locked after this transmission is completed. . The lock write transfer type belongs to a single transfer, which is unlocked by this transfer as the transfer for the lock. The lock write transfer is performed by the same bus operation as the normal write, but after the transfer is completed, the area is released from the lock state. . That is, the processor that reads the data by the lock read performs the internal operation and then writes the data to the memory using the lock write to the area again, thereby completing the lock operation.

If any requestor tries to access a locked area, the address acknowledgment signal line AACK1..0 is set to 10 to indicate that the requested area is locked.

However, the conventional lock controller is composed of a register buffer for storing up to five lock addresses, a register for storing the slot address of the requestor requesting the lock, and a lock controller for viewing and controlling their states.

In this conventional lock controller, the basic unit of lock is byte, and it operates every cycle according to the request of all requesters. If there is an operation corresponding to the lock even if it is not selected, all the installed in the system The lock controller is adapted to perform the same operation at the same time.

On the other hand, the operation flow of the conventional lock controller, as shown in Figure 2, the step of checking the transmission pattern of the address bus coming in through the system bus connection (100) per cycle; If the transmission type is lock read, retrieving (101) the status of the lock buffer; As a result of retrieving the status of the lock buffer, if all areas of the lock buffer are empty, the information of the corresponding address bus is stored in the lowest buffer. If the previous address is stored in any buffer, it corresponds to the empty buffer immediately above. Storing the addresses (103, 104, 105); Checking a lock busy condition and generating a locked busy signal if it is a locked busy condition (107); If it is not a lock read and a lock write, it compares whether the corresponding slot number and the address match, and if it matches, it releases the lock buffer and releases the lock (110, 111, 112).

The conventional lock controller operating as described above has the following problems.

First, if the lock buffer is set to five stages, if an address is stored in an arbitrary buffer, the next address is stored immediately above the buffer, even though the lower buffer is empty. Second, even if the lower four buffers were empty, there was a problem that the address could not be stored when the address was stored in the uppermost lock buffer.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a lock control device that can effectively use the lock buffer.

In order to achieve the above object, the present invention provides a multiprocessor system, comprising: a system bus matching unit for interfacing with a system bus; The address and byte enable information is received from the system bus matching unit and stored according to a load signal or deleted according to a delete signal. The address and byte enable information is newly stored through the address and byte enable and the system bus. If the input address and the byte enable signal match, the same signal is output.If the address previously input and the newly input address match with the system bus but the byte enable signal is not the same, it is activated over. A lock buffer that outputs a signal and outputs a flag signal that is activated when an address is stored in the lock buffer; If the transmission type is interlock read from the system matching unit, if the transmission type is interlock read, the load signal is output to search the flag bit of the lock buffer and store the corresponding address at the bottom of the empty buffer, and the lock busy (lock_busy) A lock control signal is generated if the transmission condition is interlocked, and if the transmission type is interlock write, the lock control unit outputs a delete signal to empty the buffer if the slot number and address are matched. It is done.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

First, as described above, a lock is for preventing another processor from accessing a specific address area until a specific processor reads and writes a specific address (lock area). It is intended to be performed by a lock controller installed in memory.

This lock operation is started by an interlock read transfer form and is completed by an interlock write.

The lock controller according to the present invention includes a system bus matching portion 21 for interfacing with a system bus, as shown in FIG. Address and byte enable information is received from the system bus matching unit and stored according to the load signal (LOAD4: 0) or stored according to the delete (DELETE4: 0) signal. If the newly input address and the byte enable signal match, the same signal (SAME4: 0) is outputted.If the previously existing address matches the newly input address through the system bus, but the byte enable signal is not the same A lock buffer 22 for outputting an activated over signal OVER4: 0 and outputting an activated flag signal FLAG4: 0 when an address is stored in the lock buffer; The slot number (IN_AT7: 0) and the transfer type (IN_TT3: 0) are input from the system bus matching unit 21, and if the transfer type is an interlock read, the flag bit of the lock buffer is searched to store the corresponding address at the bottom of the empty buffer. The lock control unit 23 outputs a load signal, generates a lock busy signal when the lock busy condition is applied, and compares the corresponding slot number with the address when the transmission type is interlocked. It consists of).

The operation of the apparatus of the present invention configured as described above will be described with reference to the flow of FIG.

The system bus matching unit 21 inputs information such as an address, byte enable, transmission type, address tag, etc. from the system bus 1, and outputs a lock busy signal.

The lock control unit 23 continuously checks the transmission mode, and if so, checks the state of the lock buffer 22. At this time, the lock buffer 22 has five register groups capable of storing five lock addresses. If an address is stored in the register, the flag is in an active state, and if it is empty, the flag signal is in an inactive state. Therefore, you can see the state of the buffer by looking at the flag state. If the lock buffer 22 is empty, the corresponding load (LOAD4: 0) signal of the lock buffer is activated to store the address and byte enable data in the lowest register, so that the lock buffer 22 has a corresponding buffer register. Address and byte enable data are stored in the. Next, the flag signal of the corresponding register is switched to active (200 to 205).

If the transmission type input to the lock control unit 23 is an interlock light, if the lock buffer 22 compares the address and the byte, and activates the same signal, the lock control unit 23 checks whether the slot numbers match through the address tag. If it matches and checks, it activates the delete signal of the corresponding buffer to empty the buffer.

On the other hand, a processor having a different slot number outputs an address and byte enable signal previously stored in the lock buffer to perform an interlock read, or generate a lock busy signal when the buffer is full to generate a higher block 24. And the system bus (1) side (210, 211, 222).

As described above, the address lock controller according to the present invention has an effect of efficiently handling the lock control by allowing the lock buffer to be used sequentially from the bottom if the lock buffer is empty.

Claims (1)

A system bus matching unit 21 for interfacing with the system bus; Receives address and byte enable information from the system bus matching unit and stores them according to a load signal or deletes them according to a delete signal. If the input address and the byte enable signal match, the same signal is output.If the address previously input and the newly input address match with the system bus but the byte enable signal is not the same, it is activated over. A lock buffer 22 that outputs a signal and outputs a flag signal that is activated when an address is stored in the lock buffer; If the transmission type is an interlock read from the system bus matching unit, the load signal is output to search for the flag bit of the lock buffer and to store the corresponding address at the bottom of the empty buffer. The lock control unit 23 generates a lock busy signal under the (lock_busy) condition, and outputs a delete signal to empty the buffer when the transmission type is an interlock write. An address bus lock control device in a computer system having a.