JPS6137627U - Receiving machine - Google Patents

Receiving machine

Info

Publication number
JPS6137627U
JPS6137627U JP12112584U JP12112584U JPS6137627U JP S6137627 U JPS6137627 U JP S6137627U JP 12112584 U JP12112584 U JP 12112584U JP 12112584 U JP12112584 U JP 12112584U JP S6137627 U JPS6137627 U JP S6137627U
Authority
JP
Japan
Prior art keywords
storage means
receiving machine
tuning data
receiver
preset key
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12112584U
Other languages
Japanese (ja)
Inventor
美智範 浜田
洋一 坂本
Original Assignee
三洋電機株式会社
鳥取三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社, 鳥取三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP12112584U priority Critical patent/JPS6137627U/en
Publication of JPS6137627U publication Critical patent/JPS6137627U/en
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の受信機のブロック図、第２図は本考案
の受信機の正面図、第９図は第１図に示す本考案の動作
を説明するフローチャート図である。 第４図は従来の受信機のブロック図である。８・・・カ
ウンタ、９・・・パ−ラレル入力／シリアル出力変換器
、１０・・・シリアル入力／パラレル出力型シフトレジ
スタ、１４， １５， １６， １７・・・選局
データ記憶用シフトレジスタ、１８・・・入カゲート、
２０・・・出力ゲート。FIG. 1 is a block diagram of the receiver of the present invention, FIG. 2 is a front view of the receiver of the present invention, and FIG. 9 is a flowchart for explaining the operation of the receiver of the present invention shown in FIG. FIG. 4 is a block diagram of a conventional receiver. 8... Counter, 9... Parallel input/serial output converter, 10... Serial input/parallel output type shift register, 14, 15, 16, 17... Shift register for storing channel selection data , 18... entry gate,
20...Output gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 選局データを記憶する記憶手段とこの詰憶手段から選局
データを呼び出すプリセットキーとを具備した受信機に
於いて、前記プリセットキーの操作時間に応答して、前
記記憶手段を選局データの読み出し状態と書き込み状態
に設定する手段を設けたことを特徴とする受信機。In a receiver equipped with a storage means for storing tuning data and a preset key for reading the tuning data from the storage means, the storage means is loaded with the tuning data in response to the operation time of the preset key. A receiver comprising means for setting a read state and a write state.
JP12112584U 1984-08-07 1984-08-07 Receiving machine Pending JPS6137627U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12112584U JPS6137627U (en) 1984-08-07 1984-08-07 Receiving machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12112584U JPS6137627U (en) 1984-08-07 1984-08-07 Receiving machine

Publications (1)

Publication Number Publication Date
JPS6137627U true JPS6137627U (en) 1986-03-08

Family

ID=30679922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12112584U Pending JPS6137627U (en) 1984-08-07 1984-08-07 Receiving machine

Country Status (1)

Country Link
JP (1) JPS6137627U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63204811A (en) * 1987-02-19 1988-08-24 Sanyo Electric Co Ltd Synthesizer receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63204811A (en) * 1987-02-19 1988-08-24 Sanyo Electric Co Ltd Synthesizer receiver

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