JPS62171096U - - Google Patents
Info
- Publication number
- JPS62171096U JPS62171096U JP1986060619U JP6061986U JPS62171096U JP S62171096 U JPS62171096 U JP S62171096U JP 1986060619 U JP1986060619 U JP 1986060619U JP 6061986 U JP6061986 U JP 6061986U JP S62171096 U JPS62171096 U JP S62171096U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- comparison
- reset
- sends out
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Storage Device Security (AREA)
Description
第１図は本考案のＲＯＭの機能ブロツク図、第
２図は一般のＲＯＭの機能ブロツク図である。
１……メモリ部、２……トライステートバツフ
ア、３……比較部、４……フリツプフロツプ、５
……比較信号制御部、６……リセツト信号発生部
。
FIG. 1 is a functional block diagram of the ROM of the present invention, and FIG. 2 is a functional block diagram of a general ROM. 1... Memory section, 2... Tri-state buffer, 3... Comparison section, 4... Flip-flop, 5
. . . Comparison signal control section, 6 . . . Reset signal generation section.
Claims (1)
に従つて読出し信号として送出するメモリ部と、 前記読出し信号を入力して保持し、ＦＦ出力信
号に従つてデータ信号として送出するトライステ
ートバツフアと、 前記読出し信号と前記データ信号を入力し、両
者が一致したとき比較信号を送出する比較部と、 電源を投入したときにリセツト信号を送出する
リセツチ信号発生部と、 前記リセツト信号を入力したあと最初の選択信
号を入力するまでの間だけ前記比較信号を比較制
御信号として送出する比較信号制御部と、 前記リセツト信号によつてリセツトされ、前記
比較制御信号によつてセツトされて前記トライス
テートバツフアをオンにする前記ＦＦ出力信号を
送出するフリツプフロツプと、 を有して前記データの読出しの可否を制御するこ
とを特徴とする読出し専用メモリ。[Claims for Utility Model Registration] A memory unit that sends out previously written data as a readout signal in accordance with an address signal; and a memory unit that inputs and holds the readout signal and sends it out as a data signal in accordance with an FF output signal. a tri-state buffer; a comparison section that receives the read signal and the data signal and sends out a comparison signal when they match; a reset signal generation section that sends out a reset signal when the power is turned on; and the reset signal. a comparison signal control section that sends out the comparison signal as a comparison control signal only after inputting the signal until inputting the first selection signal; and a comparison signal control section that is reset by the reset signal and set by the comparison control signal. a flip-flop that transmits the FF output signal that turns on the tri-state buffer; and a flip-flop that controls whether or not the data can be read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986060619U JPS62171096U (en) | 1986-04-21 | 1986-04-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986060619U JPS62171096U (en) | 1986-04-21 | 1986-04-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62171096U true JPS62171096U (en) | 1987-10-30 |
Family
ID=30893182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986060619U Pending JPS62171096U (en) | 1986-04-21 | 1986-04-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62171096U (en) |
-
1986
- 1986-04-21 JP JP1986060619U patent/JPS62171096U/ja active Pending