JPS6245798U - - Google Patents
Info
- Publication number
- JPS6245798U JPS6245798U JP13589785U JP13589785U JPS6245798U JP S6245798 U JPS6245798 U JP S6245798U JP 13589785 U JP13589785 U JP 13589785U JP 13589785 U JP13589785 U JP 13589785U JP S6245798 U JPS6245798 U JP S6245798U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- read
- address
- integrated circuit
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の要部を示すブロツ
ク図、第２図は本考案の実施例のＲＯＭアドレス
を示す図。
１……読出し専用メモリ（ＲＯＭ）、２，５…
…アドレスデコーダ、３……アドレス発生回路、
４……書替え可能なプログラマブル読出し専用メ
モリ（ＥＰＲＯＭ）、６……データ書込み回路、
７……アドレス制御信号、８……書込み信号、９
……共通バス、１０……データ。
FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, and FIG. 2 is a diagram showing ROM addresses of the embodiment of the present invention. 1... Read-only memory (ROM), 2, 5...
...Address decoder, 3...Address generation circuit,
4... rewritable programmable read-only memory (EPROM), 6... data write circuit,
7...Address control signal, 8...Write signal, 9
...common bus, 10...data.
Claims (1)
びアドレスデコーダとを含み、 この読出し専用メモリに記憶された命令プログ
ラムにより演算や各部の制御を行うプログラム制
御方式の集積回路において、 上記アドレス発生回路で発生するアドレス領域
の特定部分に相当する上記読出し専用メモリが、
外部書込み手段を有する書替え可能なプログラマ
ブル読出し専用メモリから構成されること を特徴とする集積回路。[Claims for Utility Model Registration] A program control system that includes a read-only memory, an address generation circuit and an address decoder for the read-only memory, and performs calculations and controls each part using an instruction program stored in the read-only memory. In the integrated circuit, the read-only memory corresponding to a specific part of the address area generated by the address generation circuit,
An integrated circuit comprising a rewritable programmable read-only memory having external writing means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13589785U JPS6245798U (en) | 1985-09-05 | 1985-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13589785U JPS6245798U (en) | 1985-09-05 | 1985-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6245798U true JPS6245798U (en) | 1987-03-19 |
Family
ID=31038517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13589785U Pending JPS6245798U (en) | 1985-09-05 | 1985-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6245798U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634199A (en) * | 1979-08-27 | 1981-04-06 | Fujitsu Ltd | Memory correction system |
| JPS5823393A (en) * | 1981-08-05 | 1983-02-12 | Sanyo Electric Co Ltd | Mask rom device |
| JPS6050696A (en) * | 1983-08-27 | 1985-03-20 | Shinko Electric Co Ltd | Memory circuit |
-
1985
- 1985-09-05 JP JP13589785U patent/JPS6245798U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634199A (en) * | 1979-08-27 | 1981-04-06 | Fujitsu Ltd | Memory correction system |
| JPS5823393A (en) * | 1981-08-05 | 1983-02-12 | Sanyo Electric Co Ltd | Mask rom device |
| JPS6050696A (en) * | 1983-08-27 | 1985-03-20 | Shinko Electric Co Ltd | Memory circuit |