JPS63130471U - - Google Patents

Info

Publication number
JPS63130471U
JPS63130471U JP2130487U JP2130487U JPS63130471U JP S63130471 U JPS63130471 U JP S63130471U JP 2130487 U JP2130487 U JP 2130487U JP 2130487 U JP2130487 U JP 2130487U JP S63130471 U JPS63130471 U JP S63130471U
Authority
JP
Japan
Prior art keywords
elevator
memory
processing unit
central processing
electrically erasable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2130487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2130487U priority Critical patent/JPS63130471U/ja
Publication of JPS63130471U publication Critical patent/JPS63130471U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例の制御用マイクロ
コンピユータのEEPROM書き換えシステム構
成図、第2図はROM,RAMのROMマツプR
AMマツプ、第3図は、第1図に示す外部マイク
ロコンピユータのROMに格納するプログラムの
フローチヤートである。 1……制御用マイクロコンピユータ、2……中
央演算処理装置(MPU)、3……電気的消去書
き込み可能なメモリ(EEPROM)。
Fig. 1 is a configuration diagram of an EEPROM rewriting system of a control microcomputer according to an embodiment of the present invention, and Fig. 2 is a ROM map R of ROM and RAM.
The AM map in FIG. 3 is a flowchart of a program stored in the ROM of the external microcomputer shown in FIG. 1... Control microcomputer, 2... Central processing unit (MPU), 3... Electrically erasable and writable memory (EEPROM).

Claims (1)

【実用新案登録請求の範囲】 多階床間を走行するエレベータにおいて、 電気的に消去書き込み可能なメモリと、中央演
算処理装置と、バス制御権を解放する回路とを備
え前記メモリを書き変えるデータ書き込み装置と
接続可能にしたことを特徴とするエレベータ制御
装置。
[Claims for Utility Model Registration] An elevator that travels between multiple floors, comprising an electrically erasable and writable memory, a central processing unit, and a circuit for releasing bus control rights, and data for rewriting the memory. An elevator control device characterized by being connectable to a writing device.
JP2130487U 1987-02-18 1987-02-18 Pending JPS63130471U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2130487U JPS63130471U (en) 1987-02-18 1987-02-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2130487U JPS63130471U (en) 1987-02-18 1987-02-18

Publications (1)

Publication Number Publication Date
JPS63130471U true JPS63130471U (en) 1988-08-25

Family

ID=30817624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2130487U Pending JPS63130471U (en) 1987-02-18 1987-02-18

Country Status (1)

Country Link
JP (1) JPS63130471U (en)

Similar Documents

Publication Publication Date Title
JPS63130471U (en)
JPS6379185U (en)
JPS61156403U (en)
JPS6392963U (en)
JPS6353152U (en)
JPS5949233U (en) microcomputer
JPH0354053U (en)
JPS63143953U (en)
JPH01102906U (en)
JPS63139647U (en)
JPS6184955U (en)
JPS61204257U (en)
JPH02113899U (en)
JPS6245798U (en)
JPS63163043U (en)
JPS6368049U (en)
JPS61119199U (en)
JPH0191904U (en)
JPS6336999U (en)
JPS58190752U (en) One chip microcontroller
JPH026353U (en)
JPS6397148U (en)
JPS63178941U (en)
JPS5924284U (en) industrial robot
JPS62169851U (en)