JPS6336999U - - Google Patents

Info

Publication number
JPS6336999U
JPS6336999U JP12711786U JP12711786U JPS6336999U JP S6336999 U JPS6336999 U JP S6336999U JP 12711786 U JP12711786 U JP 12711786U JP 12711786 U JP12711786 U JP 12711786U JP S6336999 U JPS6336999 U JP S6336999U
Authority
JP
Japan
Prior art keywords
prom
proms
write
data
sockets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12711786U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12711786U priority Critical patent/JPS6336999U/ja
Publication of JPS6336999U publication Critical patent/JPS6336999U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク構成
図である。 1……キー入力部、2……制御プロセツサ部、
3……表示部、4……PROMソケツト(#1)
、5……PROMソケツト(#2)、6……PR
OMソケツト(#n)、7……内蔵メモリ(#1
)、8……内蔵メモリ(#2)、9……内蔵メモ
リ(#n)、10,11,12……データバス、
13……アドレス及び制御信号。
FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Key input section, 2...Control processor section,
3...Display section, 4...PROM socket (#1)
, 5...PROM socket (#2), 6...PR
OM socket (#n), 7...Built-in memory (#1
), 8... Built-in memory (#2), 9... Built-in memory (#n), 10, 11, 12... Data bus,
13... Address and control signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数個のPROMに同時に書込み可能なPRO
Mライタにおいて、あらかじめそれぞれ違つたデ
ータが書き込まれたn個の1組になつたPROM
と該各PROMのデータを書き込む何も書き込ま
れていないn個の1組になつたブランクPROM
とを選択的に着脱可能なn個のPROMソケツト
と、該n個の各PROMソケツトにそれぞれ接続
されたn個のメモリとを具備し、書込みデータ総
量が複数個のPROMにまたがる場合に前記各ブ
ランクPROMに別々のデータを同時に書込み可
能なことを特徴とするPROMライタ。
PRO that can write to multiple PROMs simultaneously
In the M writer, a set of n PROMs each with different data written in advance.
and a set of n blank PROMs into which data is written in each PROM.
n PROM sockets that are selectively attachable and removable, and n memories respectively connected to each of the n PROM sockets, and when the total amount of write data spans a plurality of PROMs, each of the above A PROM writer characterized by being able to simultaneously write different data into a blank PROM.
JP12711786U 1986-08-22 1986-08-22 Pending JPS6336999U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12711786U JPS6336999U (en) 1986-08-22 1986-08-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12711786U JPS6336999U (en) 1986-08-22 1986-08-22

Publications (1)

Publication Number Publication Date
JPS6336999U true JPS6336999U (en) 1988-03-09

Family

ID=31021560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12711786U Pending JPS6336999U (en) 1986-08-22 1986-08-22

Country Status (1)

Country Link
JP (1) JPS6336999U (en)

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