JPS6368054U - - Google Patents
Info
- Publication number
- JPS6368054U JPS6368054U JP15896586U JP15896586U JPS6368054U JP S6368054 U JPS6368054 U JP S6368054U JP 15896586 U JP15896586 U JP 15896586U JP 15896586 U JP15896586 U JP 15896586U JP S6368054 U JPS6368054 U JP S6368054U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- shared memory
- memory
- bus master
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
第１図は、本考案によるプライオリテイ決定装
置を説明する為の図、第２図は、従来のプライオ
リテイ決定装置を説明する為の図である。１，２
，３は、バスマスタ、４は共有メモリ、５，６，
７はバス要求信号、８，９，１０はプライオリテ
イ信号、１１，１２，１３は共有メモリへのデコ
ードアドレス、１４はレジスタ、１５はメモリで
ある。なお、図中同一あるいは相当部分には同一
符号を付して示してある。
FIG. 1 is a diagram for explaining a priority determining device according to the present invention, and FIG. 2 is a diagram for explaining a conventional priority determining device. 1,2
, 3 is the bus master, 4 is the shared memory, 5, 6,
7 is a bus request signal; 8, 9, and 10 are priority signals; 11, 12, and 13 are decode addresses to the shared memory; 14 is a register; and 15 is a memory. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.
Claims (1)
タ授受を行うマルチコンピユータシステムにおい
て、共有メモリとのデータの転送を行う各々のバ
スマスタから転送される共有メモリへのデコード
アドレスを取込むレジスタと、このレジスタの内
容と各バスマスタからのバス使用要求線をアドレ
スとするメモリとを有し、このメモリの内容によ
り各バスマスタのプライオリテイを決める信号を
発生することを特徴とするプライオリテイ決定装
置。 In a multi-computer system that exchanges data using shared memory connected on a bus, there is a register that takes in the decode address to the shared memory transferred from each bus master that transfers data to and from the shared memory. A priority determining device comprising a memory whose addresses are the contents of a register and a bus use request line from each bus master, and generating a signal for determining the priority of each bus master based on the contents of this memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15896586U JPS6368054U (en) | 1986-10-17 | 1986-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15896586U JPS6368054U (en) | 1986-10-17 | 1986-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6368054U true JPS6368054U (en) | 1988-05-07 |
Family
ID=31082953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15896586U Pending JPS6368054U (en) | 1986-10-17 | 1986-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6368054U (en) |
-
1986
- 1986-10-17 JP JP15896586U patent/JPS6368054U/ja active Pending
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