JPS63118659U

JPS63118659U -

Info

Publication number: JPS63118659U
Application number: JP826187U
Authority: JP
Priority date: 1987-01-22
Filing date: 1987-01-22
Publication date: 1988-08-01

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図ないし第７図は各プロセツサの動作を示
すフローチヤート、第８図は第１図のデータ処理
装置の具体構成例を示すブロツク図、第９図およ
び第１０図は第８図の各部のタイミング図、第１
１図は従来例を示すブロツク図である。 ……第１のプロセツサ、……第２のプロセ
ツサ、２１……共有メモリ、２２……バス切替ス
イツチ、２３，２４，２５……バスライン。 FIG. 1 is a block diagram showing an embodiment of this invention, FIGS. 2 to 7 are flowcharts showing the operation of each processor, and FIG. 8 is a block diagram showing an example of a specific configuration of the data processing device shown in FIG. Figures 9 and 10 are timing diagrams of each part in Figure 8, and Figure 1.
FIG. 1 is a block diagram showing a conventional example. ...First processor, ...Second processor, 21...Shared memory, 22...Bus changeover switch, 23, 24, 25...Bus line.

Claims

[Claims for Utility Model Registration] A first processor with a high priority, a second processor with a low priority, a shared memory shared by the first and second processors, and a second processor with a high priority; a bus changeover switch that selectively connects a bus line of the processor to a bus line of the shared memory, when a shared memory use request interrupt signal is given from the first processor to the second processor. Then, the second processor controls the bus changeover switch to connect the bus line of the second processor and the bus line of the shared memory to the bus line of the first processor and the bus line of the shared memory. a shared memory use permission interrupt signal from the second processor to the first processor; and a shared memory use end interrupt signal from the first processor to the second processor. is given, the second processor controls the bus changeover switch to connect the bus line of the first processor and the bus line of the shared memory to the bus line of the second processor. A data processing device configured to switch the shared memory to a connected state with a bus line.