JPS647333U - - Google Patents

Info

Publication number
JPS647333U
JPS647333U JP10025887U JP10025887U JPS647333U JP S647333 U JPS647333 U JP S647333U JP 10025887 U JP10025887 U JP 10025887U JP 10025887 U JP10025887 U JP 10025887U JP S647333 U JPS647333 U JP S647333U
Authority
JP
Japan
Prior art keywords
signal
clock control
flop
flip
keyboard controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10025887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10025887U priority Critical patent/JPS647333U/ja
Publication of JPS647333U publication Critical patent/JPS647333U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の構成を示すブロツ
ク図、第2図は従来のクロツク制御装置の構成の
一例を示すブロツク図である。 1……キーボードコントローラ、3,7……フ
リツプフロツプ、5……クロツク制御部。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of a conventional clock control device. 1...Keyboard controller, 3, 7...Flip-flop, 5...Clock control section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] キーボードコントローラと、このキーボードコ
ントローラの出力信号を一時的に保持しこのキー
ボードコントローラからの所定の信号により前記
保持した信号を出力する第1のフリツプフロツプ
と、この第1のフリツプフロツプの出力信号を保
持しこの第1のフリツプフロツプからの所定の信
号により少なくとも2つのクロツク制御信号を出
力する第2のフリツプフロツプと、前記クロツク
制御信号によつて中央処理装置のクロツク信号を
切換えるクロツク制御部とを具備してなることを
特徴とするクロツク制御装置。
a keyboard controller, a first flip-flop that temporarily holds an output signal of the keyboard controller and outputs the held signal in response to a predetermined signal from the keyboard controller; A second flip-flop that outputs at least two clock control signals in response to a predetermined signal from the first flip-flop, and a clock control section that switches the clock signal of the central processing unit in accordance with the clock control signal. A clock control device featuring:
JP10025887U 1987-06-30 1987-06-30 Pending JPS647333U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10025887U JPS647333U (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10025887U JPS647333U (en) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS647333U true JPS647333U (en) 1989-01-17

Family

ID=31328178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10025887U Pending JPS647333U (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS647333U (en)

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