JPH0267446U - - Google Patents
Info
- Publication number
- JPH0267446U JPH0267446U JP14687088U JP14687088U JPH0267446U JP H0267446 U JPH0267446 U JP H0267446U JP 14687088 U JP14687088 U JP 14687088U JP 14687088 U JP14687088 U JP 14687088U JP H0267446 U JPH0267446 U JP H0267446U
- Authority
- JP
- Japan
- Prior art keywords
- access
- control circuit
- cpus
- access control
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000873 masking effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Multi Processors (AREA)
Description
第1図は本考案に係るアクセス制御回路の回路
図、第2図は従来のアクセス制御回路のブロツク
図、第3図はその要部の回路図である。
9……アクセス信号供与手段、10,11……
Dタイプフリツプフロツプ、19……アクセス要
求信号マスク手段、20,21……AND回路、
22……インバータ回路、23……アクセス無効
手段、24……AND回路、25……3入力AN
D回路。なお、図中、同一符号は同一、又は相当
部分を示す。
FIG. 1 is a circuit diagram of an access control circuit according to the present invention, FIG. 2 is a block diagram of a conventional access control circuit, and FIG. 3 is a circuit diagram of its essential parts. 9... Access signal providing means, 10, 11...
D type flip-flop, 19...Access request signal masking means, 20, 21...AND circuit,
22... Inverter circuit, 23... Access disabling means, 24... AND circuit, 25... 3-input AN
D circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
クセス制御回路において、 前記CPUの1つからアクセス要求信号が出力
された場合に、そのCPUによるアクセスを可能
にし、そのアクセスの期間は他のCPUからのア
クセス要求信号をマスクするアクセス要求信号マ
スク手段と、複数のCPUからアクセス要求信号
が同時に出力された場合には、1つのCPUのア
クセスを可能にし、そのアクセスの期間は他のC
PUのアクセスを無効にするアクセス無効手段と
を備えていることを特徴とするアクセス制御回路
。[Claims for Utility Model Registration] In an access control circuit for accessing a common circuit from a plurality of CPUs, when an access request signal is output from one of the CPUs, the access control circuit enables access by that CPU and controls the access control circuit. The period includes an access request signal masking means for masking access request signals from other CPUs, and when access request signals are output from multiple CPUs at the same time, one CPU is allowed to access, and the access period is other C
An access control circuit comprising: access disabling means for disabling access to a PU.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14687088U JPH0267446U (en) | 1988-11-10 | 1988-11-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14687088U JPH0267446U (en) | 1988-11-10 | 1988-11-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0267446U true JPH0267446U (en) | 1990-05-22 |
Family
ID=31416756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14687088U Pending JPH0267446U (en) | 1988-11-10 | 1988-11-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0267446U (en) |
-
1988
- 1988-11-10 JP JP14687088U patent/JPH0267446U/ja active Pending