JPH022733U - - Google Patents

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Publication number
JPH022733U
JPH022733U JP7802988U JP7802988U JPH022733U JP H022733 U JPH022733 U JP H022733U JP 7802988 U JP7802988 U JP 7802988U JP 7802988 U JP7802988 U JP 7802988U JP H022733 U JPH022733 U JP H022733U
Authority
JP
Japan
Prior art keywords
data bus
bus
signal
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7802988U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7802988U priority Critical patent/JPH022733U/ja
Publication of JPH022733U publication Critical patent/JPH022733U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の構成を示した図、
第２図は第１図の装置のブロツク図である。 １……データバス、２……ナンドゲート、３…
…リセツトボタン、４……第１のフリツプ・フロ
ツプ、５……第２のフリツプ・フロツプ、６……
アービタ、９……デイレイライン。 FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a block diagram of the apparatus of FIG. 1. 1...Data bus, 2...Nand gate, 3...
...Reset button, 4...First flip-flop, 5...Second flip-flop, 6...
Arbiter, 9...day line.

Claims (1)

【実用新案登録請求の範囲】 共通のデータバスを使用する複数の装置からな
るデータ処理装置において、 リセツト信号が発生すると、前記データバスの
バス権のリクエスト信号を発生する第１のフリツ
プ・フロツプと、 このリクエスト信号に応じて、データバスのア
ービタからバスグラント信号が与えられたところ
で、データバスに所定のパルス幅のリセツト信号
を与える第２のフリツプ・フロツプ、 を具備したデータ処理装置。[Claims for Utility Model Registration] In a data processing device consisting of a plurality of devices using a common data bus, when a reset signal is generated, a first flip-flop that generates a request signal for bus ownership of the data bus; , a second flip-flop that applies a reset signal of a predetermined pulse width to the data bus when a bus grant signal is applied from the data bus arbiter in response to the request signal.
JP7802988U 1988-06-13 1988-06-13 Pending JPH022733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7802988U JPH022733U (en) 1988-06-13 1988-06-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7802988U JPH022733U (en) 1988-06-13 1988-06-13

Publications (1)

Publication Number Publication Date
JPH022733U true JPH022733U (en) 1990-01-10

Family

ID=31302979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7802988U Pending JPH022733U (en) 1988-06-13 1988-06-13

Country Status (1)

Country Link
JP (1) JPH022733U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0656107U (en) * 1993-01-08 1994-08-05 佐藤道路株式会社 Movable mixer for both carrier and vehicle

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145411A (en) * 1985-12-20 1987-06-29 Fujitsu Ltd System reset control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145411A (en) * 1985-12-20 1987-06-29 Fujitsu Ltd System reset control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0656107U (en) * 1993-01-08 1994-08-05 佐藤道路株式会社 Movable mixer for both carrier and vehicle

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