JPS62145411A - System reset control system - Google Patents

Abstract

PURPOSE:To prevent the memory access from being intermitted forcibly by issuing a bus enable permission to a bus using request immediately when no master during access exists in a bus arbitration circuit. CONSTITUTION:When an RSTSW signals is inputted to a reset control circuit 1 after a reset switch is depressed, the reset control circuit 1 uses a bus request signal BR7 to request a bus to a bus arbitration circuit 3. When the bus request circuit 3, based on the request, decides the provision of the next bus cycle, it is informed to the reset control circuit 1 by using a bus enable permission signal BG7. When the reset control circuit 1 receives the bus using enable signal BG7, an access signal AS is negated, and when a BGACK is negated, a bus using acknowledge signal BGACK and a reset signal RESET are outputted immediately and each section is reset.

Description

[Detailed Description of the Invention] [Summary] In a microprocessor system, when a system reset is performed, if the master is accessing memory,
If this is forcibly interrupted by a system reset, the memory contents may be completely destroyed, so conventionally,
Is it possible to send a set signal to each part of the system in synchronization with the end timing of memory access? However, this method had the drawback that the signal was not issued when there was no master accessing the memory, such as in the HALT state.

In order to solve these conventional drawbacks, the present invention issues a bus request signal to the bus arbitration circuit when a system reset is instructed, and when this signal is accepted and a bus use permission signal is received, each part in the system The present invention discloses a control method that can reliably reset the system under any conditions without destroying the memory contents by sending a reset signal to the system.

[Industrial application field]

The present invention relates to the control of system reset in a microprocessor system, and in particular, it is possible to prevent the memory contents from being destroyed even if there is a master accessing the memory at the time of reset, and to prevent the memory contents from being destroyed even if there is a master accessing the memory at the time of reset. The present invention relates to a control method that can reliably reset the system even when the master is in HALT.

[Conventional technology]

In a microprocessor system, when the system reset switch is pressed, if each part is reset immediately, the contents of the memory may be destroyed.

In other words, since a system reset occurs asynchronously with the operation of each part within the system, if the master happens to be accessing memory at that time, the master will be forcibly reset, resulting in the memory access being interrupted and the memory contents being destroyed. This creates the possibility that

For this reason, conventionally, even when the system reset switch is pressed, each part within the system is not reset immediately, but a reset signal is issued for each part at the same timing when the currently executing memory access is completed. It was commonly taken.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional control method, the system reset signal is issued in synchronization with the end of access to the memory, so when there is no master accessing the memory due to a HALT state, etc. , there was a drawback that a reset signal was not output.

In view of these conventional drawbacks, the present invention provides a system reset in a microprocessor system equipped with a bus arbitration circuit without destroying memory contents.
The purpose is to provide a complete control system that can be reliably performed regardless of memory access from the master.

[Means for solving problems]

According to the present invention, the above-mentioned object is, as described in the claims, a circuit that adjusts bus use requests from masters related to memory access, and when there are simultaneous bus use requests from a plurality of masters. In a system that is equipped with a bus arbitration circuit that controls the master with the highest priority to be granted permission to use the bus, while the master is configured to continue sending out bus permission confirmation signals while the master is using the bus, system reset is required. means for requesting the bus arbitration circuit to use the bus with the highest priority when the bus arbitration circuit is instructed;
A system reset characterized by providing means for sending a bus use permission confirmation signal and a reset signal to each part in the system when the bus use request is accepted and the bus use is permitted and the bus becomes usable. This is achieved through a control method.

[Effect]

In the above-mentioned means, when a system reset is instructed and a request is made to the bus arbitration circuit to use the bus with the highest priority, the bus arbitration circuit immediately resets the bus if there is no master currently accessing the memory. , if there is a master accessing the memory, permission to use the bus is granted in response to the bus use request when the memory access is completed. At this time, it issues a bus use permission signal and also sends out a reset signal to reset each part.

In other words, upon receiving reset No. a from the outside, the circuit that resets each part in the system requests the bus use request to the bus arbitration circuit as if it were a kind of master (having the highest priority for bus use). When this request is accepted and permission to use the bus is issued from the bus arbitration circuit, internal reset signals are sent to each component, so memory access is forcibly interrupted by a system reset. This will not cause any inconvenience.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention,
1 is a reset control circuit, 2 is a CPU.

3 represents a bus arbitration circuit, 4 represents a master 2, 5 represents a master 3, and 6 represents a memory. Also, to explain each signal, BR is a bus request signal, BRn is a bus request signal n5B
G is bus use permission signal, BGn is bus use permission signal n
, BGACK is a bus use permission confirmation signal, AS is an access signal, RESET is a cent signal, and R8TSW is a reset switch signal.

In FIG. 1, when the reset switch is pressed and the R8TSW signal is input to the reset control circuit 1, the reset control circuit 1 requests the bus from the bus arbitration circuit 3 using the bus request signal BR7.

When the bus arbitration circuit 3 decides to grant the next bus cycle in response to the above request, it notifies the reset control circuit 1 of the decision using the bus use permission signal BG7.

When the reset control circuit 1 receives the bus use permission signal BG7, the access signal As is negated and the BGACK is also negated, it immediately outputs the bus use confirmation signal BGACK and the reset signal aEsET.This resets each part and causes a system reset. The operation ends.

FIG. 2 is a time chart showing an example of the operation of the embodiment of the present invention.

〔Effect of the invention〕

As explained above, according to the method of the present invention, when a system reset is instructed by pressing the system reset switch, etc., the circuit that controls system reset controls the bus related to memory access as if it were a master. A request for use is made, and if the request is granted, the bus is not in use immediately, and if the bus is currently in use, the reset signal is output to each part as soon as the request is completed. There is no inconvenience that memory access is forcibly interrupted and the memory contents are destroyed, and the system can be reset reliably even when there is no master accessing the memory due to a master halt state, etc. There are advantages.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of the embodiment of the present invention. 1... Reset control circuit, 2... CPU, 3...
Bus arbitration circuit, 4...Master 2.5...Master 3.
6...Memory l゛. R2 RE, 5Eγ Figure 2

Claims (1)

[Claims] Bus arbitration is a circuit that adjusts bus usage requests from masters related to memory access, and when multiple masters request bus usage at the same time, it controls so that the master with the highest priority is granted permission to use the bus. In a system configured such that the master continues to send a bus use permission confirmation signal while the bus is in use, when a system reset is instructed, the master sends the bus with the highest priority to the bus arbitration circuit. A means for requesting the use of the bus, and a means for transmitting a bus use permission confirmation signal and a reset signal to each part in the system when the bus use request is accepted and the bus is permitted to be used. A system reset control method characterized by: