JPH0433065B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] As long as the bus requesting device to which the right to use the bus is granted continues to use the common bus for a predetermined period of time, the common bus is made exclusive to the bus requesting device;
If the continuous use of the common bus ends even before the predetermined time has elapsed, the common bus is released to other bus requesting devices. Thereby, bus usage efficiency can be improved. If no bus request is made by another bus requesting device after this time has elapsed, the bus requesting device to which the right to use the bus has been granted is given the right to use the bus. This results in
This results in a significant reduction in the overhead for bus acquisition, especially for bus requesting devices that use the bus frequently.

[Industrial application field]

The present invention relates to a bus occupancy control system, and more particularly, to a bus occupancy control system that provides a device that has been granted the right to use the bus the time to use a common bus exclusively.

Many information processing systems are configured with a plurality of bus requesting devices connected to a common bus. In such a system, it becomes necessary to perform bus acquisition processing for each bus requesting device. This bus acquisition process increases the overhead of the system, which is why it is desired to improve the technical means for the bus acquisition process. This requirement is particularly high in a system in which a plurality of bus requesting devices with different bus usage frequencies coexist.

[Conventional technology]

There are the following bus acquisition methods in the above-mentioned system.

When a data transfer request occurs to each bus requesting device,
A bus request signal is sent from each device. The right to use the bus is granted to one of the bus requesting devices based on these bus request signals in accordance with a system-defined bus right priority determining system. A bus requesting device that has been granted the right to use the bus sends a signal indicating that the bus is in use and transfers data, and after the transfer is completed, it turns off the signal that indicates that the bus is in use, releases the bus, and makes other bus requests. Such as allowing devices to use the bus.

There are also devices that continue to hold the bus until another bus requesting device requests the bus.

[Problems that the invention attempts to solve]

In the former method mentioned above, the bus is released every time data is transferred, so a bus requesting device that uses the bus frequently has to perform bus acquisition processing every time, resulting in a large overhead. , which may impede data transfer ability. Furthermore, even in the latter method, the same type of problem is brought to light in systems where multiple bus requests occur frequently.

The present invention was created in view of the above-mentioned problems, and provides a bus occupancy control method that can reduce the overhead of bus acquisition especially in a bus requesting device that uses the bus frequently and improve bus usage efficiency. The purpose is to

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. According to the present invention, one of the plurality of bus requesting devices is determined in a predetermined relationship in response to a bus use request from the plurality of bus requesting devices connectable to a common bus.
In a system in which one bus requesting device is granted bus usage rights and uses the common bus, at least two or more of the plurality of bus requesting devices have priority over bus usage requests individually. In a system in which no ranking is given and a common single ranking is given, a bus usage right granting means 1 for granting bus usage rights to a bus requesting device having the single ranking that has generated a bus usage request; , a bus use request from the single-rank bus requesting device other than the device to which the bus use right has been granted after the generation of a signal indicating the bus use right to which the bus use right has been granted by the bus use right granting means 1; is detected, before a predetermined period of time has elapsed from the time when the signal indicating the bus usage right was generated, and the single-rank bus requesting device that has been granted the bus usage right is the common bus requesting device. The system is further provided with a bus right granting control means 2 which prohibits the bus right granting means 1 from granting the bus right when there is a request to use the bus continuously.

[Effect]

When a certain bus requesting device is granted a bus usage right by the bus usage right granting means 1, the bus usage right is granted by the bus usage right granting means 2 for a predetermined time from the time when the bus usage right is granted. It is valid without being interfered with by other bus usage requests as long as it is used continuously. Even before the predetermined time has elapsed, the bus is released when a bus requesting device that has been granted the right to use the bus completes using the bus, and even after the predetermined time has elapsed, the bus is released by another bus requesting device. If there is no request, the bus requesting device to which the bus usage right has been granted is left with the bus usage right.

By doing so, it is possible to improve bus usage efficiency and reduce the overhead of bus acquisition by bus requesting devices that use the bus frequently.

〔Example〕

Figure 2 is a system configuration diagram for implementing the present invention.
FIG. 3 is a diagram showing the configuration of its main parts. In FIG. 2, 10 is a main storage device, which is connected to a central processing unit 12 and DMA (Direct Transfer) via a main storage controller 11.
(Memory Access) controller 13 or input/output devices 17 ₁ , 17 ₂ , . . . 17 _n . Central processing unit 12 and DMA
An input/output bus 14 is connected to the controller 13, and a DMA control bus 15 is also connected to the DMA controller 13. Input/output bus 14 and
The DMA control bus 15 includes input/output devices 16 ₁ , 16 ₂ ,
16 ₃ , . . . , 16 _l are connected, and the DMA controller performs bus occupancy control for these input/output devices and performs data transfer. In addition, input/output devices 17 ₁ , 17 ₂ , ... 17 _n connected only to the input/output bus 14
acquires the right to use the bus and performs data transfer. 20 is a bus arbiter (input/output bus usage right grant control means).

FIG. 3 is a detailed diagram of the DMA controller 13 and bus arbiter 20.

30 is a DMA priority circuit, which handles multiple access request devices such as input/output devices.
Upon receiving the DMA transfer request signals DREQ0 to DREQn, a subchannel selection signal is sent to the DMA subchannels (#0 to #n) 31 and the DMA response circuit 32. The DMA response circuit 32 generates response circuits DACK0 to DACKn in response to the DMA transfer request signal and sends them to the corresponding access request device, and also sends a transfer end signal TEND to the bus occupancy control section 33. 3
Reference numeral 4 denotes a data transfer timing control unit that receives a data transfer request signal TR (described later) from the bus occupancy control unit 33 and sends timing signals necessary for data transfer to the DMA subchannel 31, the DMA response circuit 32, and the main memory access control unit 35. . Main memory access control unit 35 connects DMA subchannel 31 to memory interface 36 . Each of these components 30 to 36 is provided in a conventional device.

The bus occupancy control section 33 sends the bus request signal BRQd to the bus arbiter 20, and if the signal BRQd is at the highest level among the bus requesting devices requesting the bus at that time, it sends the signal BGRd to the bus occupancy control section 33. Generates bus busy indication signal BSYd. This signal BSYd is applied to the timer 41, and after a predetermined time elapses, a signal REL2 is generated and the bus occupancy control section 3
3. The signal BSYd is driven by an open collector element 42, and the signal wired and wired with the bus busy indication signal of another bus requesting device notifies the bus arbiter 20 that the bus is busy.

The above-mentioned signal BRQd is generated from the AND gate 50, and the input of the AND gate 50 is the signal
These are the output signal DRQS of the OR gate 51 receiving DREQ0 to DREQn and the output signal () of the JK flip-flop 52. This JK flip-flop 52 is set by the above-mentioned signal BGRd and reset by the output signal of the AND gate 53. This AND gate 53 is the signal REL
1 and JK flip-flop 54 output signals
It generates an output signal when TR is present and signal DRQS is absent or signal REL2 is present. J
-K flip-flop 54 is set by the output signal of AND gate 55, and the above-mentioned signal
Reset by TEND. AND gate 55 has signals BSYd and DRQS and
Generates an output signal when REL1 and REL2 are absent.

60 are bus request signals BRQ0 to BRQm and
This is a bus priority circuit that receives BRQd and makes the bus vacant and sends out a bus use permission signal BGRi (i=0 to m) corresponding to the bus request signal with the highest priority. 61 receives the bus request signals BRQ0 to BRQm and outputs the signal REL.
This is an OR gate that generates 1.

The manner in which bus occupancy is controlled under the above configuration will be described below.

When one or more of the plurality of DMA request signals DREQ0 to DREQn becomes high level, the signal DRQS becomes high level H, and if the signal is at high level H, that is, the DMA controller does not have the right to use the bus, the AND gate 50 bus request signal from
BRQd is output.

If the bus is free (high) and signal BRQd is the highest among the bus requestors requesting the bus, then signal BGRd is set high. This causes the signal BSYd to go high, indicating that the bus is in use. The signal BSYd operates the timer 41 and notifies the bus arbiter that the bus is in use by a signal wired with the bus in-use indication of another bus requesting device.

In parallel with this, the AND condition of the AND gate 55 receiving the signal BSYd is satisfied and the signal TR is generated from the JK flip-flop 54.
The DMA controller 13 performs main memory access while the signal TR is at a high level, and the corresponding signal DACKi.
(i is 0 to n) is set to a high level and a series of sequence processing similar to the conventional one is performed, such as data transfer with the corresponding access requesting device 16i.

In this way, once the DMA controller 13 acquires the right to use the bus, the signal REL2 from the timer 41 does not go to high level H (before a predetermined period of time has elapsed) and an unprocessed DMA request remains. The bus will not be released as long as there are. In other words,
REL1=H, REL2=L and DRQS=H (unprocessed
If there is a DMA request), the bus is not released (the AND gate 53 does not generate a signal to reset the JK flip-flop), and after the data transfer is completed, TR is set to H again to continue data transfer. .

However, REL1=H and REL2=H
That is, when a predetermined time has elapsed, no new data transfer is started even if there is an unprocessed DMA request, and when =H, the bus is released (BSYd = L).

Also, when REL1=H and REL2=L,
If DRQS=L (no DMA request) and data is not being transferred (=H), the bus is released.

Note that the time given by the timer in the above embodiments may be fixed or variable.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the overhead required for bus acquisition by a bus requesting device, particularly a bus requesting device that uses the bus frequently, and improve bus usage efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a system implementing the present invention, and FIG. 3 is a diagram showing the configuration of essential parts of the present invention in the system shown in FIG. In FIG. 1, 1 is a bus use right granting means; 2
is a bus use right granting control means.

Claims (1)

[Scope of Claims] 1. In response to bus use requests from a plurality of bus requesting devices connectable to a common bus, one bus requesting device among the plurality of bus requesting devices is determined in a predetermined relationship. In a system that uses the common bus by being given the right to use the common bus, at least two or more bus requesting devices among the plurality of bus requesting devices are not individually prioritized for bus use requests. , in a system in which a common single rank is given, bus use right granting means 1 for granting bus use rights to a bus requesting device of the single rank that has issued a bus use request; and the bus use right granting means. 1, when a bus use request is detected from the single-rank bus requesting device other than the device to which the bus use right has been granted after the generation of a signal indicating the bus use right to which the bus use right has been granted by the Before a predetermined period of time has elapsed since the time when a signal indicating the right to use the bus was generated, and a bus requesting device of a single rank that was given the right to use the bus continuously uses the common bus. 1. A bus occupancy control system comprising: a bus right granting control means 2 which prohibits the bus right granting means 1 from granting a bus right when there is a request.