JPS63231662A - Bus control circuit - Google Patents

Abstract

PURPOSE:To enable a port having a lower priority level of bus use right to use a bus within a prescribed time by temporarily setting a high priority level to this port if this port cannot use the bus over the prescribed time. CONSTITUTION:A bus control circuit 1 is provided with a timer 5, a timer 6, a priority control circuit 7, and a bus use permission signal generating circuit 8. A bus master 2, a bus master 3, and a bus master 4 have the highest priority level, the lower priority level, and the lowest priority level of bus use right respectively. The time of expiration of the timer 5 is set to T2 shorter than a timer T1 for the purpose of securing the maximum time T1 required for validation of a bus use permission signal (d) after the time when the bus master 3 validates a bus request signal (c). The time of expiration of the timer 6 is set to T4 shorter than T3 for the purpose of securing the maximum time T3 required for validation of a bus use permission signal (f) after the time when the bus master 4 validates a bus request signal (e).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to bus control means for a system having a plurality of bus masters.

〔overview〕

The present invention provides a bus control circuit that grants bus usage rights to a plurality of ports connected to a bus, when a port with a lower priority for bus usage rights is unable to use the bus despite the passage of a predetermined time. By temporarily setting a high priority to a port, a port with a low priority can use the bus within a predetermined time.

[Conventional technology]

Conventionally, priority control of bus usage rights in this type of system has been fixed priority control or rotating priority control.

[Problem that the invention seeks to solve]

First, in the case of fixed priority control, when a bus master with a high priority continuously requests the use of the bus, a bus master with a low priority cannot acquire the bus, and processing by this bus master stops. There is. In addition, in the case of rotating priority control, there is no priority level, so bus masters with high urgency and bus masters with low urgency are treated equally, which has the disadvantage that the processing of bus masters with high urgency may be delayed. .

The present invention eliminates these drawbacks and provides a bus in which a bus master with a lower priority can acquire the right to use the bus without delaying the processing of a bus master with a higher priority. The purpose is to provide a control circuit.

[Means for solving problems]

The present invention provides a bus control system having bus master means, coupled to a port connected to a bus, and comprising means for setting bus usage rights assigned different levels of priority to each of the bus master means. The circuit includes timer means for ascertaining that a request for use of the bus by the bus master means to which the right to use the bus with a lower level of priority has been set has not been satisfied within a predetermined time; and means for temporarily setting a bus use right assigned a higher level priority to the bus master means to which the bus use right assigned a lower level priority is set based on the output. It is characterized by:

[For production]

A timeout signal is output from the timer when a lower priority bus master requests the bus and the bus master fails to acquire the bus within a certain period of time. The priority of the bus master that times out is temporarily set to the highest priority.
Obtain the right to use the bus.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. This embodiment includes a bus control circuit 1 and a system
It comprises a bus 10 and bus masters 2.3 and 4 connected to the system bus 10. FIG. 2 is a configuration diagram of the bus control circuit 1 of the present invention. This bus control circuit 1 includes a timer 5, a timer 6, and a priority control circuit 7.
and a bus use permission signal generation circuit 8. here,
Bus master 2 has the highest priority for bus usage rights, bus master 3 has the next highest priority, and bus master 4 has the lowest priority. Also, the timeout time of the timer 5 is the maximum time T1 from when the bus master 3 validates the bus request signal C until when the bus permission signal d becomes valid.
In addition, the timeout time of timer 6 is set to T2, which is shorter than T1, in order to guarantee that , let T be shorter than T4.

Now, when the bus master 2 makes the bus request signal a valid, the bus control circuit l outputs the priority circuit output signal j unless the time-out signal m of the timer 5 and the time-out signal n of the timer 6 are valid. is enabled, the bus use permission signal generation circuit 8 monitors the bus status signal, and
If the system bus 10 is not in use, the bus use permission signal is enabled to give the bus master 2 the right to use the system bus 10.

Here, the timeout signal m of timer 5 or timer 6
bus master 3 if timeout signal n is valid.
Alternatively, the priority of bus master 4 becomes higher, bus master 3 or bus master 4 is given the right to use the bus, and is forced to wait until timeout signals m and n become invalid. Next, when the bus master 3 makes the bus request signal C valid, the bus control circuit 1 outputs a priority circuit output signal unless the bus request signal a from the bus master 2 and the time-out signal n of the timer 6 are valid. k becomes valid, the bus status signal is monitored by the bus use permission signal generation circuit 8, and if it is not being used, the bus use permission signal d is made valid, giving the bus master 3 the right to use the system bus 10. . If the time-out signal n is valid, the priority of the bus master becomes high, the bus master 4 is given the right to use the bus, and is made to wait until the time-out signal n becomes invalid. In addition, if bus master 2's bus request signal a is valid, bus master 2 has a higher priority, so it is forced to wait until bus request signal a becomes invalid, but if bus master 2's request continues Then, bus master 3 cannot guarantee when the right to use will be granted. However, the timer 5 times out after a time T2 after the bus request signal C becomes valid, and makes the time-out signal m valid. When the time-out signal m becomes valid, the priority control circuit 7 disables the signal j even if the bus request signal a of the bus master 2 is valid, enables the signal k, and sets the priority of the bus master 3. make it higher.

When the bus request signal e of the bus master 4 becomes valid, it operates in the same way as the bus master 3.

〔Effect of the invention〕

As explained above, the present invention includes a timer that times out when a bus master with a lower priority has not been able to acquire the bus for a certain period of time after the bus request from the bus master becomes valid; The bus control circuit consists of a priority control circuit that temporarily sets the priority of this bus master to the highest when the timer times out, so the bus master with a lower priority This has the effect of allowing the user to obtain the right to use the bus within the required time.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention. FIG. 2 is a configuration diagram of the bus control circuit of the present invention. 1... Bus control once! , 2-4...bus master,
5.6...Timer, 7...Priority control circuit, 8...Bus use permission signal generation circuit, 10...System bus. lυ Example configuration Figure 1 Bus control circuit configuration Figure 2

Claims (1)

[Claims] (1) A bus control circuit having bus master means, coupled to a port connected to the bus, and having means for setting bus usage rights assigned different levels of priority to each of the bus master means. a timer means for confirming that a request for use of the bus by the bus master means to which the right to use the bus with a lower level of priority has been set has not been satisfied within a predetermined time; and an output of the timer means. Based on the above-mentioned rules, bus usage rights with lower priority levels are set.
1. A bus control circuit comprising means for temporarily assigning bus usage rights to a master means at a higher level of priority.