JPS58217071A - Information processing system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a system, and to mediate use of a bus at a high speed, by dividing plural master processors into several blocks, controlling in parallel the bus use between the blocks, and controlling in parallel the bus use in the block in which the bus use is approved. CONSTITUTION:Plural master modules (master processors) 2-5 are connected to one control bus 1, and each block 2-5 is divided into blocks of modules 2, 3 and modules 4, 5, respectively. Each request of the modules 2, 3 and 4, 5 of said each block is supplied to an OR circuit 16, each OR output is supplied to a priority degree controlling circuit 6, and use of a bus 1 of each block is controlled in parallel. Also, the modules 2, 3 and 4, 5 in each block are connected by enable signal lines 11, 15, respectively, and use of the bus in each block in which use of the bus 1 is approved is controlled in series. In this way, the constitution of an information processing system is simplified, and use of the bus 1 is mediated at a high speed.

Description

[Detailed Description of the Invention] The present invention relates to an information processing system that uses one path (hereinafter referred to as a common path) in a time-sharing manner, and in particular, a plurality of master modules obtain exclusive rights to the common bus in consideration of priority. This relates to the configuration of a multiprocessor system.

Multiple master modules (for example, one chip
When a control processor (including a PU) monopolizes the common bus in a time-sharing manner, it is essential to arbitrate the exclusive right of the common bus of each master module, that is, allocate the exclusive right.

When a master module attempts to monopolize the common bus, if no other master module has issued a request for exclusive use of the common bus, or if it has issued a request for exclusive use of the common bus but has a lower priority than itself, it will The master module will have the highest priority of all master modules on the common bus. With a master module having this highest priority, if the common bus goes to an empty state where no master module is occupied, that master module will monopolize the common bus, and prohibit the use of the common bus at the same time. . When allocating this exclusive right, it is necessary to prioritize the master modules, and there are two conventional prioritization methods: a parallel method and a daisy chain method.

The configuration of the former parallel system is as shown in FIG. 1, in which bus-exclusive request signals s and io are sent from each master module 2 to 5.

12.14 is output to the priority control circuit 6, and the master modules 2 to 5 specified by the priority control circuit 6
A bus-exclusive permission signal or enable signal 9 for
, 11, 13.15 are transferred. That is, the bus exclusive right to each master module is assigned by this priority control circuit.

In this system, each master module outputs a request signal to the priority control circuit and then receives an enable signal, so an enable signal is output to the master module that is not outputting a request signal. Never. In other words, since all mask modules are directly connected to one priority control circuit, high-speed bus arbitration is possible. However, at least one priority control circuit is required in an information processing system, and especially when this parallel method is applied to an information processing system with a large number of mask modules, the priority control circuit and its connections become necessary. The disadvantage was that it was large-scale and complicated.

On the other hand, the configuration of the latter daisy chain method is as shown in Figure 2, and in this example, each master module has 5,
The priorities increase in the order of 4, 3.2. That is, module 2 is the master module with the highest priority.

Now, in FIG. 2, the mask module 3 has the second highest priority overall, but it receives the enable signal 11 for itself from the master module 2, which has one level higher priority than itself, and The enable signal 13 for the mask module having one level lower priority than itself is sent to the mask module 4 having one level lower priority. In this way, the master module with the highest priority is connected to the mask module with the lowest priority in order by the enable signal line in a daisy chain manner, and the bus is only used when the enable signal arrives. It is now possible to do so.

In this method, each master module does not use a request signal. Therefore, a priority control circuit like the parallel system is not necessary. Therefore, a certain master module,
For example, the enable signal for master module 4 in FIG. 2 is master module 2$-! and 3 (master module with higher priority than 4) are in a position to obtain the right to use the bus without outputting a request signal, unless they are attempting to monopolize the common bus. This also means that each master module has an enable signal output for itself, and when it does not need to monopolize the common bus, it must output an enable signal to lower master modules. It is built on.

In this way, in the daisy chain system, the priority control is distributed to each master module and the receiver is assigned, so there is no need to provide a special priority control circuit. However, since signal lines for determining priorities are connected in cascade, the number of connection stages increases as the number of master modules increases, and the delay prevents high-speed bus arbitration.

In this way, in a multi-processing system with a large number of master modules, the conventional configuration has the disadvantage of either having multiple MK-& priority control circuits or being unable to perform high-speed bus arbitration. I'm disappointed.

An object of the present invention is to provide a multi-information processing system that enables high-speed bus arbitration without complicating the configuration.

According to the present invention, a system can be obtained in which a mask module is divided into a plurality of blocks, a daisy chain method is applied within each block, and a parallel method is applied between blocks.

Now, multiple masters on the common bus have a common bus exclusive request output line (request), a common bus exclusive output line (bus busy), a common bus exclusive permission output line (enable output), and a common bus exclusive permission input line (enable input). In an information processing system having slave modules accessed by a module and a master module, multiple master modules are divided into multiple blocks each consisting of several master modules, and priority is given within each block using a daisy chain method. The block is configured to determine priorities in a parallel manner between blocks.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, there are four master modules, mask module 2.3 and mask module 4.5 are each divided into blocks, each block forms a daisy chain, and the priority for the two blocks is The control circuit is provided in parallel. The OR circuit 16 receives a common request signal 17 from each master module in the block.
and 18.

In the priority determination process, first, the priority of the target block is determined by the parallel method between blocks, and then the priority of the target mask module within the target block is determined by the daisy chain method within the block. Therefore, bus priorities can be determined easily and quickly in an information processing system.

Now, to explain the operation using an example in which the master module 3 is trying to monopolize the common bus, the master module 3 outputs the request signal 10 to the priority control circuit 6 via the OR circuit 16. 6 receives this request signal as a request from the upper block and outputs an enable signal 9 to this block. At this time, if the high-level master module 2 is monopolizing the common bus or is about to monopolize the common bus, it does not output the enable signal 11 to the low-level master module 3. Conversely, if the master module 2 does not need to exclusively use the common bus, it outputs an enable signal to the master module 3.

As a result, the target master module can obtain the right to use the bus.

By applying the present invention, when n modules are combined into one block, the number of master modules of the target information processing system can be reduced in terms of circuit simplification compared to applying the parallel method alone. It is possible to simplify the circuit to the level of a 1/n-level priority control circuit, and it is also possible to simplify the bus arbitration to the level of the n-level daisy-chain system in terms of faster bus arbitration compared to the single application of the daisy-chain system. This makes it possible to speed up the process.

Further, depending on the number of n, it can be freely decided whether to give priority to circuit simplification or to speeding up bus arbitration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional parallel system information processing system, FIG. 2 is a conventional daisy chain system information processing system block diagram, and FIG. 3 is a block diagram of an information processing system according to an embodiment of the present invention. 9- 1°0°1°°Common bus, 2~5°°1°°Master module, 6...Priority control circuit% 7...
...Bus busy signal line, 8...2 request signal line, 9...2 enable input signal line,
10...3 request signal line, 11...
...3 enable input signal line. 12...4 request signal line, 13...
...4 enable input signal line, 14...5 request signal line, 15...5 enable input signal line, 16...OR circuit, 17... °・
・OR output signal line of 8 and 10, 18...OR output signal line of 12 and 14. 10- Ritsu 22 Kuniju 23

Claims (1)

[Claims] In an information processing system having a plurality of master processors on one bus, the plurality of master processors are divided into several blocks, bus use decisions are controlled in parallel among the blocks, and bus use is permitted. An information processing system characterized in that bus usage rights are given to any master processor by serially controlling bus usage decisions within a block.