JPS5847468Y2 - Microprocessor mutual exclusion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mutual exclusion circuit for mutually exclusive operation of resources shared by two microprocessors.

In a microprocessor system including a plurality of microprocessors, there are cases where two microprocessors perform processing while operating a shared resource such as a shared data table on a shared memory.

In such a case, a mutual exclusion function must be provided between the processors so that both microprocessors do not operate on this shared resource mutually exclusive, ie, at the same time.

For example, in the past, multiple variables were prepared in a specific area on the shared memory to display the usage status of shared resources, and each processor checked these variables before performing an operation to check the usage status of the shared resources using software. We have confirmed that.

In such conventional methods, when a microprocessor needs to manipulate a shared resource, it checks whether the shared memory can be manipulated by checking variables stored in a specific area on the shared memory. Know what.

That is, when one microprocessor is operating a shared resource, this microprocessor sets a value indicating that it is operating in a variable in the area on the shared memory.

Therefore, even if another microprocessor attempts to operate on a shared resource, the other microprocessor first examines the variables stored in a specific area, thereby preventing the other microprocessor from operating on the shared resource. The shared resources are not manipulated by other microprocessors.

Furthermore, when a microprocessor finishes operating a shared resource, it sets a value in a variable in a specific area of shared memory to indicate that it is not in use, allowing other microprocessors to operate on the shared resource. Let me show you something.

In this way, mutual exclusion of shared resources between processors can be achieved through a program, but with this method, each processor inspects and changes variables stored in a specific area each time it uses a shared resource. In order to do so, a certain algorithm must be executed.

Also, after each operation, a certain algorithm must be executed to change this variable.

Therefore, a certain amount of extra operation time (overhead) is required before and after using the shared resource, which greatly affects the processing time of the computer system.

The present invention solves the drawbacks of the conventional technology,
The aim is to realize a mutual exclusion circuit between microprocessors that performs real-time operation in response to request signals from microprocessors when accessing shared memory.

FIG. 1 is a block diagram of a microprocessor system using the microprocessor mutual exclusion circuit of the present invention.

10.20 are two microprocessors each sharing a shared memory 30; microprocessor 10.20
are connected to the input/output circuits 12, 22 and the memory IJs 13, 23, etc. via respective path lines 11, 21, respectively.

On the other hand, the microprocessors 10.20 share a shared memory 30 via respective path lines 11.21, to which a mutual exclusion circuit 40 is connected.

FIG. 2 is a block diagram showing one embodiment of the microprocessor mutual exclusion circuit of the present invention.

The mutual exclusion circuit 40 receives a request signal (R
EQl, REQ2) and a reset signal (R8TI, R8T2; indicating that the shared resource operation has been completed), and depending on the state of these signals, the mutual exclusion circuit 40 assigns one of the microprocessors 10.20 exclusive use of the shared memory. Generates a proprietary signal GRANT1 or GRANT2 to permit.

Mutual exclusion circuit 40 includes competition circuit 41 . Proprietary signal generation circuit 4
2. A signal generation circuit 44 is provided.

The shared resources on the shared memory 30 are shared by the microprocessor 10.
, 20, the signal generation circuit 44 supplies the input prohibition signal P to the competition circuit 41,
Request signal REQ1. Input of REQ2 is prohibited.

On the other hand, if the shared resource on the shared memory 30 is not being operated by the microprocessor 10 or 20, the contention circuit 41
When the input prohibition signal P is not supplied to the input inhibit signal P and the request signal REQ 1 or REQ 2 is supplied to the competition circuit 41 at this time, one of the request signals is supplied to the exclusive signal generation circuit 42 .

The exclusive signal generation circuit 42 generates an exclusive signal GRANT1 or GRAN that allows one of the microprocessors 10 or 20 to operate the shared resource based on the output of the contention circuit 41.
Supply T2.

Further, the signal generation circuit 44 supplies the input prohibition signal P to the competition circuit 41 at the same time that the exclusive signal generation circuit 42 generates the exclusive signal.

When the microprocessor 10 or 20 finishes operating the shared resource on the shared memory 30, a reset signal R8T1 or R8T2 is supplied to the signal generation circuit 44 from the microprocessor 10 or 20 that has finished the operation, and an input prohibition signal P is supplied.
disappears.

Note that the signal generation circuit 44 does not have the function of making the input prohibition signal P disappear by means of a reset signal, but can also have a function of making the input prohibition signal P disappear after a certain period of time has elapsed.

In this way, the microprocessor mutual exclusion circuit 4 of the present invention
0 supplies a proprietary signal to the microprocessor 10 or 20 when a request signal is supplied from either one of the microprocessors 10 or 20, and when one microprocessor is operating the shared memory, the other microprocessor Even if it receives a request signal, it functions so as not to supply a proprietary signal to the other microprocessor.

FIG. 3 is a connection diagram showing a specific embodiment of the mutual exclusion circuit 40.

Terminals 401 and 402 are microprocessor 10.2, respectively.
0 to receive request signals REQI, REQ2, terminals 461, 462 receive exclusive signals GRANT1. GRANT
The terminal that generates 2, 451.452 is the reset signal R8
T1. This is a terminal that receives R8T2.

411, 412 are NAND circuits with three inputs, 43
0.450 is an OR circuit, and 420.440 is an R-S flip-flop.

The three inputs of the NAND circuits 411 and 412 are each connected to the terminal 40.
1,402. and the outputs of the NAND circuits 412 and 411, and the Q output of the R-S flip-flop 440.

The outputs of the NAND circuits 411 and 412 are connected to the OR circuit 430, and at the same time, the inverted output values thereof are connected to the set terminal S and reset terminal R of the R-S flip-flop 420.

The Q output of R-S flip-flop 420 is connected to terminal 462 and the Q output is connected to terminal 461.

Further, the output inversion value of the OR circuit 430 is connected to the set terminal S of the R-S flip-flop 4400, the output inversion value of the OR circuit 450 is connected to the reset terminal R of the R-S flip-flop 440, and the output inversion value of the OR circuit 450 is connected to the input of the OR circuit 450. terminal 451,
452 is connected.

Next, the operation of the mutual exclusion circuit shown in FIG. 3 will be explained.

In the embodiment of FIG. 3, the request signals REQ1.
An H-level signal is given to REQ2, and the exclusive signal and reset signal are both L-level signals.
and 'R8Tl, R8T2' are displayed by drawing a bar above the signal abbreviations.

(1) When neither microprocessor 10 nor microprocessor 20 requests operation of the shared resource.

Request signals REQI and REQ2 are connected to terminals 401°40
2, the terminals 401 and 402 are at L level.

R-S flip-flop 440 is in a reset state,
The Q output is at H level.

Therefore, the set human power S and the reset human power R of the R-S flip-flop 4200 are both at the L level, and the R-S flip-flop 420 maintains its previous state.

Therefore, although either terminal 401 or 402 remains at L level, this signal is not read by the microprocessor.

(2) When a request signal requesting operation of a shared resource is generated from one of the microprocessors 10 and 20.

For example, the request signal RE from the microprocessor 10
When Q1 is supplied to the terminal 401, an L level output is generated from the NAND circuit 411, and immediately the NAND circuit 412
gate is closed, and input of the request signal REQ2 is prohibited.

At this time, the setting force of the R-S flip-flop 420 becomes S or H level, the Q output becomes L level, and the terminal 461
The exclusive signal GRANT1 is generated to permit the microprocessor 10 to operate the shared resources on the shared memory 30.

On the other hand, the ``XL'' level output of the NAND circuit 411 is supplied to the R-S flip-flop 4400 set S through the OR circuit 430, which sets the Q output to ``L'' and generates the input prohibition signal P, thereby disabling the shared resource. Indicates that the operation is in progress.

The output with an L level, that is, the input prohibition signal P, is supplied to the NAND circuits 411 and 412, and the input of REQI and REQ2 is prohibited, but the Q output of the R-S flip-flop 420 maintains the L level. Then, a proprietary signal GRANT1 is supplied to the microprocessor 10.

When the microprocessor 10 finishes operating the shared resource, it supplies a reset signal R8T1 to the terminal 451, and the R-S
The flip-flop 440 is reset and the Q output is
“It becomes a level.

Therefore, the human power prohibition signal P disappears, and the NAND circuits 411, 4
12 are opened together and the request signal REQ1 or REQ
It will be in the state of waiting for the input of 2.

(3) When a shared resource is being operated by one microprocessor while a request signal is provided by the other microprocessor.

For example, as in case (2) above, while the microprocessor 10 is operating the shared resource, the NAND circuit 411
, 412 are both closed.

Therefore, even if the request signal REQ2 is supplied to the terminal 402 from the other microprocessor 20, the input of this request signal REQ2 is prohibited, and therefore the exclusive signal G
RANT2 is not generated until the operation of the microprocessor 10 is completed and the reset signal R8T1 is supplied to the terminal 451.

In the embodiment of the present invention shown in FIG. 3, an example was shown in which the R-S flip-flop 440 was used as the signal generation circuit, but a monostable multivibrator was used and the terminals 451,
452. OR circuit 450 may be omitted.

However, in this case, the time the microprocessor operates on the shared resource is determined by the time constant of the monostable multivibrator.

Therefore, such a configuration is effective in a microprocessor system in which the operation time for shared resources is fixed.

Furthermore, the microprocessor has a function to temporarily stop the processor for memory with slow access time, and the microprocessor stops its operation by supplying an "L" level signal to the READY or WAI signal. .

Therefore, as shown in the portions 47 and 48 surrounded by broken lines in FIG. By supplying this, the mutual exclusion function of the microprocessor can be provided.

For example, while the microprocessor 1 is operating the shared memory, the microprocessor 20 sends the request signal REQ.
2 is supplied to terminal 402, terminals 402 and 462
Since both are at the H level, the output of the NAND circuit 472 becomes L, and the microprocessor 20 stops operating.

Therefore, the microprocessor 20 stops operating and waits for the operation of the shared resource until the microprocessor 10 completes the operation of the shared resource.

As described above, the circuit of the present invention allows two microprocessors to operate the system's shared resources in a mutually exclusive manner, eliminating the need for checking the usage status of shared resources using a program as in the past. Operation time (
overhead) can be eliminated.

Furthermore, the circuit configuration is simple, and its industrial effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor system using the microprocessor mutual exclusion circuit of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a connection diagram of an embodiment of the present invention. 10.20...Microprocessor, 11.2
1... Pass line, 30... Shared memory, 40... Mutual exclusion circuit, 41...
Competitive circuit, 42... Proprietary signal generation circuit, 44.
...Signal generation circuit.

Claims (1)

[Scope of utility model registration request] In a microprocessor system in which a shared resource shared by two microprocessors is operated in a mutually exclusive manner, a signal generation circuit outputs an input prohibition signal during operation of the shared resource, and one or both of the two microprocessors. When the status signal indicates that the shared resource is being manipulated, the input of the request signal is prohibited, indicating that the shared resource is not being manipulated. and a competition circuit that inputs one of the request signals, and an exclusive signal generation circuit that generates an exclusive signal that allows one of the two microprocessors to monopolize the shared resource based on the output of the competition circuit, When a request signal is supplied from one of the two microprocessors mentioned above, a proprietary signal is supplied to that one microprocessor, and while one microprocessor is operating a shared resource, a request signal is received from the other microprocessor. A microprocessor mutual exclusion circuit characterized in that even if a proprietary signal is received by the other microprocessor, the exclusive signal is not supplied to the other microprocessor.