JPH04308955A - Multiprocessor device - Google Patents

Abstract

PURPOSE:To utilize equally and validly a shared bus without any competition even when a slave processor which doesn't make a request for occupying the shared bus exists. CONSTITUTION:This device is equipped with a shared bus 4 with which a master processor 1 and plural slave processors 21-23 are connected with, slave processors 21-23 which output a request signal 6 for occupying the shared bus 4, master processor 1 which recognizes the number of the slave processors which make the request for occupying the shared bus 4 by the request signal 6, and outputs an interruption signal 5 for a time required for occupying the shared bus 4 by the recognized number of slave processors, and delay means 31-33 which delay the interruption signal 5 for the time required for occupying the shared bus 4 by one slave processor according to the request signal.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention relates to a multiprocessor device, and particularly to a multiprocessor device that allows each slave processor to monopolize a shared bus equally and effectively when a plurality of slave processors access the shared bus at the same time. Regarding equipment.

0002

2. Description of the Related Art In recent years, in order to improve the performance of systems such as workstations, multiprocessor systems using a plurality of microprocessors have become mainstream. In this type of multiprocessor device, a bus arbitration circuit is provided so that when a plurality of slave processors access the shared bus at the same time, they can use the shared bus equally. As an example,
There is a configuration as shown in Japanese Unexamined Patent Publication No. 2-68649. The configuration will be described below with reference to FIGS. 4 and 5. It is assumed that the number of slave processors in the multiprocessor device described here is three.

As shown in FIG. 4, the multiprocessor device includes a timer 8 that outputs an interrupt signal 5 at regular intervals, a master processor 1 that includes a shared RAM 7 and receives the interrupt signal 5 as input, and a master processor 1 that receives the interrupt signal 5 as input. Slave processors 21 to 33 having built-in delay means 31 to 33 for delaying
23, master processor 1 and slave processor 2
It consists of a shared bus 4 connected to nodes 1 to 23. The operation of the multiprocessor device configured as described above will be described below.

[0004] The timer 8 outputs an interrupt signal 5 at regular intervals, and outputs an interrupt signal 5 to the master processor 1 and slave processor 2.
1 to 23. Master processor 1 writes data to shared RAM 7 in response to this interrupt signal 5. When each slave processor 21 to 23 reads data from the shared RAM 7, each slave processor 21 to 23
The time during which the shared bus 4 is occupied by the common bus 4 is determined to some extent, and this time is determined in advance, and the delay means 31 to 33 are set so that the interrupt signal 5 arrives at intervals of that time.
Set the delay time. That is, as shown in FIG. 5, if the delay time of the delay means 31 is T1 (=0), the delay time 32 of the delay means is T2, and the delay time of the delay means 33 is T3, the usage state of the shared bus 4 is slave processor 21
23 equally acquire the right to use the bus without competing.

[0005]

[Problem to be Solved by the Invention] However, in such a configuration of a multiprocessor device, even if a slave processor does not request exclusive use of the shared bus 4, the right to use the bus is always given equally to all slave processors. Therefore, there is a problem in that there is wasted time when none of the slave processors uses the shared bus.

SUMMARY OF THE INVENTION Accordingly, the present invention is intended to solve the above-mentioned problems, and an object thereof is to provide a multiprocessor device that can equally and effectively monopolize a shared bus.

[0007]

[Means for Solving the Problems] A multiprocessor device of the present invention includes: a shared bus to which a master processor and a plurality of slave processors are connected; a slave processor that outputs a request signal for exclusive use of the shared bus;
A master processor that recognizes the number of slave processors requesting exclusive use of the shared bus based on this request signal, and outputs an interrupt signal for the time necessary for the recognized number of slave processors to exclusive use of the shared bus. and a delay means for delaying the interrupt signal by the time necessary for one slave processor to monopolize the shared bus depending on the state of the request signal.

[0008]

According to the present invention, with the above-described configuration, an interrupt signal delayed by the delay means is given only to the slave processor requesting exclusive use of the shared bus, so that the shared bus can be equally and effectively occupied.

[0009]

Embodiments Examples of the present invention will be described with reference to the drawings. However, it is assumed that the number of slave processors in the multiprocessor device of this embodiment is three.

A block diagram of one embodiment of the present invention is shown in FIG. In FIG. 1, the multiprocessor device of this embodiment includes a master processor 1 and a plurality of slave processors 21.
- 23 are connected, slave processors 21 to 23 that output a request signal 6 for exclusive use of the shared bus 4, and the number of slave processors that request exclusive use of the shared bus 4 using the request signal 6. The master processor 1 recognizes the shared bus 4 and outputs the interrupt signal 5 for the time required for the recognized number of slave processors to monopolize the shared bus 4, and the interrupt signal 5 is sent to one slave processor depending on the state of the request signal. Delay means 31 whose number corresponds to the slave processors delay the time-divided interrupt signal 5 necessary to monopolize the shared bus 4.
It consists of ~33. However, other elements (e.g. ROM
, FPU, etc.) are not shown. Also, a indicates an interrupt signal 5 from the previous stage, b a request signal 6, c an interrupt signal to the slave processor, and d an interrupt signal to the subsequent stage.

An embodiment of the delay means 31 to 33 used here is shown in FIG. In the delay means 31 to 33, the latch 24 stores the state of the request signal c, and when the request signal c is high, the interrupt signal a from the previous stage is delayed by the delay circuit 25, and the corresponding slave processor is sent to the slave processor. An interrupt signal c is given, and the same signal is given to the subsequent stage. Further, when the request signal c is low, the interrupt signal a from the previous stage is given to the next stage without going through the delay circuit 25, and the corresponding slave processor is given the low level interrupt signal c.

Next, the operation of this embodiment will be explained using FIG. 3. Assume that slave processors 21 and 23 request exclusive use of shared bus 4. At this time, the slave processors 21 and 23 output the request signal 6 to the master processor 1. The request signal 6 is sent to delay means 31 to 33 corresponding to each slave processor.
It is also output. Upon receiving the request signal 6, the master processor 1 uses a known decoding means to recognize the number of slave processors that have requested exclusive use of the shared bus 4 from the state of the request signal 6. At the same time, interrupt signals 5 are output for the time required for the recognized number of slave processors to monopolize the shared bus 4. That is, the interval between interrupt signals 5 is set equal to the number of recognized slave processors.

First, since the slave processor 21 requests exclusive use of the shared bus 4, the delay means 31 outputs the interrupt signal 5 delayed by T1 (the delay time of the delay means 31 to 33) to the slave processor 21. shared bus 4
At the same time, the delayed interrupt signal 5 is also output to the delay means 32 at the next stage.

Next, the slave processor 22 uses the shared bus 4.
Therefore, the delay means 32 does not output the interrupt signal 5 to the slave processor 22, and outputs the input interrupt signal 5 to the next stage delay means 33 without delay.

Next, the slave processor 23 requesting exclusive use of the shared bus 4 outputs the interrupt signal 5 delayed by T1 to the slave processor 23 and makes the shared bus 4 exclusive. You can own it without having to use it.

[0016] When the master processor 1 has completed as many cycles as the number of slave processors recognized by the master processor 1, the master processor 1 receives the next request signal 6 again and recognizes the number of slave processors that have requested exclusive use of the shared bus 4. and performs the same operation as above. Here, one cycle is defined as the time during which one slave processor exclusively uses the shared bus. Therefore, the slave processors 21 and 23 that requested exclusive use of the shared bus 4 do so without competing with each other. Furthermore, the slave processor 22 that does not request exclusive use of the shared bus 4 is not given the right to use the shared bus, and is effectively using the shared bus.

As described above, according to this embodiment, the selectively delayed interrupt signal 5 is given only to the slave processor requesting exclusive use of the shared bus 4. The shared bus can be used equally and effectively without causing contention.

In this embodiment, as many delay means 31 to 33 as there are slave processors are used, but there is no need to use as many delay means as there are slave processors; for example, one delay means may be used. Needless to say, it may be configured.

[0019]

As explained above, in the present invention, a selectively delayed interrupt signal is given only to the slave processor requesting exclusive use of the shared bus.
Slave processors can use the shared bus equally and effectively without contention on the shared bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor device in one embodiment of the present invention.

FIG. 2 is a circuit diagram of one embodiment of a delay means.

FIG. 3 is an operational diagram of the multiprocessor device of the present invention.

FIG. 4 is a block diagram of a conventional multiprocessor device.

FIG. 5 is an operational diagram of a conventional multiprocessor device.

[Explanation of symbols]

1 Master processor 4 Shared bus 5 Interrupt signal 6 Request signal 7 Shared RAM 21-23 Slave processor 31-33 Delay means

Claims (1)

[Claims] 1. A shared bus to which a master processor and a plurality of slave processors are connected; a slave processor that outputs a request signal for exclusive use of the shared bus; and a slave processor that outputs a request signal for exclusive use of the shared bus; a master processor that recognizes the number of slave processors and outputs an interrupt signal for the time necessary for the recognized number of slave processors to monopolize the shared bus; A multiprocessor device comprising: delay means for delaying a time necessary for one slave processor to exclusively occupy the shared bus.