JPS63247857A - Access arbitrating circuit - Google Patents

Abstract

PURPOSE:To prevent the delay of the access time of a device having a low priority by using a means which permits the next access for a prescribed access request when plural access requests have conflicts. CONSTITUTION:The access requests of three devices (not shown here) are latched by a latch circuit 1 via access request lines 101, 102 and 103 and supplied to an arbitrating logic circuit 3. The circuit 3 performs arbitration based on an input pattern and delivers the result of arbitration to a latch circuit 4 as an access permission signal. This permission signal is sent back to said devices via access permission lines 115, 116 and 117. The latch circuits 1, 2 and 4 latch input signals in the same phase and synchronously with each other. Furthermore the output result of the circuit 4 is sent to the circuit 2 via a control line 114.

Description

TECHNICAL FIELD The present invention relates to an access arbitration circuit, and more particularly to an access arbitration circuit that arbitrates access rights when a plurality of devices share one hardware resource.

Conventionally, this type of access arbitration circuit has been configured to grant access permission to a plurality of access requests according to a predetermined fixed priority order. The priority logic at this time is that, as shown in FIG. 4, when two or more of the access requests from the three access request lines 201, 202, and 203 conflict, the access request with the higher priority is It is selected by the arbitration logic circuit 11, and access permission signals are outputted via access permission lines 211, 212, and 213.

In FIG. 4(b), the access request line 201 on the input side
, 202 , 203 indicate the presence or absence of an access request, and rlJ and "0" from the access permission lines 211 , 212 , 213 on the output side
” indicates whether access permission is granted.

Here, the access request from the access request line 201 has the first priority, the access request from the access request line 202 has the second priority, and the access request from the access request line 203 has the third priority.

In such conventional access arbitration circuits, a fixed priority is assigned to each access request, so if a device with a high priority frequently makes access requests, the access of a device with a low priority is This has the disadvantage that requests are no longer granted and the access time of low priority devices becomes slow.

Purpose of the Invention The present invention was made in order to eliminate the drawbacks of the conventional devices as described above, and it is possible to prevent the access time of a device with a low priority from becoming slow when a device with a high priority makes frequent access requests. The purpose of the present invention is to provide an access arbitration circuit that can prevent the above problems and improve the performance of the entire system.

Structure of the Invention The access arbitration circuit according to the present invention is an access arbitration circuit that selects one access request from among a plurality of access requests having predetermined priorities and permits access according to the priority order. means for excluding the access request that has been granted from the target of next access, and means for permitting next access to a predetermined access request when there is a continuous conflict among the plurality of access requests. It is characterized by

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the access arbitration circuit according to one embodiment of the present invention is comprised of latch circuits 1.2.4 and arbitration logic circuit 3. Further, this access arbitration circuit arbitrates access rights when three devices (not shown) share one hardware resource (not shown).

These devices are respectively device #1. #2. #3, device #1. #2. The access request #3 is transmitted to the latch circuit 1 through access request lines 101, 102, and 103, respectively, and latched by the latch circuit 1.

Device #1 latched by this latch circuit 1. #2.
Each access request #3 is further latched by the latch circuit 2 and then input to the arbitration logic circuit 3.

The arbitration logic circuit 3 performs arbitration according to the input pattern, and outputs the arbitration result to the latch circuit 4 as an access permission signal. The latch circuit 4 latches this access permission signal, and this access permission signal is passed through access permission lines 115, 116 and 117 to device #1. #2
．． Returned to #3. .

Here, the latch circuit 1.2.4 has an O-lock signal line 104.
The input signal is latched in phase in synchronization with the clock signal from. Further, the output result of the latch circuit 4 is transmitted to the latch circuit 2 through the control line 114. Therefore, when the access of the permitted access request is completed, if the permitted access request continues to exist in the latch circuit 2, it is reset. In addition, latch circuit 2.
4 are access request lines 101 and 102 after the access is completed.
, 103 and initialized.

By doing this, even if an access request is once granted and the device that executed the access makes another access request, the granted access request will be set at the next latch timing immediately after the access ends in the latch circuit 2. Not done.

FIG. 2 is a diagram showing the arbitration logic of the arbitration logic circuit 3 of FIG. 1. In the figure, the output line 10 of the latch circuit 2 on the input side
"1" and "0" from 8, 109 and 110 respectively indicate the presence or absence of an access request, and "1" from output lines 111, 112 and 113 to latch circuit 4 on the output side
” and “0” respectively indicate whether access is permitted. Here, the output lines 108, 1 of the latch circuit 2 on the input side
09 and 110 are devices #1 and #2, respectively. These are the input lines for the access request from device #3 to the arbitration logic circuit 3, and the output lines 111, 112, and 113 are the input lines for the access request from device #1. #
2. This is an output line to the latch circuit 4 for permission to access #3.

FIG. 3 is a diagram showing a configuration example of the arbitration logic circuit 3 for realizing the arbitration logic of FIG. 2. FIG. 3(a) shows an example of a configuration using AND gates 5 to 8 and an OR gate 9, and FIG. 3(b) shows an example of a configuration using a ROM (read only memory) table. In FIG. 3(b),
The ROM 10 is supplied with addresses through signal lines 108, 109, and 110, and outputs the arbitration logic shown in FIG. 2 as data through signal lines 111, 112, and 113.

The operation of one embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

Now, device #1. #2. Assume that #3 all generate access requests consecutively. Latch circuit 1 is connected to these devices #1. #2. The access request ("1") from #3 is latched and output to the latch circuit 2 via output lines 105, 106, and 107. Latch circuit 2 is latch circuit 1
latches the output signal from the output lines 108 and 109
, 110 to the arbitration logic circuit 3. At this time, the latch circuit 2 outputs the output signal from the latch circuit 1 as it is to the arbitration logic circuit 3 since the output result of the latch circuit 4 from the control line 114 is rOJ.

In the arbitration logic circuit 3, in response to the input of rllllJ, N O
Since OJ is output (see Figure 2), these devices #1. #2. Device # among the access requests from #3
The access request from device #1 is selected, and permission to access device #1 is output to latch circuit 4 via output line 111. In the latch circuit 4, this access permission to the device #1 is sent back to the device #1 via the access permission line 115, and the output result is output to the latch circuit 2 via the control line 114.

The latch circuit 2 resets the access request from the device #1 that was subsequently input through the output line 105 from the latch circuit 1 based on the output result of the latch circuit 4 inputted by the Fa 114, and resets the access request from the device #1 that was inputted subsequently by the output line 105 from the latch circuit 1. The access request from #3 is output to the arbitration logic circuit 3.

The arbitration logic circuit 3 outputs roll in response to the input of rollJ.
oJ is output, so these devices #1. #2. #
Among the access requests from device #3, the access request from device #2 is selected, and permission to access device #2 is output to latch circuit 4 via output line 112. In the latch circuit 4, permission to access the device #2 is sent back to the device #2 via the access permission line 116, and this output result is transmitted to the latch circuit 2 via the control line 114.
Output to.

In the latch circuit 2, according to the output result of the latch circuit 4 input through the control line 114, the output line 1 from the latch circuit 1 is
06, and outputs the access request from devices #1 to #3 to the arbitration logic circuit 3.

In the arbitration logic circuit 3, rool is input in response to the input of N0IJ.
J is output, so these devices #1. #2. #3
The access request from device #3 is selected from among the access requests from device #3, and permission to access device #3 is output to latch circuit 4 via output line 113. In the latch circuit 4, the access permission to the device #3 is sent back to the device #3 via the access permission line 111, and the output result is output to the latch circuit 2 via the control line 114.

By the above operation, device #1. #2. #3 Assuming that all access requests occur consecutively, at this time,
Device #1. #2. #3 is in a contention state, but the order in which access is granted by the arbitration logic circuit 3 is device #1. Device #2゜Device #3. Device #1. Device #2. It becomes... Also, device #1
If device #2 and device #2 generate access requests consecutively, device #1 and device #2 will repeat, and 1
Two devices cannot perform consecutive accesses.

In this way, the latch circuit 2 excludes access requests for which access is permitted by the arbitration logic circuit 3 from the next access target based on the output result from the latch circuit 4 input via the control line 114. When there are successive competing access requests, the priority order at the time of access arbitration can be fixed by allowing the next access to the access request determined by the arbitration logic set in advance in the arbitration logic circuit 3. First, the priority order can be made variable depending on the status of the access request. Thus, one or more devices #1. #2. It is possible to prevent other devices from being inaccessible for a long period of time due to continuous or alternate access by #3. therefore,
Since it is possible to guarantee that access is always granted within a certain finite number of access cycles for all access requests, the performance of the entire system can be improved.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, there is provided a means for excluding an access request to which access is permitted from among a plurality of access requests having a predetermined priority order from the next access target; When there are continuous conflicts, by providing a means for granting the next access to a predetermined access request, if a device with a high priority makes frequent access requests, the device with a low priority can This has the effect of preventing slow access times and improving the performance of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the arbitration logic of the arbitration logic circuit of FIG. 1, and FIG.
This figure shows a configuration example of an arbitration logic circuit for realizing the arbitration logic of FIG. 2, and FIG. 4 is a diagram showing the arbitration logic of a conventional arbitration logic circuit. Explanation of symbols of main parts 1.2.4...Latch circuit 3...Arbitration logic circuits 101-103...Access request lines 115-1
17... Access permission line 114... Control line

Claims (1)

[Claims] An access arbitration circuit that selects one access request from among a plurality of access requests having predetermined priorities according to the priority and grants access,
Means for excluding the access request for which access has been permitted from being targeted for next access, and means for permitting next access to a predetermined access request when there is successive conflict among the plurality of access requests. An access arbitration circuit characterized by: