JP2538874B2 - Common bus arbitration method - Google Patents

Description

The present invention relates to a common bus arbitration method capable of effectively arbitrating access (bus use request) from a plurality of bus masters to a system bus.

(Prior Art) Multiple Computers (Processors) Sharing a System Bus
In the case of a system that performs data transmission via the system bus, a data transmission collision may occur on the system bum. Therefore, conventionally, each computer that mainly uses the system bus is set as a bus master, and a bus use request signal is generated from each of these bus masters, and a bus use permission signal is selectively given to the bus master. Is being done. At this time, a plurality of bus request signals may occur simultaneously. For this reason, an arbitration circuit (arbiter) is used to arbitrate this and give a bus use permission signal to only one bus master.

By the way, there are the following three arbitration methods for such a bus.

One of them is called a serial priority determination method (daisy chain), and includes a plurality of bus masters 1a, 1b, ...
1n is connected in series as shown in FIG.

Then, each bus master can generate a bus request only when the bus master on the upper side does not generate a bus request. In other words, the bus master that has generated the bus request prohibits the bus master on the lower side from generating the bus request.

However, in this bus arbitration method, the arbitration process is very simple, but on the other hand, the delay time for the arbitration process becomes longer in proportion to the number of bus masters that make up the chain, and its priority is fixed. There is a problem that it will end up.

On the other hand, the parallel priority determination method as shown in FIG. 5 uses a plurality of bus masters 1a, 1b, to 1n in a multi-bus system.
Bus requests that are output in synchronization with each other are input in parallel to the arbitration circuit 2 including a priority encoder and a priority decoder, the bus requests are accepted with a predetermined priority, and a bus request is issued to the bus master. Is to give permission to use.

According to this method, the problem of delay time described above is solved. However, the problem that the priority for the bus request is fixedly determined cannot be solved.

On the other hand, the arbitration circuit side cyclically inquires of each bus master whether or not there is a bus request, and when the bus master generating the bus request is detected, the bus master is permitted to use the bus. There is a round robin system that gives.

According to this method, the bus requests of the respective bus masters are sequentially searched cyclically, so that the bus requests can be equally received. However, there is a problem that as the number of bus masters increases, the time (bus arbitration time) for searching these bus masters cyclically becomes longer.

(Problems to be Solved by the Invention) As described above, in each of the arbitration methods described above, there are problems such as a long arbitration processing time and a fixed priority for a bus request. is there.

For example, if the bus request is treated equally by the round robin method and the arbitration processing time is shortened, an extremely high-speed search circuit is required, which makes the realization extremely difficult.

The present invention has been made in consideration of such circumstances, and an object thereof is to handle bus requests from a plurality of bus masters equally and to perform bus arbitration at a high speed. It is an object of the present invention to provide a common bus arbitration method capable of improving the bus usage efficiency by preventing all output bus requests from being blocked at the same time.

[Structure of the Invention] (Means for Solving the Problems) The first aspect of the present invention is to select a bus request signal output from a plurality of bus masters in a multi-bus system in synchronization with each other with a predetermined priority. A priority encoder, a mask circuit for selectively blocking the input of the bus request signal to the first priority encoder according to a mask pattern, and a predetermined control signal,
For example, according to a signal given from the outside or a signal internally generated according to the previous arbitration result, the mask
A second priority encoder for selecting a bus request signal from the bus master with a predetermined priority when the first priority encoder does not operate. Is.

(Operation) According to the present invention, the input of the bus request signal to the first priority encoder is blocked according to the mask pattern, so that the priority of the bus request in the first priority encoder is set to the mask pattern. It can be arbitrated by changing it accordingly. Then, in the mask circuit, the first priority
If only a bus request is provided with blocked input to the encoder, the second priority encoder will back up the first priority encoder to arbitrate for the bus request.

As a result, bus requests from a plurality of bus masters are treated equally, and arbitration is performed at high speed by parallel processing. Furthermore, the problem that all the bus requests output from the bus master are blocked at the same time is prevented,
Since any bus request is always accepted, the bus usage efficiency can be improved and the system throughput can be improved.

(Embodiment) Hereinafter, an embodiment method of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an arbitration circuit in a multibus system configured by applying the system of the first embodiment.

This arbitration circuit has first and second priority encoders 11 and 12 which have their enable control terminals connected in cascade to input bus request signals from a plurality of bus masters in parallel, respectively. Of the priority encoders 11 and 12 are wired-ORed and input, and a priority decoder 13 that selectively outputs a bus use permission signal to the bus master, and a shift register 14 that generates a mask pattern according to a control signal. , And the first priority encoder according to the mask pattern generated by the shift register 14.
And a mask circuit 15 for selectively blocking a bus request signal from the bus master for 11.

First and second priority encoders 11, 12
Is, for example, a semiconductor circuit (chip) manufactured by TI (type name: LS348), receives a bus request signal from a bus master in parallel, receives the bus request signal in a preset priority order, and receives the bus request signal. It produces an output corresponding to the signal. Here, the bus request signals having a large number value are preferentially accepted with respect to the bus request signals 0 to 7.

The enable control terminal of the first priority encoder 11 is grounded, and when a bus request signal is input, a priority selection operation for the bus request signal is always performed. Further, the enable control terminal of the second priority encoder 12 is connected to the enable control output of the first priority encoder 11, and only when the first priority encoder 11 does not operate, the input bus request A priority selection operation for a signal is performed.

Here, the mask circuit 15 is composed of seven gate circuits that selectively block the input of the bus request signals of Nos. 1 to 7, respectively, and the bus request signal of No. 0 has the first priority level as it is. It is designed to be input to the encoder 11.

Further, the shift register 14 uses a control signal externally input as a clock, and cyclically generates a mask pattern in which the bus request signal with the highest priority side sequentially masks.
That is, a mask pattern for masking only bus request signal No. 7 is generated at the first clock timing, and a mask pattern for masking bus request signals No. 7 and 6 is generated at the next clock timing. Then, while increasing the number of bus request signals to be masked one after another,
After generating a mask pattern for masking each of the bus request signals up to the number, all of them are reset (the output of the mask pattern is stopped) at the next timing.

Thereafter, the mask pattern which changes in this way is cyclically generated in synchronization with the clock.

The mask circuit 15 is thus provided with a shift register.
According to the mask pattern generated by 14, the input of bus request signals No. 1 to No. 7 to the first priority encoder 11 is selectively blocked.

On the other hand, the second priority encoder 12 receives the bus request signals Nos. 1 to 7 which are selectively blocked by the mask circuit 15 in the same priority order as the first priority encoder 11. Has been done. Since the 0th bus request signal is unconditionally input to the first priority encoder 11, it is not input to the second priority encoder 11.

The priority encoder 13 is, for example, a semiconductor circuit (chip) manufactured by TI (type name: LS138), and the output of the first priority encoder 11 that operates under mask control in this manner or the first In accordance with the output obtained from the second priority encoder 12 when the priority encoder 11 of the above does not operate, the bus permission signal is selectively output to the bus master that has generated the bus request signal that has been preferentially accepted. are doing.

According to the arbitration circuit configured as described above, the generation of the bus use permission signal for the bus request signals from the plurality of bus masters is as follows.

Now, if the bus request signal is given only from a certain one bus master and the input of the bus request signal to the first priority encoder 11 is not blocked by the mask circuit 15, the first priority encoder 11
Accepted by. As a result, the first priority encoder 11 gives an output corresponding to the acceptance number of the bus request signal to the priority decoder 13, and the bus use permission signal is given to the bus master which has issued the bus request. Become. Further, when the mask circuit 15 blocks the input of the bus request signal to the first priority encoder 11, the first priority encoder 11 does not operate. As a result, the second priority encoder 12 receives the bus request signal, and the second priority encoder 12 receives the output of the second priority encoder 12.
A bus use permission signal is given to the bus master that generated the bus request.

On the other hand, when the bus request signals are simultaneously given from a plurality of bus masters and are inputted to the first priority encoder 11, the priority encoder 11 accepts only one bus request signal in the above-mentioned priority order. Become. At this time, according to the mask pattern described above, if the bus request signal with the higher priority is masked,
The first priority encoder 11 will select the bus request signal that is preferentially determined among the bus request signals that have been input without being masked. Therefore, the priority for a plurality of bus request signals is changed.

When all of the plurality of bus request signals are blocked by the mask circuit 15, the first priority
The encoder 11 will not operate, and the second priority encoder 12 will operate instead. Therefore, the second priority encoder 12 backs up the function stoppage caused by the masking process of the first priority encoder 11, and the bus request signal is accepted in a predetermined priority.

As described above, according to the present arbitration circuit, bus arbitration is performed at high speed by the parallel selection and acceptance of bus requests by the priority encoders 11 and 12. At the same time, the operation of the mask circuit 15 according to the mask pattern masks the bus request signals of higher priority in the priority encoder in order, so that the priority can be changed. As a result, it is possible to equalize the acceptance of a plurality of bus request signals.

By the way, in the above-described embodiment, the mask pattern is sequentially changed by the control signal given from the outside, but it is also possible to control this internally.

FIG. 2 is a schematic configuration diagram of an arbitration circuit showing the embodiment. The same parts as those shown in FIG. 1 are designated by the same reference numerals.

This arbitration circuit differs from the previous embodiment in that the shift register 14 described above as the mask pattern generation circuit is used.
Instead of the above, a decoder 16 which operates by receiving the outputs of the priority encoders 11 and 12 is used. This decoder 16 has the first or second priority encoders 11 and 12 when arbitration is performed for the bus request signal at a certain timing as shown in the operation mode of FIG.
Is latched, and a mask pattern corresponding to the latched data is generated at the next timing.

Specifically, when a bus request signal having a certain priority is accepted, at the next timing, all the priorities of the bus request signal and the bus request signals having a higher priority than that are blocked. The mask pattern is generated.

In this way, according to the result of the previous arbitration, by internally generating a mask pattern that minimizes the priority for the bus request, it becomes possible to further equalize a plurality of bus request signals. Therefore, the same effect as that of the above-described embodiment can be obtained.

The present invention is not limited to the above embodiments. For example, the number of bus requests to be arbitrated and the priority in the priority encoder can be arbitrarily set. Further, the method of generating the mask pattern and the mode of controlling the change of the mask pattern can be appropriately modified. In short, the present invention can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] As described above, according to the present invention, a plurality of bus requests can be treated equally, and arbitration processing thereof can be executed at high speed, that is, in a short time.

Furthermore, by providing the second priority encoder for backup, it is possible to prevent all the bus requests output from the bus master from being blocked at the same time, and always accept any one of the bus requests. Therefore, it is possible to improve the use efficiency of the bus, and it is possible to increase the throughput of the system.

Therefore, efficient use of the system bus becomes possible,
It is possible to achieve a great practical effect by improving the throughput of the entire system and further improving the processing capacities of a plurality of processors sharing the system bus.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an arbitration circuit showing a first embodiment of the present invention, FIG. 2 is a schematic configuration diagram of an arbitration circuit showing a second embodiment of the present invention, and FIG. 3 is a second implementation. FIGS. 4 and 5 showing the operation mode of the decoder in the example, respectively, are diagrams for explaining the arbitration method in the conventional multi-bus system. 11 …… first priority encoder, 12 …… second
Priority encoder, 13 ... Priority decoder, 14 ... Shift register (mask pattern generation circuit), 15 ... Mask circuit, 16 ... Decoder (mask pattern generation circuit).

Claims (4)

(57) [Claims] 1. A system provided with an arbitration circuit for arbitrating access to a system bus from a plurality of bus masters, wherein the arbitration circuit selectively outputs a bus request signal from the bus master with a predetermined priority. A priority encoder, a mask circuit for selectively blocking input of the bus request signal to the first priority encoder according to a mask pattern, and means for changing the mask pattern according to a predetermined control signal. A second bus for selectively outputting the bus request signal with a predetermined priority when all the bus request signals from the bus master are blocked by the mask circuit at the same time and the first priority encoder does not operate. A priority encoder and the first and second priority encoders Common bus arbitration scheme characterized by comprising a decoder for alternatively generating a bus grant signal for the bus master in accordance with the output of the encoder. 2. The common bus arbitration system according to claim 1, wherein the second priority encoder operates by receiving an enable signal from the first priority encoder. 3. The common bus arbitration system according to claim 1, wherein the predetermined control signal for changing the mask pattern is internally generated at the end of the arbitration or externally applied. 4. The common bus arbitration method according to claim 1, wherein the change of the mask pattern minimizes the selection priority for the previously selected bus master.