RU2710912C1 - Device for generating priorities when accessing shared memory of several devices - Google Patents

Abstract

FIELD: data processing.SUBSTANCE: invention relates to information processing. Control electronic computer comprises several devices: processor, four input/output channels (IOC), having direct access to common memory (CM), and a program timing device (PTD). Prioritization device (PD) is intended to resolve conflict situations when accessing CM. PD establishes sequence of access to CM from processor and IOC at simultaneous request. IOC have equal priority relative to each other and higher priority in relation to processor. Processor processes information received by IOC from external sensors and generates information for dispensing by means of IOC to control elements of system. Exchange with external subscribers is performed by input/output channels, besides, each of four IOC has its own set of subscribers.EFFECT: creation of a device for generating priorities, inclusion of which in a control machine will allow increasing the speed of data processing with simultaneous access to CM of several devices.1 cl, 2 dwg, 2 tbl

Description

The invention relates to digital technology in the field of information processing and can be used in the space industry to resolve conflicts between individual devices when accessing shared memory in direct access mode.

A device for conflict resolution is described in the copyright certificate No. 1325479 of March 24, 1986, “Priority access to shared memory”, containing two channels for organizing the exchange of two computers with shared memory (OP), and containing two triggers (1 and 2 ), storing requests from two computers, a block of the sequence of execution of incoming requests (3) and logic circuits (4-11) for generating a set of signals for each channel. In the specified device, the order of processing requests is not installed and is determined by the order of their arrival. Processing the next request is performed only after the processing of the first. When a request is made on one of the channels, the device blocks access on the other channel.

A device for conflict resolution is described in the patent for invention No. 2152072 dated 03/02/1999 - “Variable priority device”, containing n - bit register of requests (1) for fixing incoming requests, n 1 - bit priority registers (20), inputs which are inputs for setting priority codes for request sources, a priority block (3) and a set of logical elements “AND” and “OR” for generating signals arriving at the information inputs of the priority block. Signals for setting the mode 4 ₁ , 4 ₂ and control signals 5 ₁ ... 5 _n together with the priority codes at the inputs of 1 - bit priority registers are designed to specify the sequence of processing requests. Priority can be changed in the process. After prioritizing devices, applications are also processed sequentially, i.e. the next application is processed after the processing of the previous one.

A device for conflict resolution is described in the patent for invention No. 2320001 dated June 23, 2006. “Priority request servicing device”, containing a request register (1), each bit of which has a priority, a clock counter (10), the code of which after decryption (11) allows the passage of requests in descending order of their priorities through the keys (12) to the output of the device. In this device, priority is set rigidly, and processing of a lower priority application is performed after processing of a higher priority application.

The disadvantage of the above devices may be a significant delay in processing applications of individual devices, while accessing the OP of several devices.

The objective of the invention is to develop a device that provides guaranteed access to any of the four devices (input / output channels) to the OP with a certain frequency for the operational reception and delivery of information to digital computer subscribers.

The figure 1 shows a diagram of the inclusion of UVP in a computer.

The figure 2 presents the structural diagram of the UVP, which includes the following elements:

1 shaper of cycle numbers (FSC);

2 priority decoder (DShPR);

3 channel shaper (FZK);

4 shaper locks (FBL).

The signals according to figure 2:

ММЦ - an input label of a machine cycle;

T1 is the first clock signal;

T2 is the second clock signal;

ЗП0 - the first input signal;

ZP1 - the second input signal;

ЗП2 - the third input signal;

ZP3 - the fourth input signal;

ZPRO - processor request;

НЦ0 - cycle number "1";

NTs1 - cycle number "2"

НЦ2 - cycle number "3";

NTs3 - cycle number "4";

RZK0 - the first permission signal;

RZK1 - the second permission signal;

RZK2 - third permission signal;

RZK3 - the fourth permission signal;

ZKP0 - the first signal of the application;

ZKP1 - the second signal of the application;

ZKP2 - the third signal of the application;

ZKP3 - the fourth signal of the application;

BLKVV0 - the first blocking of signals;

BLKVV1 - second signal blocking;

BLKVV2 - third signal blocking;

BLKVV3 - fourth signal blocking;

BLPR0 - blocking the processor request.

Formed in the software temporary device (PVU) signals MMC, T1 and T2 are fed to the input of the UVP. From UVP, the signals of MMC and T1 arrive at the FSC (1). The signals NTs0-NTs3 come from the Federal Scientific Center (1) to the DSPR (2). Signals ЗП0-ЗП3, generated by the corresponding КВВ0-КВВ3, are fed to the input of the UVP, and from the input of the UVP they are fed to the ДСПР (2) and ФЗК (3), and the signals ФЗК0-РЗК3 from ДШПР (2) are fed to the ФЗК (3). In addition, the T2 signal is supplied to the FZK (3). FZK (3) produces signals BLKVV0-BLKVV3 arriving at the output of the UVP. From UVP signals BLKVV0-BLKVV3 arrive at their corresponding KVV0-KVV3. In addition, the FZK (3) generates the signals ZKP0-ZKP3 arriving at the FBL (4). In addition, from the input of the UVP to the FBL (4), the LSSF signal is received. From the FBL (4), the BLPRO signal is supplied to the output of the UVP. From the UVP output, the BLPRO signal is sent to the processor. In addition, at the input of the UVP from the processor receives the signal ZPRO. From the UVP input, this signal is fed to the FBL (4).

The principles of the device.

The control electronic computer (COMPUTER) includes several devices: a processor, four input-output channels (I / O) with direct access to (OP), and a software-temporary device (PVU) that synchronizes the processor and the HVS. If necessary, simultaneous access to the OP between devices there are conflict situations.

The formation of the MMC and the clock signals T1, T2 in the PMD does not depend on the need for the processor or HVB to contact the OP.

Signals MMC determine the duration of the computer cycle of the computer.

Signals T1 and T2 are formed with a shift of 0.25 μs.

Priority formation device (UFP) is designed to resolve conflict situations when accessing the real-time OB in the control computer.

The UFP establishes the sequence of access to the OP from the processor and the HVB during a simultaneous request.

HMI have the same priority in relation to each other and higher priority in relation to the processor.

The processor in this scheme has the lowest priority, because it processes the information received by the HVAC from external sensors, and generates information for issuance by means of the HVAC to the governing bodies of the system.

Interaction with external subscribers is performed at a strictly defined time of the computing process. Exchange with external subscribers is carried out by input-output channels, each of the four HVBs having their own set of subscribers. In this regard, it is difficult to prioritize the EHR among themselves if access to the OP is necessary.

UVP provides the formation of signals WE and CE, necessary to access the OP from only one of the devices.

The processor, when performing the operation associated with the appeal to the OP, generates a signal ZPRO - the input signal of the request for permission to work with the OP from the processor.

If there is no signal ЗКП0-ЗКП3 if there is a signal ZPRO, there are no input request signals for permission to work with the OP from КВВ0-КВВ3, then the processor, using the internal clock signals СП1-СП4, generates access signals to the OP (WE and CE).

If at the same time as a signal for the LATCH, there is a signal of an application for the OP of at least one HFB (ZKP0-ZKP3), then in the FBL block (4) a BLPRO signal is generated, which leads to the blocking of the internal clock signals of the processor (SP1-SP4) regarding access to the OP and he goes into STOP mode - suspends the execution of operations associated with the appeal to the OP. Signals WE and CE are not generated.

If the processor performs operations not related to access to the OP, then regardless of the presence or absence of signals ZKP0-ZKP3, program execution continues.

When resolving conflicts between the EHF, the UFP provides the following principle: each SEC can be guaranteed to contact the OP in its “own” cycle, depending on the number of the SEC.

To achieve this, the time between the marks of the machine cycle is divided into cycles of operation of HVB, with a duration of 0.5 μs, successively following each other.

Each cycle from 0 to 3 belongs to the KBB with the corresponding number. In this cycle, it is allowed to refer to the OP of the given KBB, if necessary.

In the block of the Federal Scientific Center (1), the signals NTs0-NTs3 are formed and are fed to the DShR block (2).

If it is necessary to contact the OP, each HVAC generates signals ЗП0-ЗП3, which also go to the ДСПР block (2).

In the block ДШПР (2) the signals РЗК0, РЗК1, РЗК2 and РЗК3 are generated - permission signals for working with the OP for КВВ0-КВВ3 depending on НЦ0-НЦ3 - cycle number “0-3” of access to the OP and on the presence or absence of ЗП0 signals -ZP3 - the input signal of the request for permission to work with the OP from KVV0-KVV3. The signal generation algorithm RZK0-RZK3 is presented in table 1.

Signals RZK0-RZK3 are fed to the FZK block (3) and depending on the presence or absence of signals ZP0-ZP3 in the FZK block (3) signals ZKP0-ZKP3 are formed - the signal of the request for the OP from KVV0-KVV3 and BLKVV0-BLKVV3 is the internal clock lock signals КВВ0-КВ3 (С1-С4) in terms of access to the OP in accordance with table 2.

The BLKVV0-BLKVV3 signals block the internal clock signals SK1-SK4 in the corresponding HFB, and stop the HFB for a time ≤1.5 μs in terms of access to the OP. Signals WE and CE are generated only in the HMI, which is allowed to access the OP.

Exchange with subscribers is not suspended, the exchange cycle is not violated.

If it is necessary to write or read more than one information word, the call to the OP of each HVC can occur with a break for the duration of the call of neighboring HVS. At the same time, each HFB is guaranteed to turn to the OP at least once every 2 μs.

The maximum number of information words that must be written or read from the OP during one exchange session with the OP is three. Therefore, the maximum time for which one session of access to the OP will be performed is 6 (0.5 * 3 * 4) μs.

The technical result is the creation of a device for the formation of priorities, the inclusion of which in the control machine will increase the speed of data processing while accessing the OP of several devices.

Thus, a priority forming device is declared, comprising a priority decoder (2), into which a channel request generator (3), a lock generator (4) and a cycle number generator (1), to which signals the input label of the machine cycle and the first clock signal, at the same time, the second clock signal is supplied to the channel imager; the signals of the cycle numbers "1", "2", "3" and "4" come from the shaper of the number of cycles to the priority decoder, and the first, second, third and fourth input signals generated by the corresponding input-output channels go to the priority decoder and channel claim generator, and the first, second, third and fourth permission signals from the priority decoder also arrive at the channel claim generator, and the channel first, second, third and fourth signal blocking signals arrive ue to the output device furthermore generator generates channel applications the first, second, third and fourth signal input to the application generator locks, which receives the signal processor and generates a request signal supplied to the CPU lock device yield.

Claims (1)

A priority generating device comprising a priority decoder, characterized in that a channel request generator, a lock generator and a cycle number generator are supplied, to which signals the input label of the machine cycle and the first clock signal are received, the second clock signal being transmitted to the channel request generator; the signals of the cycle numbers "1", "2", "3" and "4" come from the shaper of the number of cycles to the priority decoder, and the first, second, third and fourth input signals generated by the corresponding input-output channels go to the priority decoder and channel filler, and the first, second, third and fourth permission signals from the priority decoder also go to the channel filler, and the channel filler generates the first, second, third and fourth signal blocking signals, coming to the output of the device, in addition, the channel imager generates the first, second, third, and fourth order signals arriving at the blocking imager, which receives the processor request signal and generates a processor blocking signal that is output to the device.

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