JPS594733B2 - Kyoutsuba Seigiyo Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a common memory, etc. that is commonly used by multiple request sources such as processors or high-speed data transfer devices such as magnetic tape devices and magnetic disk devices via a single common bus. This relates to a control circuit that adjusts conflicting requests for access to the common resource from different request sources and determines the right to use the bus cycle, that is, the right to use the common resource.

Conventionally, one processor and one high-speed data transfer device used a common bus to use a common memory, but access to the common memory required one bus cycle each time the right to use the bus was requested. (this is equivalent to a memory cycle), or occupies most or all of the right to use memory cycles for a certain period of time, such as a direct memory access mechanism (hereinafter referred to as DMA), such as memory access from a magnetic disk device, etc. Bus control methods were often adopted that resulted in

In the case of the former method, time is required for each bus cycle to request the right to use the bus, determine the right to use the bus, and grant the right to use the bus, and the bus cycle time, that is, the effective common memory cycle time This has the disadvantage that it slows down the process, leading to a decrease in memory usage efficiency. In the case of the latter method mentioned above, which occupies the bus cycle for a certain period of time, the frequency of memory access is not that high, but memory access is guaranteed a certain number of times within a certain unit time, such as in a control unit that controls a communication line. This method has the drawback of being inappropriate if there are other bus cycle requestors that need to be processed. This invention improves memory usage efficiency by providing a bus occupancy bit in a bus control command that specifies the operation of a common bus that is issued from a request source when a bus occupancy request is accepted. A bus cycle occupancy counter is set up according to the
The present invention provides a bus control circuit that can guarantee the right to use the bus at a certain rate to other request sources within a certain unit time.

Further, in this invention, by using the bus occupancy bit, it is possible to make it impossible for other request sources to access the common memory during a certain period of bus cycle occupancy, and thus the state of a certain area of the common memory can be If the process is hindered if the request source is changed by another request source, it is possible to use the bus occupancy bit mentioned above to prohibit access from other request sources for a certain period of time, so that the process can be performed without the above problem. can. According to the present invention, in a bus control circuit that adjusts conflicts between a plurality of request signals requesting the right to use a bus, when a request source whose request has been accepted starts using the bus, the following bus command is included in the output bus command. A bus cycle occupancy bit is provided to indicate whether or not to request occupancy of a bus cycle, and when a request for occupancy of a bus cycle is detected from this bit, the right to use the bus cycle is continuously granted to the requestor. Means will be provided to provide this information.

Therefore, it is not necessary to determine which request source should be granted usage rights for each bus cycle, thereby increasing the efficiency of bus cycle usage. In addition, a bus cycle occupancy counter is provided in the bus control circuit to count the number of consecutive bus cycle uses, and when this exceeds a certain number of times, even if the bus cycle occupancy bit requests occupancy, all of the requests are For example, new request sources are accepted according to priority or on a first-come, first-served basis, thereby guaranteeing that the bus can be used a certain number of times within a unit time for other request sources as well. Next, an embodiment of the common bus control circuit according to the present invention will be described with reference to the drawings.

In FIG. 1, a processor group (Pl, P2, P3) 1 and a DMA adapter (P4) 2 that connects a high-speed data transfer device 3 such as a magnetic disk device to the bus are connected to a common bus 4. A common memory 7 is connected via a memory control unit 6. A bus control unit 5 performs control such as determining the right to use the common bus 4 for each request source of the processor group 1 and the device 3. Processor group Pl,
Each bus cycle request signal Rl, R2, R3, R4 output from P2, P3 and DMA adapter P4 is input to the bus control circuit 5. The requesting town receives request acceptance signals Al, A2, A3, A from the bus control circuit 5.
4 to each request source. The bus control circuit 5 is configured as shown in FIG. 2, for example. That is, the bus use request signals Rl, R2, R3, and R4 are sent to the bus use right determining circuit 11.
is input. In this embodiment, the bus right determining circuit 11
When these circuits are used as priority control circuits, R1 has the lowest priority, and R2, R3, and R4 have higher priorities in this order. The output of the priority control circuit 11 is set in the register 12. In this set control, when there is one or more bus cycle requests and the 0th bit of the bus command register (described later), that is, the bus cycle occupancy bit, is 10, the generated bus control clock is given to register 2 as the set signal 13. It is done by being given. Request signals Rl, R2, R3, R
4 is supplied to the AND circuit 15 through the 0R circuit 14,
The bus control clock and the negative output of the 0th bit of the command register 17 are also input to this circuit 15 from a terminal 16 . The output of the register 12 is outputted as bus use permission signals Al, A2, A3, and A4 to the requesting processor or DMA adapter to which the right to use the bus is granted. Only one of the signals Al, A2, A3, and A4 becomes 61° at a time. Bus use permission signal An (
The processor or DMA adapter that receives the signal, n being 1, 2, 3, or 4, outputs a memory address, write data in the case of writing, and a bus command to the common bus.

The bus command indicates the operation of the common memory and the common bus, and is set in the command register 17. This bus command consists of 4 bits, for example, as shown in Fig. 3, and the 0th bit indicates whether or not to occupy the next bus cycle. A command with the following content is given to memory control. Therefore, the first to third bits are sent as they are to the memory control section 6 (FIG. 1). Bus command register 17
When the 0th bit is 1F'', it indicates that the next bus cycle is requested continuously, and when it is ``O'', it indicates that there is no request for the next bus cycle.

The output of the 0th bit of the bus command register 17 is supplied to the gate 18, to which the cycle start timing is also given from the terminal 19. Therefore, the 0th bit above is "
When it is 1゛, terminal 19 is activated at the memory access start timing.
The bus cycle occupancy counter 20 counts the timing from . The output of the counter 20 is input to decoders 21 and 22, which decode the count values respectively, and the decoder 21 generates an output only when it decodes 2.
2 produces an output only when 4 is decoded. The use permission signals Al and A2 are logically summed in a circuit 23, and the output thereof and the output of the decoder 21 are supplied to an MΦ circuit 24.

The use permission signals A3 and A4 are logically summed in a circuit 25,
The output and the output of the decoder 22 are taken by an AND circuit 26, and the outputs of the AND circuits 24 and 26 are taken by an 0R circuit 28.
is supplied to In other words, in this embodiment, the bus usage right request R
For requests R3 and R4, the maximum number of consecutive bus cycles that can be occupied is set to two, and for requests R3 and R4, the maximum number of bus cycles that can be occupied is set to four. When permission to use the bus cycle is continuously output for the maximum number of times of bus cycle occupancy corresponding to each of the bus use permission signals Al, A2 or A3, A4, the output of the 0R circuit 28 becomes 61゛. As a result, the gate 29 opens, and the bus cycle end timing from the terminal 30 is determined by the gate 29.
The counter 20 is reset to 10'' and the command register 17 is also reset.
The bus control clock passes through the D circuit 15, and the output of the priority control circuit 11 is set in the register 12. That is, the granting of the right to use the bus is determined again, and a bus use permission signal is output to the request source. FIG. 4 shows a time chart showing the operation of each signal line and bus cycle occupancy counter in FIG. 2.

Bus permission signal Am for bus permission request signal Rm
When becomes ``1'', access to the bus from the request source Pm is started, and since the 0th bit of the bus command is 1'', the bus cycle occupancy counter 20 is updated to 1 at the memory cycle start timing.The request source Pm starts accessing the bus. If the maximum number of bus cycle occupancies given to the original Pm is 62, the bus cycle occupancy counter "2", that is, when the bus cycle is used twice, bus use is permitted at the end timing of the memory cycle at that time.Aml bus command register and sets the bus cycle occupancy counter to I.-Then, it receives the request signal Rn, which has the highest priority among the request signals other than the request signal Rm.The 0th bit of the bus command generated by this use permission signal An is 0'. Since the next bus cycle occupation is not requested, the counter 20 remains 0. Figure 5 shows the time of transition of bus cycle usage rights of bus cycle request sources Pl, P2, P3, and P4 such as processors or DMA adapters. The chart shows a chart.Since bus access requests are continuously output from the bus cycle request source P4, the bus cycle is consecutively allocated to the request source P4 for the maximum number of bus occupancies of four times.
This is a case where the right to use the bus cycle is transferred to another bus cycle request source Pl, P3, or P2 every four cycles. As shown in Figure 5, by using bus cycles to some extent consecutively, the total number of times T (this is equal to a bus cycle) required for transfer of bus usage rights is minimized, and memory usage efficiency is maximized. The right to use the bus is controlled so that even when a certain request source is in continuous use, the right to use the bus is granted at a certain rate to other request sources with lower priority. In addition, by providing a bit in the bus command that indicates whether or not to occupy the next bus cycle, for example, a processor can use the common bus continuously depending on its processing status, and as mentioned above, multiple When a certain area of a common memory is commonly used by two processors, it is possible to prevent necessary data from being erased by other processors.

Conventionally, one processor and one magnetic disk device, for example, were connected to a common bus, and it was predetermined for each device to use the processor one bus cycle at a time, and the magnetic disk device to use it continuously. In this invention, it is possible to use the device continuously as many times as necessary depending on the processing state, that is, depending on the demand at the time. However, by providing a bus cycle occupancy counter as described above, the number of consecutive uses can be limited. In the above embodiment, a priority control circuit is used as the bus usage right determination circuit 11 for a plurality of request signals, but other control circuits may be used, for example, an arrival order reception circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiprocessor device to which the present invention is applied, FIG. 2 is a block diagram showing an example of a common bus control circuit according to the present invention, and FIG. 3 is a diagram showing the bit configuration of a bus command. FIG. 4 is a time chart showing an example of the operation of the bus control circuit, and FIG. 5 is a time chart showing an example of bus cycle usage. 1, 2: Request source, 4: Common bus, 7: Common memory, 5:
Common bus control circuit, 11: Bus usage right determination circuit, 12:
Register, 15: AND circuit, 17: Bus command register.

Claims (1)

[Claims] 1. A plurality of request sources are connected to a common memory through a common bus and are connected to a multiprocessor system that uses the common bus in a time-sharing manner according to the bus cycle, and the plurality of request sources that have sent the common bus use request signal In a common bus control circuit that grants the right to use the common bus to one of the request sources, the bus cycle occupancy bit added to the bus command sent by the request source to which the right to use the common bus has been given is the next one. means for continuously granting the right to use the common bus even in the next bus cycle of the request source that sent the bus command when indicating a bus cycle occupancy request, and the number of consecutive grants of the right to use the common bus; 1. A common bus control circuit, wherein the common bus control circuit is configured to accept use request signals for the common bus from the plurality of request sources when the number of requests reaches a predetermined number.