JPS5953923A - Data processing system - Google Patents

Abstract

PURPOSE:To provide a specified bus access time irrespective of whether the priority order is high or low, and also to reduce the number of signal lines, by providing two bus use request signal lines having the priority order, and two bus use approval signal lines corresponding to said signal lines. CONSTITUTION:For instance, a data processing device 6 generates a bus use request. The bus use request is sent out simultaneously to but request signal lines RQX1, TQY1, and the RQX1 and the RQY1 are sent to a bus control device 1 and a bus control device 2, respectively. The devices 1, 2 send out a signal to bus use approval signal lines GRX1, GRY1 corresponding to the RQX1 and the RQY1, unless there are bus use requests (namely, RQX0, RQY0) of a higher tank than the RQX1 and the RQY1. As for devices which can receive the bus use approval signal from the devices 1, 2, among devices 1-16, no device except the device 6 exists, in this case. In case when the priority order is decided in this way, and the devices 1, 2 send out only one approval signal, as for the device which can receive two approval signals, only one is determined, and the device which obtains the right of using is determined to only one device.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] Thus, it relates to connected data processing systems.

[Prior art]

In a data processing system that has a bus configuration, bus usage requests are selected from "D number of devices assigned to the bus" and the right to use the bus is granted to the only device on the bus. Conventionally, two bus right-to-use determination mechanisms have been used for this purpose.One is called the deci-chain method, and the other is for individual requests and nested requests. This is called the dokwarisho method.

FIG. 1 shows a schematic block diagram of the deci-chain system. In Figure 1, 1 is bus control device 1, 2.3 to N
A data processing device 7.20 is a signal line for transmitting a bus use request to a bus control device, and 21, 22.23 is a communication path for transmitting a bus use permission signal, forming a so-called decimal chain. 13, 14, 15 are AND games), [1, 11,
Reference numeral 12 denotes a slip-flop (hereinafter referred to simply as F/F) which holds the bus use request of each device, and it is assumed that the intervening device P3 generates the bus use request signal.

The bus use request signal is transmitted to the bus control device 1 via the driver 17 and the bus signal line 20, and the bus control device 1 sends a bus use permission signal to the signal line 21.

In the device 2, the bus use permission signal is ANDed with the bus use request of the device 2 at a gate 13. #°-1° [Since none of the devices 2 has issued a bus use request, the bus use permission signal is passed through the AND gate 13 and transmitted to the device 3 via the signal line 22. Since the device 3 is generating a bus use request, the inverted output (Q) of the F/F 11 has a logic value of 1ON, and the bus use permission signal is output from the AND gate 14.
It is not transmitted from device 3 onwards.

The device itself issues a request to use the bus, and the device that receives the bus use permission signal obtains the right to use the bus.

Therefore, the closer the bus control device is to the bus control device, the higher the degree to which it responds to bus usage requests.

This deci-chain method has been widely used since it requires a small amount of hardware and has a simple configuration. Devices that are further away from the bus, that is, devices with lower priority, require more time from issuing a bus use request to receiving a bus use permission signal (hereinafter this time is referred to as bus access time). There was a drawback that it took a while.

For example, the delay time of the first stage υ of 13, 14, and 15 (for example, the AND game in Figure 1) is about 1 Ons in the case of a TTL element. From when the usage permission signal is sent until the lowest device receives the bus usage permission signal 19X 10=1
It will cost 90n8.

In addition, the bus permission signal is gated with each device's bus use request and connected in a chain across all devices, so if an empty slot is created, this decimal chain will eventually be cut. , it was not possible to create empty slots between devices.

On the other hand, a schematic block diagram of the single request single allocation method is shown in FIG. In Fig. 2, 1 is a bus control device, 2, 3,
4. N is a data processing device, 30, 31, 32, and 33 are bus use request signal lines, and 35, 36, 37, and 38 are bus use permission/repair No. 1d.

This method is different from the above-mentioned deci-chain method.
Each device on the bus individually sends a unique bus request signal to the bus control device, and the bus control device prioritizes each bus use request signal according to a predetermined priority order, and A bus use permission signal is individually sent to the device to which the bus is allocated.

In this method, the bus access time is determined only by the delay required for determining the priority of the bus controller itself.
, both high and low priority devices are fixed, and the drawback of the above-described decimal contention chain system in which devices with low priority for bus usage rights are particularly slow is eliminated. However, bus use request signal lines and bus use allocation permission signal lines are required for the number of devices, and as the number of devices connected to the bus increases, a large number of signal lines are required for the bus use right determination mechanism. The above-mentioned deci-chain method requires only two wires, the bus request signal line and the deci-chain, regardless of the number of devices, whereas the single-request, single-assignment method requires only two bus use request signal lines and the deci-chain, regardless of the number of devices. If there are 10 devices, the number of signal lines required for the decision mechanism is 20 in total (10 each for requests and permissions), and 40 in total for 20 devices.There was a disadvantage in terms of implementation structure. .

[Purpose of the invention]

The purpose of the present invention is to provide a constant bus access time regardless of whether the priority is high or low, and to reduce the number of signal lines for the bus usage right determination mechanism compared to the single request single allocation method.
Another object of the present invention is to provide a data processing system that eliminates the drawbacks of the deci-chain system, such as the impossibility of providing empty slots and the fact that priorities are fixed depending on the mounting position of the bus.

[Structure of the invention]

According to the present invention, in a data processing system consisting of a plurality of data processing devices and a bus control device connected by a common bus, each data processing device transmits a plurality of bus use request signals that adjust priorities. It has two bus use permission signal lines for transmitting one bus use request signal line and a plurality of bus use permission signals corresponding to the priority order, and when the data processing device requests the use of the bus, , a bus use request signal is sent to each of the two bus use request signal lines, and the bus control device selects the highest priority bus use request from the requested bus use request signal line. A bus use permission signal is sent to two bus use permission signal lines, one each corresponding to the signal line, and the data processing device that generated the bus use request does not use the bus from either of the two bus use permission signal lines. A data processing system is obtained in which the data processing device that receives the permission signal obtains the right to use the bus.

[Question about the example]

Next, regarding the present invention, I will refer to the drawings and see if there is an h5 in the field. , reveal. FIG. 3 is a principle block diagram showing the basic idea of the present invention. In Figure 3, 1°2 is the bus control device, ■~0 is the data processing device, RQX Q~RQX3
．． RQYO to RQY3 are bus transmission signals with priority, CJrRXQ-GRX3, GRlY
Q~GRY3 is 几QXO, RQX3, :L is also QYo
~I is also a bus license line corresponding to QY3, and its priorities are RQ, X□, and RQX1.

RQX2. RQX3. RQYO, RQYl, RQY2
, RQY3. The arrows in the figure indicate the direction of the signal.

Assume that the device (3) in FIG. 3 issues a bus use request. Bus use requests are sent to RQX 1 and RQY l at the same time, R and QXI are sent to bus control device 1, and R and QYI are sent to
is sent to the bus controller 2. Bus control device 1゜2 is R
Requests to use the bus higher than QX 1 and RQY 1 (
That is, unless RQXo, RQYo), R
QXl.

Bus use permission signal line GR/Xi corresponding to RQYl.

Among the devices 6 and 6 that send signals to GR and Yl, there is no device other than device ■ that can receive the bus use t'f enable signal from the two bus control devices w1 and 2. I want to. In this way, the priorities of the plurality of bus use request signals are determined 7, and the bus control devices 1, 27 . >Other than sending only the 2 IF bus use permission signal, only one device can receive the 2 & l bus use permission signal, and the only device in the system that can obtain the right to use the bus. It is determined only for the number of devices 7. .

@Figure 4 shows a block diagram of an embodiment of the bus restriction 1 device in Figure 3.6 In Figure 4, RQXQ~R,QY
3. GRXQ to GRY3 are the aforementioned bus use request signal lines and bus use permission signal lines.

Bus use request signal line RQXQ to RQX 3 receivers 41
．． It is received by the bus controller at 42, 43, and 44.

RQXO~几Q, X3 is now % Low Level'
If it is significant, receivers 41, 42, 43.4
4 has an inverter function, the output of the L/sceiver becomes significant at 'High Level'. L/C
Ha41.42.43.

The bus use request signal received at 44 is the D type F/F.
45, 46, 47. 48 while NOR gate 5
Guided by 7. When a bus request signal is received, NO
The output of the R gate 57 is at Low Level.
F/F 45.46 from amplifier 21 after passing through inverter 58, AND gate 59, and delay line 60.

The clock signal becomes 47.48. The output signal of the amplifier 61 is further transmitted from the amplifier 63 to the F/F 49 through a delay m62.
, 50, 51.52 clock signals.

The reason why two stages of F/Fs are provided in the cascade L is to synchronize the asynchronously generated bus use request signals RQXQ and RQX3. 53, 54, 55, and 56 are AND gates that determine the priority order. In FIG. 4, as explained earlier, the AND gates 53, 54, 55, 56
is assembled, and only one bus use permission signal among GRXQ and GRX3 is output in accordance with the priority order of the requested signals.

Next, the bus access time described above will be compared between the method according to the present invention and the prior art deci-chain method. FIG. 5 shows an example of a deci-chain type bus control device used for comparison. In FIG. 5, RQ is a bus usage request signal line, and GR is a bus usage permission signal line. 71 is a receiver, 72 is an AND gate, 73 is a delay line, 74 is an amplifier, 75 is a D type F/)゛, 76
is an amplifier. Here, in the bus control device according to the present invention shown in FIG.
After receiving the bus use permission signal (XQ~R, QX3)
Let's compare the time it takes to send GR or GRXQ to GR, X3). If the circuits in Figures 4 and 5 are constructed with TTL elements, the receiver delay (41, 42, 43, 44 in Figure 4,
Figure 5 (7) 71): 1Q
ns・AND gate delay (59 and 53°5 in Figure 4)
4.55, 56, Figure 5 072): 9nS・F
/F delay (45.46, 47, 48, 49°50.51, 52 in Figure 4, (7) 75 in Figure 5): 11
nS, 'NOR gate delay (57 in Figure 4): 9ns
- Amplifier delay (61.63 in Figure 4, 74. in Figure 5)
76): 9n8・Delay line delay (60 in Figure 4. 73 in Figure 5): 20n
S ・Delay line delay (62 in Figure 4): 50n
S-inverter delay (58 in Figure 4): 7n
8, the delay of the conventional deci-chain type bus control device (FIG. 5) is 68 nS, and the delay of the bus control device according to the present invention (FIG. 4) is 143 n8.

Since the bus control device of the present invention synchronizes a plurality of bus use request signals, the delay of the bus control device itself is inferior to that of the conventional deci-chain method. However, the time from when each device generates a bus use request signal until it receives a bus use permission signal is longer than the conventional deci-chain method (see Figures 1 and 5).
Figure) is [bus control device delay] 10(N-1)X10
n8 (1), in the present invention it is given by 1; [bus control device delay]+9n8 (2).

In equation (1), the AND that constitutes the decimal chain
The delay of the gate (13.14.15 in Figure 1) is 10n.
s, and N is the number of devices. Also, in equation (2), 2
The numerical value 9n8 in the item is the delay of the AND gate because each device takes the AND of GRXQ to GRX3 and GRYQ to GRY3 in order to obtain the bus use permission signal. (This is the AND gate 88 in FIG. 7, as described later.

) Figure 6 shows the results of a comparison of 16 devices. As shown in FIG. 6, the system according to the present invention is superior to the conventional deci-chain system when the number of devices is 10.
Access time is reduced.

Note that the bus control device of the single request single assignment method is one of the aspects of the present invention.
Since the bus control device shown in FIG. 4, which is an embodiment, only has the circuits for the bus use request signal and the bus use W signal increased by the number of devices, the bus control device of the single request single assignment method can be used.
The access time is the same as the time in the present invention.

As shown in FIG. 6, the bus access time of the present invention is disadvantageous for devices with high priority compared to the prior art deci-chain system. However, in a data processing system, devices with high bus usage priority are usually file-based devices, and although these devices have high transfer speeds, it is usually a pull-to-pull transfer, and it is difficult to decide whether to use the bus or not. is determined in advance at an early time, and it is relatively easy to make the time from generating the bus use request signal to receiving the bus use permission signal overlap with other processing. On the other hand, the CPU (Central Processing Unit W) etc.
In the priority order of normal bus use requests, it is normally placed at the bottom. However, whether or not the CPU needs to transfer data to other devices via the bus depends on the type of instruction executed by the CPU. It is generally difficult to predict in advance and generate a bus use request. Therefore, the time from generation of a bus use request to reception of a bus use permission signal directly affects the CPU's arithmetic processing capacity. For example, when reading data from memory, it is added to the memory access time like (memory access time) + (path e access time), and the memory access time becomes longer. has the same effect as In these various cases, it is clear that the present invention is effective in that the time from when the CPU issues a bus use request to when it receives the bus use permission signal is short, with the exception of priorities.

Next, when comparing the number of signal lines required for the bus usage right determination mechanism for 16 devices as in the embodiment, the conventional deci-chain system has a total of 2 signal lines for the bus request signal and the deci-chain; The single request single allocation method has a total of 32 requests and grants, and in the present invention, requests (RQXO to RQX3,
gQy□~RQY3), permission (GRXQ -, -GRX
3, GRYQ to GRY3), for a total of 16 lines, and the number of signal lines is halved while taking advantage of the advantages of the single-request, single-allocation system.

FIG. 7 is a diagram illustrating the mounting interface of each device to the back board according to the present invention. In Figure 7, 81 is the connector on the back board of the device, 82.8
3, 84.85 is a DIP switch, 86.87 is a driver that outputs a bus use request signal (REQUEST) to the bus, and 88 is a driver that receives two sets of bus use permission signals and indicates that the right to use the bus has been obtained. This is an AND gate that generates a notification signal (GRAN T ). By appropriately setting the DIP switches, this device can be configured to have any priority in any slot on the back board.

〔Effect of the invention〕

As explained above, in the present invention, by providing two bus use request signal lines with priorities and two bus use permission signal lines corresponding to the number, priority of bus use rights can be obtained. The bus access time does not increase even for low-level devices, and with an appropriate number of signal lines, the mounting location can be freely selected.Also, since the priority 1p circuit does not form a chain, empty slots are also free. This has the effect that it can be set to .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of a priority determination mechanism of a conventional deci-chain system, FIG. 4 is a block diagram showing an embodiment of the bus control device in FIG. 3, and FIG. 5 is a block diagram of an example of a conventional deci-chain type bus control device. , FIG. 6 is a diagram showing a comparison of the bus access time between the conventional deci-chain method and the present invention, and FIG. 7 is a diagram showing the mounting interface between the data processing device and the back board in the present invention. FIG. 1... Bus control device, 2, 3. N...
Data processing device, 10, 11.12... Clip 70 knob, 13° 14.15... AND gate, 16, 17.18... Driver, 20...
...Bus use request signal line, 21, 22゜23...
... Decy chain signal, 30, 31, 32°3
3...Bus use request signal line, 35, 36, 37
．． 38... Bus use permission signal line, ■~@...
...Data processing device, RQXo, RQXI,
RQX2, RQX3...Bus use request signal line, 41, 42.43.44...Receiver, 4
5.46, 47.48--D, lp F/F, 4
9,50゜51.52...D type P/F, 5
3, 54, 55. 56...AND gate, 5
7...NOR gate 58...Inverter, 59...AND gate, 6o...
Delay line, 61... Amplifier, 62 Old... Delay line, 63... Amplifier, 71... Receiver, 72 Old... AND gate, 73... ...Delay line, 74...Amplifier, 75...D type F/F', 75...Amplifier, RQ...
Bus use request signal, G⇠...bus use permission signal, 81...back board Φ connector, 82,
83°84.85...DIP switch f, 86.
87...Bass fist driver, 88...A
ND gate, REQUEST... bus use request signal within the device, GRANT... bus use permission signal within the device.

Claims (1)

[Claims] In a data processing system consisting of multiple data processing devices and bus control devices connected to a common bus,
Each data processing device has two bus use request signal lines for transmitting a plurality of bus use request signals having priorities, and two bus use permission signal lines for transmitting a plurality of bus use permission signals corresponding to the priorities. and when the data processing device requests the use of the bus, it sends a bus use request signal to each of the two bus use request signal lines, and the bus control device responds to the request. Each one corresponds to the bus use request signal line with the highest priority from the first bus use request signal line.
Two bus use permissions in total (the data processing device that sends the bus use permission signal to the fi line and generates the bus use request is
A data processing system characterized in that a data processing device that receives a bus permission signal from any of the bus permission signal lines obtains the right to use the bus.