JPH07129503A - Arbiters - Google Patents

Abstract

PURPOSE:To easily perform a change even if the number of circuit for which an arbitration is required is increased and decreased and to easily perform the change of a priority, in arbiters. CONSTITUTION:In the arbiter circuit 22, a cycle pulse generator 22a responds to an operation request signal and generates a cycle pulse signal. When an AND circuit 22b does not receive the inhibition signal from the arbiter 21 when the circuit receives the cycle pulse signal, the circuit generates a valid pulse signal. When an inhibition signal generation circuit 22c receives the valid pulse signal, the circuit transmits the inhibition signal to the arbiter 23. When a waiting time adjustment circuit 22d receives the valid pulse signal, the circuit transmits an operation permission to a memory control circuit 22e after preliminarily fixed time. When the memory control circuit 22e terminates the operation, the circuit transmits a termination signal and stops the transmission of the inhibition signal from the inhibition signal generation circuit 22c. The arbiters 21 and 23 are composed in the same way as the arbiter 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration device for arbitrating priority or the like for a plurality of requests, and more particularly to an arbitration device used in a digital communication device.

[0002]

2. Description of the Related Art Generally, as an arbitration device of this type, an arbitration circuit for avoiding a collision or the like on a CPU bus is known (for example, Japanese Patent Laid-Open No. 67667). In such an arbitration device, priority determination and arbitration determination are performed according to the arbitration request signal, and the arbitration device permits an operation (for example, access) based on the determination result.

Here, an outline of a conventional arbitration device will be described with reference to FIG.

The arbitration circuit 11 includes a plurality of arbitration request circuits 12.
To 14 are connected, and memory control circuits 15 to 17 are connected to the arbitration request circuits 12 to 14, respectively. Further, each of the arbitration request circuits 12 to 14 receives an operation request signal 101 from an external device (hereinafter referred to as an output source).
Through 103 are given.

Now, when the operation request signals 101 to 103 are applied to the arbitration request circuits 12 to 14, respectively, the arbitration request circuits 12 to 14 respectively receive the arbitration request signal 104.
Through 106 are sent to the arbitration circuit 11. Then, the arbitration circuit 11 performs priority determination and arbitration determination of each request based on these arbitration request signals 104 to 106, and based on the determination result, the arbitration circuit 11 sends the arbitration request circuits 12 to 14 permission signals 107 to 107, respectively. 109 is transmitted.
The arbitration request circuits 12 to 14 enable signals 107 to 10
In response to 9, the enable signals 110 to 112 are provided to the memory control circuits 15 to 17. As a result, the memory control circuits 15 to 17 become operable. The memory control circuits 15 to 17 give the end signals 113 to 115 to the output sources after the operation is completed.

[0006]

In the above-described arbitration device, the operation request signal is converted into the arbitration request signal by the arbitration request circuit, the arbitration request signal is given to the arbitration circuit, and the priority determination and the arbitration determination are performed in the arbitration circuit. Then, when it is operable, a permission signal is generated to give permission to the arbitration request circuit. Therefore, it is necessary to combine as many arbitration request signals and permission signals as there are circuits that require arbitration. In other words, when the number of circuits that require arbitration increases or decreases, the configuration and scale of the arbitration device must be changed each time, and such changes are generally extremely difficult.

In addition, there is a problem in that when an operation request frequently occurs in a circuit having a high priority, a permission is not assigned to the circuit having a low priority.

It is an object of the present invention to provide an arbitration device whose structure and scale can be easily changed.

Another object of the present invention is to provide an arbitration device whose priority order can be easily changed.

[0010]

According to the present invention, in an arbitration device including a plurality of arbitration circuits and priorities are set in the arbitration circuits, an operation request signal is sent to each of the plurality of arbitration circuits. And a prohibition signal transmission means for transmitting an operation permission signal to the arbitration circuit of lower priority when the operation request signal is received. An arbitration device characterized by

[0011]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, the illustrated arbitration device includes a plurality of arbitration circuits 21 to 23 corresponding to a request source.
Then, operation request signals 211 to 231 are supplied from the request sources to the arbitration circuits 21 to 23, respectively.

The arbitration circuit 21 is a cycle pulse generator 21.
a, an AND circuit 21b, a prohibition signal generation circuit 21c, a waiting time adjustment circuit 21d, and a memory control circuit 21e. Similarly, the arbitration circuits 22 and 23 include the cycle pulse generators 22a and 23a and the AND circuit 22b, respectively.
And 23b, prohibition signal generation circuits 22c and 23c, waiting time adjustment circuits 22d and 23d, and memory control circuit 2
2e and 23e. Then, the clock signal 120 is applied to the cycle pulse generators 21a to 23a, the inhibition signal generation circuits 21c to 23c, and the waiting time adjustment circuits 21d to 23d, respectively.

In the arbitration circuit 21, the operation request signal 211 is given to the cycle pulse generation circuit 21a from the request source, whereby the cycle pulse generation circuit 21a has the cycle pulse signal having the preset first operation cycle interval. 212 is transmitted. H in AND circuit 21b
(High) level is given, and as a result, AN
In response to the cycle pulse signal 212, the D circuit 21b supplies the effective pulse signal 213 to the inhibition signal generation circuit 21c and the waiting time adjustment circuit 21d. Prohibition signal generation circuit 21
In c, when the effective pulse signal 213 is received, the inhibition signal 214
Is sent to the arbitration circuits 22 and 23. On the other hand, when the waiting time adjusting circuit 21d receives the effective pulse signal 213, the operation enable signal 215 after the preset first waiting time has elapsed.
To the memory control circuit (operating circuit) 21e. The memory control circuit 21e starts a predetermined operation by the operation enable signal 215, and sends an end signal 216 to the request source / prohibition signal generation circuit 21c after the operation is completed. In response to the end signal 216, the prohibition signal generation circuit 21c causes the prohibition signal 214
Stop sending.

In the arbitration circuit 22, the cycle pulse generating circuit 22a is supplied with an operation request signal 221 from a request source, whereby the cycle pulse generating circuit 22a has a cycle pulse signal having a preset second operation cycle interval. 222 is transmitted. The AND circuit 22b is connected to the output of the inhibition signal generation circuit 21c, and unless the AND circuit 22b receives the inhibition signal 214, the AND circuit 22b outputs the valid pulse signal 223 according to the cycle pulse signal 222 to the inhibition signal generation circuit 22c and the waiting time adjustment. It is given to the circuit 22d.
When the prohibition signal generation circuit 22c receives the valid pulse signal 223, the prohibition signal 224 is sent to the arbitration circuit 23. On the other hand, in the waiting time adjustment circuit 22d, the effective pulse signal 223
In response to this, an operation enable signal 225 is provided to the memory control circuit (operation circuit) 22e after the elapse of the preset second waiting time. The memory control circuit 22e starts a predetermined operation according to the operation enable signal, and sends an end signal 226 to the request source and prohibition signal generation circuit 22c after the operation is completed. In response to the end signal 226, the prohibition signal generation circuit 22c stops the transmission of the prohibition signal 224.

In the arbitration circuit 23, the operation request signal 231 is given from the request source to the cycle pulse generation circuit 23a, whereby the cycle pulse generation circuit 23a has a preset cycle pulse signal having a third operation cycle interval. 232 is transmitted. The AND circuit 23b is connected to the outputs of the prohibition signal generating circuits 21c and 22c,
When the AND circuit 23b does not receive the prohibition signals 214 and 224, the effective pulse signal 233 is given to the prohibition signal generation circuit 23c and the waiting time adjustment circuit 23d in accordance with the cycle pulse signal 232. When the inhibition signal generation circuit 23c receives the effective pulse signal 233, it transmits the inhibition signal 234 (in this embodiment, the inhibition signal 234 is not used in particular). On the other hand, when the waiting time adjusting circuit 23d receives the valid pulse signal 233, the waiting time adjusting circuit 23d outputs an operation enable signal 235 after the preset third waiting time, to the memory control circuit (operating circuit).
23e. The memory control circuit 23e starts a predetermined operation according to the operation enable signal, and outputs the end signal 2 after the operation is completed.
36 is sent to the request source / prohibition signal generation circuit 23c.
In response to the end signal 236, the prohibition signal generation circuit 23c stops the transmission of the prohibition signal 224.

As described above, in the arbitration circuit 23, the effective pulse 23 is determined based on the presence or absence of the inhibit signals 214 and 224.
3 is determined, and the arbitration circuit 22 determines the transmission of the effective pulse 223 based on the presence or absence of the inhibition signal 214. That is, in the embodiment shown in FIG. 1, the priorities are set in the order of the arbitration circuits 21 to 23.

Further, in order to prevent the collision of requests and the inability to allocate the requests to the arbitration circuit having a low priority, the first to third operation cycle intervals and the waiting time adjusting circuits in the cycle pulse generating circuits 21a to 23a. 21d
The settings of the first to the third waiting times in 23 to 23d are adjusted. That is, as described above, the priority order is the arbitration circuit 2
When the order is 1 to 23, the first to third operation cycle intervals and the first to third waiting times are set as follows.

(1) Third operation cycle interval> (operation time of memory control circuit 23e + third wait time) (2) Second wait time> third operation cycle interval (3) Second operation Cycle interval> (operation time of memory control circuit 22e + second waiting time) (4) First wait time> second operation cycle interval (5) First operation cycle interval> (operation of memory control circuit 21e Time + first waiting time) As described above, in the present embodiment, the arbitration circuit is provided for each request source, that is, the arbitration circuit is provided for each request source (that is, the distributed arbitration device is not used as the conventional arbitration device). As an arbitration device), prioritizing each arbitration circuit and sending an inhibit signal to a lower arbitration circuit when a certain arbitration circuit is operating, so it is easy to make changes when the number of circuits increases or decreases. Can be done. Furthermore, the priority can be set by setting the first to third operation cycle intervals and the first to third waiting times as described above, that is, the first to third operation cycle intervals. It is possible to easily change the priority order by changing the first to third waiting times (note that the priority order is changed by providing a selector and selectively outputting the prohibition signal from the selector). May be done).

Although the arbitration device having three arbitration circuits has been described in the above embodiment, an arbitration device having N arbitration circuits (N is an integer of 2 or more) can be similarly configured. Therefore, the description is omitted here.

[0021]

As described above, according to the present invention, each arbitration circuit is prioritized as a distributed arbitration device, and when a certain arbitration circuit is operating, an inhibit signal is sent to a lower arbitration circuit. Thus, there is an effect that not only can the change due to the increase or decrease of the circuit requiring arbitration be easily performed, but also the priority order can be easily changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arbitration device according to the present invention.

FIG. 2 is a block diagram showing a conventional arbitration device.

[Explanation of symbols]

 11 Arbitration circuit 12-14 Arbitration request circuit 15-17 Memory control circuit 21-23 Arbitration circuit 21a-23a Cycle pulse generator 21b-23b AND circuit 21c-23c Inhibition signal generation circuit 21d-23d Waiting adjustment circuit 21e-23e Memory Control circuit

Claims (4)

[Claims] 1. An arbitration device comprising a plurality of arbitration circuits, wherein the arbitration circuits have respective priorities set, and a control means for sending an operation permission to each of the plurality of arbitration circuits according to an operation request signal. An arbitration device comprising: a prohibition signal transmitting means for transmitting a prohibition signal for prohibiting the operation permission to the arbitration circuit having a lower priority when the operation request signal is received. 2. The arbitration apparatus according to claim 1, wherein the control means generates first pulse signals having a predetermined operation cycle interval in response to the operation request signal. Second means for generating a second pulse signal when the inhibition signal is not received when the first pulse signal is received, and after a predetermined time according to the second pulse signal, An arbitration device comprising: a third means for transmitting an operation permission, wherein the prohibition signal generating means transmits the prohibition signal when receiving the second pulse signal. 3. The arbitration device according to claim 2, wherein when the operation based on the operation permission ends, the prohibition signal generation means stops the transmission of the prohibition signal. . 4. The arbitration device according to claim 2, wherein the plurality of arbitration circuits are defined as first to Nth (N is an integer of 2 or more) arbitration circuits, and the predetermined operation cycle interval is set. Are defined as first to Nth operation cycle intervals in the first to Nth arbitration circuits, respectively, and the predetermined time is the first to Nth operation cycles in the first to Nth arbitration circuits, respectively. Of the first to Nth operation cycle intervals and the first operation period.
An arbitration device characterized in that the priorities are determined based on the Nth time.