CN1112260A - Arbitrator device capable of readily modifying the structure - Google Patents
Arbitrator device capable of readily modifying the structure Download PDFInfo
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- CN1112260A CN1112260A CN 94113781 CN94113781A CN1112260A CN 1112260 A CN1112260 A CN 1112260A CN 94113781 CN94113781 CN 94113781 CN 94113781 A CN94113781 A CN 94113781A CN 1112260 A CN1112260 A CN 1112260A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
Abstract
A decision device has a first to Kth decision circuit, which are respectively connected to a first to Kth request source, K representing a positive integer which is greater than one. Each of the first to Kth request sources is in communication with an external device. The decision device decides between the first to Kth request source with regard to the use of the external device in response to the first to Kth request signal. A kth of the first to kth decision circuits has a generation region, which responds to a kth request signal, for generating a kth enable signal to permit a kth request source to enter into communication with the external device if the kth decision circuit accepts the kth request signal, k representing a variable between 1 and K. A supply region supplies a kth inhibit signal to a (k+1)th to Kth decision circuit in order to terminate the generation of a (k+1)th to Kth enable signal if the kth decision circuit accepts the kth request signal.
Description
The present invention relates to a kind of arbitration device, be used for when request source is communicated by letter with peripherals, the use of this peripherals being arbitrated at a plurality of request sources.
Usually, well-known: computer system contains a plurality of by the interconnective processor of system bus.Communication aspects between these processors then is the common using system bus of processor.Therefore, computer system contains a moderator and is used for the use of these processor system buss is arbitrated.Japanese unexamined communique (Japanese Unexamined Publication) Tokkai Syo 64-67667(67667/1989) a kind of traditional moderator is disclosed.
This moderator can be used on and comprises from the communication system of first to k request source and a peripherals, and k represents the positive integer greater than 1 here.About with the communicating by letter of this external unit, first to k request source provides first to k request signal to obtain the right to use of this external unit for this moderator.This first to k request signal has first to k priority that differs from one another.
This moderator gives one in this first to k request source to give the right to use according to this first to k priority.
In this moderator, when positive integer k increases or reduces, be essential to its structure adjustment.Yet when this moderator was given the right to use according to first to k priority to one in first to k request source, it was difficult adjusting its structure.
In addition, suppose that first priority is limit priority.When first request source offered moderator with first request signal continually, it was difficult that second to k request source will obtain the right to use.
Therefore an object of the present invention is to provide a kind of arbitration device that its structure is adjusted of being easy to.
Another object of the present invention provides a kind of arbitration device that can be easy to change priority.
Other purpose of the present invention will become clearer along with following explanation.
For describing main points of the present invention, be understood that arbitration device is that each all links to each other with first to k request source of external device communication with it, k represents the positive integer greater than 1 here.This first to k request source provides first to k request signal to moderator respectively.When first to k request source and external device communication, moderator is used for responding first to k request signal and in first to k request source the use of external unit is arbitrated.According to the present invention, this moderator comprises first to k the arbitration circuit that links to each other with first to k request source respectively.K arbitration circuit in first to k arbitration circuit comprises the generation device that responds k request signal, being used for producing when k arbitration circuit receives k request signal k allows signal to make k request source energy and external device communication, here k represents the variable between 1 to k, also contain feeding mechanism be used for when k arbitration circuit receives k request signal, providing k inhibit signal to (k+1) to k arbitration circuit to stop (k+1) to k generation that allows signal.
Fig. 1 is the block scheme of conventional arbitration device;
Fig. 2 is the block scheme according to the arbitration device of a most preferred embodiment of the present invention;
Fig. 3 has been to use the block scheme at the communicator of the moderator shown in Fig. 2;
With reference to Fig. 1, at first traditional moderator is described for understanding the present invention better.Moderator 10 comprise arbitration circuit 11, the first to k requests for arbitration circuit 12-1 to 12-k, and first to k control circuit 13-1 be to 13-k, k representative here is greater than 1 positive integer.In illustrated embodiment, this positive integer equals 3.
Each in the 12-3 of first to the 3rd requests for arbitration circuit 12-1 all links to each other with arbitration circuit 11.First to the 3rd requests for arbitration circuit 12-1 also links to each other to 14-3 with first to the 3rd request source 14-1 respectively to 12-3, and they each can for example be data link.Each all can be used as the interface circuit operation to first to the 3rd requests for arbitration circuit 12-1 to 12-3.
First to the 3rd control circuit 13-1 links to each other to 12-3 with first to the 3rd requests for arbitration circuit 12-1 respectively to 13-3.First to the 3rd control circuit 13-1 links to each other to 14-3 with first to the 3rd request source 14-1 respectively to 13-3.In addition, each all can link to each other to the 14-3 external unit (not shown) of communicating by letter with first to the 3rd request source 14-1 with it first to the 3rd control circuit 13-1 in the 13-3.This external unit may be a storer for example.Externally equipment is under the situation of storer, notice that first to the 3rd request source 14-1 each in the 14-3 all leads to the inlet of this storer.
About with the writing to each other of external unit, first to the 3rd request source 14-1 provides first to the 3rd request signal to obtain the right to use of this external unit for moderator 10 to 14-3.This first to the 3rd request signal has first to the 3rd priority that differs from one another.
Hypothesis first priority is the priority of the first estate now.Second priority is second level priority.The 3rd priority is the priority of the tertiary gradient.In addition, suppose that first to the 3rd request source 14-1 is to 14-3 communicating by letter at the request of identical time and this external unit.As mentioned above, first to the 3rd request source 14-1 provides first to the 3rd request signal for respectively moderator 10 to 14-3.
This first to the 3rd request signal is received to 12-3 by first to the 3rd requests for arbitration circuit 12-1 respectively.First to the 3rd requests for arbitration circuit 12-1 that has been provided first to the 3rd request signal produces first to the 3rd arbitration request signal respectively to 12-3.This first to the 3rd arbitration request signal has first to the 3rd priority respectively.
Be supplied to the use of the arbitration circuit 11 decision external units of first to the 3rd arbitration request signal.More particularly, this arbitration circuit 11 is known: this first to the 3rd priority represents first respectively to the tertiary gradient.In addition, this arbitration circuit 11 is known: first to the 3rd request source 14-1 has first to the 3rd priority respectively to 14-3.Therefore, this arbitration circuit 11 determines the right to use of giving this peripherals to the first request source 14-1 according to first to the 3rd arbitration request signal.
According to above-mentioned decision, arbitration circuit 11 provides an enabling signal for the first requests for arbitration circuit 12-1.This first requests for arbitration circuit 12-1 responds this enabling signal and an exercisable enabling signal is provided for first control circuit 13-1.But being provided with, first control circuit 13-1 enters mode of operation behind this operation start signal.
Suppose that this external unit is to be used for storing a plurality of memory of data.First control circuit 13-1 controls this storer makes it become the access starting state.In addition, first control circuit 13-1 provides an expression to allow the access permission signal of this storage access for the first request source 14-1.
The first request source 14-1 responds this access permission signal and begins to lead to the inlet of this storer so that read data from this storer.In case lead to the inlet of this storer, the first request source 14-1 can write data this storer.
When the first request source 14-1 was through with access to storer, the first request source 14-1 provided an access end signal for first control circuit 13-1.First control circuit 13-1 responds this access end signal, makes this storer become the attendant exclusion state.In addition, first control circuit 13-1 provides an EO signal to finish communicating by letter between the first request source 14-1 and storer with notice arbitration circuit 11 for the first requests for arbitration circuit 12-1.
After arbitration circuit 11 was learnt sign off between the first request source 14-1 and storer, arbitration circuit 11 just may receive another arbitration request signal.Be that arbitration circuit 11 becomes mode of operation from waiting status.
As from above-mentioned understandable, arbitration circuit 11 provides enabling signal for the second requests for arbitration circuit 12-2 when arbitration device 10 receives the second and the 3rd request signal simultaneously.The second requests for arbitration circuit 12-2 and second control circuit 13-2 operating aspect are similar to the first requests for arbitration circuit 12-1 and first control circuit 13-1 respectively.
Although positive integer k equals 3 in the above description, it can become a bigger positive integer.Be that arbitration device 10 can receive a large amount of request signals simultaneously.Because arbitration device 10 is arbitrated the right to use of external unit in first to k request source, so must adjust its structure when positive integer k increases.More particularly, arbitration circuit 11 will know that the priority of each request source is essential.Therefore, arbitration circuit 11 must be stored a large amount of priority along with the increase of positive integer in traditional moderator.
In addition, in traditional moderator, it is difficult giving the remaining requests source with the external unit right to use when having the specific request signal of the frequent generation of specific request source of limit priority for one.
Also have, in traditional moderator, the right to use that each when contingents take place arbitration circuit 11 in first to k request source will obtain external unit all is impossible.
With reference to Fig. 2, the moderator of the most preferred embodiment according to the present invention will be continued to describe.The diagram moderator structurally is different from moderator 10 described in conjunction with Figure 1, and therefore by label 20 expressions.Moderator 20 comprises first to k arbitration circuit 21-1 to 21-k, they each structurally all be different from arbitration circuit 11 described in conjunction with Figure 1.
K arbitration circuit 21-k comprises k pulse generating circuit 31-k, k and door 32-k, k delay circuit 33-k, a k inhibit circuit 34-k and k control circuit 35-k, all these will be described in detail later, and this is that k is the variable between 1 to k.
In illustrative example, positive integer k equals 3.First to the 3rd arbitration circuit 21-1 links to each other to 14-3 with first to the 3rd request source 14-1 respectively to 21-3.As described in conjunction with Figure 1, first to the 3rd request source 14-1 links to each other with the external unit (not shown) to each of 14-3.
Enter mode of operation by supply with clock enabling signal first to the 3rd arbitration circuit 21-1 of first to the 3rd arbitration circuit 21-1 by clock cable 36 to 21-3 to 21-3.More particularly, clock signal is added to first to the 3rd pulse generating circuit 31-1 to 31-3, first to the 3rd delay circuit 33-1 to 33-3 and first to the 3rd inhibit circuit 34-1 to 34-3.First to the 3rd pulse generating circuit 31-1 to 31-3, first to the 3rd delay circuit 33-1 to 33-3 and first to the 3rd inhibit circuit 34-1 each in the 34-3 all it enters mode of operation by this clock enabling signal.
As described in conjunction with Figure 1, first to the 3rd request source 14-1 produces first to the 3rd request signal about communicating with external unit respectively to 14-3.This first to the 3rd request signal has first to the 3rd priority respectively.First to the 3rd request signal is received to 21-3 by first to the 3rd arbitration circuit 21-1 respectively.
Now note the first arbitration circuit 21-1 among Fig. 2.First request signal is added to the first pulse generating circuit 31-1 among the first arbitration circuit 21-1.The first pulse generating circuit 31-1 responds first request signal and produces first pulse signal with first pulse, and each first pulse has high level under first predetermined period.First pulse signal from the first pulse generating circuit 31-1 is added to the first AND gate 32-1.
A high level signal that is marked with " H " in Fig. 2 is provided for again the first AND gate 32-1.As a result, the first AND gate 32-1 produces first coincidence AND signal according to this high level signal and first pulse signal.Or rather, the first AND gate 32-1 is created in first coincidence AND signal that has high level during first predetermined period.First coincidence AND signal is added to the first delay circuit 33-1 and the first inhibit circuit 34-1.The high level of first coincidence AND signal is used as first useful signal.
The first inhibit circuit 34-1 responds has low level first inhibit signal during first useful signal is created in first predetermined period.To offer the second and the 3rd arbitration circuit 21-2 and 21-3 from first inhibit signal of the first inhibit circuit 34-1.Just describe as the back, each responds the second and the 3rd arbitration circuit 21-2 and 21-3 first inhibit signal and stops arbitration operation.
The first delay circuit 33-1 had for the first scheduled delay cycle.The first delay circuit 33-1 responds first useful signal and is producing first inhibit signal after the cycle through first scheduled delay.To offer first control circuit 35-1 as the first operation start signal from first inhibit signal of the first delay circuit 33-1.
As described in conjunction with Figure 1, case of external equipment is to be used to store a plurality of memory of data.First control circuit 35-1 responds first this storer of operation start signal controlling makes it become the access starting state.In addition, first control circuit 35-1 provides an expression to allow the first access permission signal of storage access for the first request source 14-1.
The first request source 14-1 responds the inlet that the first access permission signal begins to lead to this storer.When the first request source 14-1 finished access to this storer, the first request source 14-1 was provided with the first access end signal for first control circuit 35-1.First control circuit 35-1 is provided the first access end signal makes this storer become the attendant exclusion state.In addition, first control circuit 35-1 provides the first EO signal for the first inhibit circuit 34-1.The first inhibit circuit 34-1 is provided with the first EO signal and stops to provide first inhibit signal to the second and the 3rd arbitration circuit 21-2 and 21-3.As a result, each of the second and the 3rd arbitration circuit 21-2 and 21-3 can both be carried out arbitration operation.
Now concentrate on the second arbitration circuit 21-2.When second request signal was offered the second pulse generating circuit 31-2, the second pulse generating circuit 31-2 produced second pulse signal with second pulse, and each pulse has high level at second predetermined period.Second predetermined period is different from first predetermined period.Second pulse signal from the second pulse generating circuit 31-2 is added to the second AND gate 32-2.
When the second AND gate 32-2 was not provided with first inhibit signal, this second AND gate 32-2 was created in second coincidence AND signal that has high level between second predetermined period.The high level of second coincidence AND signal is used as second useful signal and uses.
The second inhibit circuit 34-2 responds second useful signal and is provided with one for the 3rd arbitration circuit 21-2 to have low level second inhibit signal.The 3rd arbitration circuit 21-3 resembles and will describe in the back, responds second inhibit signal and stops arbitration operation.
The second delay circuit 33-2 has the second scheduled delay cycle that was different from for the first scheduled delay cycle.The second delay circuit 33-2 responds second useful signal and is producing second inhibit signal through all after dates of second scheduled delay.Second inhibit signal from the second delay circuit 33-2 is added to second control circuit 35-2 as the second operation start signal.The second control circuit 35-2 that is provided with the second operation start signal is to operate with the similar mode of first control circuit 35-1.That is, second control circuit 35-2 makes this storer become the access starting state and is provided with one second access permission signal for the second request source 14-2.
When the second request source 14-2 finished access to this storer, the second request source 14-2 provided the second access end signal for second control circuit 35-2.Second control circuit 35-2 responds the second access end signal makes storer become the attendant exclusion state.In addition, second control circuit 35-2 provides the second EO signal for the second inhibit circuit 34-2.The second inhibit circuit 34-2 that is provided with the second EO signal stops to provide second inhibit signal to the 3rd arbitration circuit 21-3.As a result, make the 3rd arbitration circuit 21-3 can carry out arbitration operation.
When the second AND gate 32-2 that first inhibit signal is added among the second arbitration circuit 21-2, because first inhibit signal has low level as mentioned above, the second AND gate 32-2 always produces has low level second coincidence AND signal.That is, when first inhibit signal was offered the second AND gate 32-2, the second AND gate 32-2 did not produce second useful signal.When second useful signal was not added to the second delay circuit 33-2, the second delay circuit 33-2 did not produce the second operation start signal.Therefore, second control circuit 35-2 can not make storer become the access starting state.In addition, second control circuit 35-2 provides the second access permission signal for the second request source 14-2.That is, the second request source 14-2 can not obtain the right to use of storer.
Similarly, when second useful signal not being offered the second inhibit circuit 34-2, the second inhibit circuit 34-2 does not produce second inhibit signal.
Now with attention directing the 3rd arbitration circuit 21-3.When the 3rd request signal was added to the 3rd pulse generating circuit 31-3, the 3rd pulse generating circuit 31-3 produced the 3rd pulse signal with the 3rd pulse, and its each pulse has high level at the 3rd predetermined period.The 3rd predetermined period is different from each of first and second predetermined periods.The 3rd pulse signal from the 3rd pulse generating circuit 31-3 is added to the 3rd AND gate 32-3.
When first and second inhibit signals not being offered the 3rd AND gate 32-3, the 3rd AND gate 32-3 is created in the 3rd coincidence AND signal that has high level in the 3rd predetermined period.The high level of the 3rd coincidence AND signal is used as the 3rd useful signal.
Generation has low level the 3rd inhibit signal although the 3rd inhibit circuit 34-3 responds the 3rd useful signal, owing to there is not subordinate's arbitration circuit, the 3rd inhibit signal is not carried out conveying.
The 3rd delay circuit 33-3 has and is different from each the 3rd scheduled delay cycle in the first and second scheduled delay cycles.The 3rd delay circuit 33-3 respond the 3rd useful signal through the 3rd time delay week after date produce the 3rd inhibit signal.The 3rd inhibit signal from the 3rd delay circuit 33-3 offers the 3rd control circuit 35-3 as the 3rd operation start signal.The 3rd control circuit 35-3 that is provided with the 3rd operation start signal is to operate with the similar mode of first control circuit 35-1.That is, the 3rd control circuit 35-3 makes storer be in the access starting state and the 3rd access permission signal is provided for the 3rd request source 14-3.
When the 3rd request source 14-3 finished the access of storer, the 3rd request source 14-3 provided the 3rd access end signal for the 3rd control circuit 35-3.The 3rd control circuit 35-3 responds the 3rd access end signal makes storer become the attendant exclusion state.In addition, the 3rd control circuit 35-3 provides the 3rd EO signal for the 3rd inhibit circuit 34-3.The 3rd inhibit circuit 34-3 that is provided with the 3rd EO signal stops to produce the 3rd inhibit signal.
When any offers the 3rd AND gate 32-3 among the 3rd arbitration circuit 21-3 in first and second inhibit signals, since as mentioned above first and second inhibit signals each all have low level, have low level the 3rd coincidence AND signal so the 3rd AND gate 32-3 always produces.That is, when any of first and second inhibit signals offered the 3rd AND gate 32-3, the 3rd AND gate 32-3 did not produce the 3rd useful signal.When the 3rd useful signal was not added to the 3rd delay circuit 33-3, the 3rd delay circuit 33-3 did not produce the 3rd operation start signal.Therefore, the 3rd control circuit 35-3 can not make storer become the access starting state.In addition, the 3rd control circuit 35-3 provides the 3rd access permission signal for the 3rd request source 14-3.That is, the 3rd request source 14-3 can not obtain the right to use to storer.
As very intelligible from top description, the first request source 14-1 has the priority of the first estate in the above-described embodiments.The second request source 14-2 has the priority of second grade.And the 3rd request source 14-3 has the priority of the tertiary gradient.
As mentioned above, first to the 3rd predetermined period differs from one another.In addition, first to the 3rd cycle time delay is differing from each other.Therefore, even the first request source 14-1 often produces first request signal, the second request source 14-2 also might obtain the right to use of storer.Similarly, even the first and second request source 14-1 and 14-2 often produce first and second request signals respectively, the 3rd request source 14-3 still may obtain the right to use of storer.
Except that Fig. 2, refer again to Fig. 3, will describe relevant data packet transmission device with arbitration device shown in Fig. 2.Data in graph form packet transfer device 40 is used for by communication path data packet signal being sent to a receiving trap (not shown).This data packet transmission device 40 comprises direct access memory (DMA) circuit 41, transfer management table 42, data management table 43, data-carrier store 44, data packet transmission circuit 45, and confirms circuit 46.
In case when sending data packet signal to receiving trap, be provided with a series of input data just for dma circuit 41.Response transmission request signal, dma circuit 41 can utilize data management table 43 to go to check whether data-carrier store 44 has the dead zone.When data-carrier store had the dead zone, the inlet that dma circuit 41 leads to data management table 43 was set up a mark in this data management table 43.This mark is represented the use of this dead zone.The inlet that dma circuit 41 leads to data-carrier store 44 will be imported data and write on data-carrier store 44 these dead zones as stored data.In addition, dma circuit 41 can utilize transfer management table 42 to deposit address date therein in.The memory cell of the data of storing in the address date representative data storer 44.
Data packet transmission circuit 45 can utilize transfer management table 42 to check whether this table 42 has address date in the predetermined cycle.When the transfer management table had address date, data packet transmission circuit 45 was read the address date of transfer management table 42 to learn in the data-carrier store 44 by the memory cell of deposit data.Data packet transmission circuit 45 can utilize data-carrier store 44 to read according to address date and by the data packet transmission circuit 45 of deposit data sense data is sent to receiving trap as data packet signal by communication path as the sense data of data-carrier store 44.
When receiving trap received data packet signal, receiving trap sent an answer signal by communication path to data packet transmission device 40.This answer signal offers the affirmation circuit 46 in the data packet transmission device 40.Confirm to utilize data management table 43 to wipe this mark when circuit 46 is provided with answer signal.
As mentioned above, each of dma circuit 41 and data packet transmission circuit 45 all can utilize transfer management table 42 and data-carrier store 44 both.Each of dma circuit 41 and affirmation circuit 46 all can be utilized data management table 43.The access of dma circuit 41 may conflict mutually with the access of data packet transmission circuit 45 in transfer management table 42.Similarly, the access of dma circuit 41 may conflict mutually with the access of data packet transmission circuit 45 in data-carrier store 44.The access of dma circuit 41 may conflict mutually with the access of confirming circuit 46 in data management table 43.Therefore, data packet transmission device 40 includes the arbitration device shown in Fig. 2.
The first request source 14-1 can be used as dma circuit 41, data packet transmission circuit 45 and one of confirms in the circuit 46 operation.The second request source 14-2 can be used as dma circuit 41, data packet transmission circuit 45 and confirms another one operation in the circuit 46.The 3rd request source 14-3 also can be used as another operation in dma circuit 41, data packet transmission circuit 45 and the affirmation circuit 46.Each effect external unit of transfer management table 42, data management table 43 and data-carrier store 44.
Claims (8)
1, a kind of and first arbitration device that links to each other to K request source, each request source is all got in touch with external device communication, here K represents the positive integer greater than 1, described first provides first to K request signal for respectively described arbitration device to described K request source, when described first during to K request source and described external device communication, described arbitration device be used for responding described first to described K request signal in described first the use to the described external unit of described K request source arbitration, described arbitration device comprises:
Respectively with described first first to K the arbitration circuit that links to each other to described K request source;
Described first K the circuit in described K the arbitration circuit includes:
Respond the generation device of K request signal, be used for when described K arbitration circuit receives described K request signal, produce K enabling signal so that K request source and described external device communication, this is that K represents a variable between 1 to K; And
Feeding mechanism is used for when described K arbitration circuit receives described K request signal, provides K inhibit signal to described K arbitration circuit for (K+1), to stop generation (K+) to K enabling signal.
2, arbitration device as claimed in claim 1, receive described one respectively when described (k-1) request signal when described first to described (k-1) individual arbitration circuit, be supplied to described k arbitration circuit to first of (k-1) individual arbitration circuit to (k-1) individual inhibit signal from described first, wherein said generation (producing) device comprises:
Respond generation (generating) device of described k request signal, be used for all not providing described first respectively when described (k-1) individual inhibit signal when described first to described (k-1) individual arbitration circuit during k the predetermined period, produce k useful signal, and
Deferred mount with k scheduled delay cycle is used for giving described k useful signal to produce described k enabling signal with the described k scheduled delay cycle.
3, arbitration device as claimed in claim 2 is characterized in that described generating means comprises:
Respond the pulse generating unit of described k request signal, be used for during described k predetermined period, producing k pulse signal with high level, and
Door gear is used for all not providing described first respectively when described (k-1) individual inhibit signal when described first to described (k-1) individual arbitration circuit, responds described k pulse signal and produces described k useful signal.
4, arbitration device as claimed in claim 2 is characterized in that described generation device also comprises:
Respond the control device of described k enabling signal, be used to control described external unit realizing communicating by letter between described k request source and the described external unit, described control device responds described k enabling signal provides a representative to permit the enabling signal of communicating by letter between described k request source and the described external unit to give described k request source.
5, arbitration device as claimed in claim 3 is characterized in that described generation device also comprises:
Respond the control device of described k enabling signal, be used to control described external unit realizing communicating by letter between described k request source and the described external unit, described control device responds described k enabling signal and offers k request source will represent the enabling signal of communicating by letter between described k the request source of permission and the described external unit.
6, arbitration device as claimed in claim 3 is characterized in that:
Described feedway responds described k useful signal and provides described k inhibit signal to described k arbitration circuit for described (k+1).
7, arbitration device as claimed in claim 5 is characterized in that:
Described feedway responds described k useful signal, provides described k inhibit signal to give described (k+1) to k arbitration circuit.
8, arbitration device as claimed in claim 7, described k request source provide an end signal for when it finishes with described external device communication described control device.
It is characterized in that:
Described control device responds described end signal an end of communication signal is offered described feedway;
Described feedway responds described end of communication signal to be stopped to provide described k inhibit signal to described (k+1) to described k arbitration circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5270703A JP2626510B2 (en) | 1993-10-28 | 1993-10-28 | Mediation device |
| JP270703/93 | 1993-10-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1112260A true CN1112260A (en) | 1995-11-22 |
| CN1095124C CN1095124C (en) | 2002-11-27 |
Family
ID=17489789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 94113781 Expired - Fee Related CN1095124C (en) | 1993-10-28 | 1994-10-28 | Arbitrator device capable of readily modifying the structure |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2626510B2 (en) |
| CN (1) | CN1095124C (en) |
| DE (1) | DE4438416B4 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107315703A (en) * | 2017-05-17 | 2017-11-03 | 天津大学 | Double priority level control type fair arbitration device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5494925B2 (en) * | 2009-07-16 | 2014-05-21 | 日本電気株式会社 | Semiconductor integrated circuit, information processing apparatus, and processor performance guarantee method |
| RU2749151C1 (en) * | 2020-10-26 | 2021-06-07 | федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) | Task dispatcher arbiter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1487826B2 (en) * | 1966-05-21 | 1972-02-24 | Siemens AG, 1000 Berlin u. 8000 München | CIRCUIT ARRANGEMENT FOR PRIORITY-BASED DATA TRANSFER |
| JPS5534780A (en) * | 1978-09-04 | 1980-03-11 | Nec Corp | Priority decision device |
| IT1199745B (en) * | 1986-12-12 | 1988-12-30 | Honeywell Inf Systems | ACCESS ARBITRATOR CIRCUIT |
| DD286444A5 (en) * | 1989-08-03 | 1991-01-24 | Veb Carl Zeiss Jena,De | PROCESS FOR COUPLING MULTIMASTERABLE BUSES |
| JP2511588B2 (en) * | 1990-09-03 | 1996-06-26 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Data processing network, method for acquiring lock and serialization device |
-
1993
- 1993-10-28 JP JP5270703A patent/JP2626510B2/en not_active Expired - Fee Related
-
1994
- 1994-10-27 DE DE19944438416 patent/DE4438416B4/en not_active Expired - Fee Related
- 1994-10-28 CN CN 94113781 patent/CN1095124C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107315703A (en) * | 2017-05-17 | 2017-11-03 | 天津大学 | Double priority level control type fair arbitration device |
| CN107315703B (en) * | 2017-05-17 | 2020-08-25 | 天津大学 | Dual priority control type fair arbiter |
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| Publication number | Publication date |
|---|---|
| JPH07129503A (en) | 1995-05-19 |
| CN1095124C (en) | 2002-11-27 |
| DE4438416A1 (en) | 1995-05-04 |
| DE4438416B4 (en) | 2004-08-26 |
| JP2626510B2 (en) | 1997-07-02 |
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