JP2007079964A - Information processing apparatus and method for acquiring bus use right - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the number of signal lines for bus acquisition from increasing with increasing of the number of bus masters. <P>SOLUTION: An information processing apparatus has a bus 12 for data transfer, a determination signal line 14 to transmit input signals, and a plurality of bus masters which are connected to the bus 12 and the determination signal line 14, and configured with priority orders related to bus use right acquisition. When a bus master 16 which has not acquired the use right of the bus 12 requests for acquisition of the use right of the bus 12, another bus master 16 which must acquire the use right of the bus 12 outputs a priority order signal that indicates its own priority order to the signal line 14 simultaneously with the bus master 16. In addition, the other bus master 16 determines whether or not the use right of the bus 12 is acquired based on a combined signal which is combined with a plurality of priority order signals that are simultaneously output to the signal line 14 to perform data transfer through the bus 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a bus usage right acquisition method, and more particularly, to an information processing apparatus and a bus usage right acquisition method for transferring data via a bus when a plurality of bus masters acquire the bus usage right. .

  Conventionally, in an information processing apparatus, when a plurality of bus masters are connected to a bus, the bus master that has acquired the right to use the bus performs data transfer via the bus. At this time, it is necessary to arbitrate which bus master acquires the right to use the bus. This arbitration method is called a bus arbitration method (bus usage right acquisition method).

  In this bus arbitration method, in general, bus request signal lines and bus use permission signal lines corresponding to the number of bus masters existing on the bus are used, and each bus master exists as a bus use arbitrator. The channels are connected in a one-to-one correspondence.

  However, this bus arbitration method requires at least as many bus request signal lines and bus use permission signal lines as the number of bus masters existing on the bus, and a bus having a large number of bus masters requires a large number of bus request signal lines and buses. Only the number of bus request signal lines and bus use permission signal lines prepared in the bus arbiter can support the bus master, and it is necessary to change the bus arbiter when expanding.

  Therefore, as a bus arbitration method in which signal lines do not increase even if there are many bus masters, bus request signals from each bus request source are multiplexed and output as time-divided signals in slots, and the right to use the bus is obtained. A bus arbitration method is known in which a bus request source code of a bus request source is output to a request code output signal line of each bus request source (Patent Document 1).

  Further, a request highway for inserting a bus use request and priority from each input / output device into a predetermined time slot and transferring it to the bus arbitration means is connected to each input / output device and the bus adjustment means, and the bus There is known a bus arbitration system including a permission highway for transferring use permission to each input / output device (Patent Document 2).

  Each module that requires a bus use right detects a bus use right request acceptance cycle from the bus cycle on the bus, and if it is assigned to its own module among the existing signal lines during the bus use right request acceptance cycle. A bus usage right acquisition method is known in which a bus usage right request signal and a bus usage permission signal line are not required by sending a bus usage right request signal to the received signal line (Patent Document 3).

Also, a bus arbitration system is known in which a plurality of bus masters are daisy chained in a loop via a bus right control line, and a bus permission pulse circulates in this loop (Patent Document 4).
JP-A-2-45857 JP-A-9-198342 JP-A-2-224166 JP-A-5-28102

  However, according to the bus arbitration method described in Patent Document 1, the number of bus request signal lines is reduced, but since a request code output signal line is connected to each bus request source, the bus request source is If it increases, there is a problem that the number of signal lines increases.

  Further, according to the bus arbitration method described in Patent Document 2, there is a problem that it takes time until the bus use request is transmitted to the arbiter because the bus use request and the priority order are time-division multiplexed and output. .

  Further, according to the bus usage right acquisition method described in Patent Document 3, since it is necessary to monitor all signal lines connected to each module, it takes time to make a determination for acquiring the bus usage right. There is a problem that.

  Further, according to the bus arbitration method described in Patent Document 4, there is a problem that it takes time to determine the right to use the bus as the bus masters increase because the bus permission pulse circulates.

  The present invention has been made to solve the above-described problems, and prevents an increase in the number of signal lines for acquiring a bus with an increase in the number of bus masters, and for acquiring a right to use the bus. It is an object of the present invention to provide an information processing apparatus and a bus usage right acquisition method that can shorten the determination time.

  In order to achieve the above object, an information processing apparatus according to a first invention includes a bus for performing data transfer, a single signal line for transmitting an input signal, the bus, and the signal line. And a plurality of bus masters that have a priority set for acquiring the right to use the bus, and the bus master that needs to acquire the right to use the bus has not acquired the right to use the bus When acquisition of the right to use the bus is requested by another bus master, a priority signal indicating its own priority is output to the signal line simultaneously with the other bus master, and a plurality of signals simultaneously output to the signal line And determining whether or not the right to use the bus has been acquired based on the combined signal obtained by combining the priority signals of the first and second signals. It is configured to include a bus master group for performing the data transfer.

  According to the bus usage right acquisition method according to the second invention, a bus for performing data transfer, a single signal line for transmitting an input signal, and the bus and the signal line are connected. And a bus usage right acquisition method in the bus master of the information processing apparatus, including a bus master group including a plurality of bus masters set with a priority order for acquiring the bus usage right, wherein the bus usage right is acquired. A priority signal indicating its own priority at the same time as the other bus master when acquisition of the right to use the bus is requested by another bus master that has not yet acquired the right to use the bus. Is output to the signal line, and it is determined whether or not the right to use the bus has been acquired based on a composite signal obtained by combining a plurality of the priority signals output simultaneously to the signal line. , When it is determined that acquired the right to use the bus, it is characterized by performing data transfer through the bus.

  According to the first and second inventions, when a bus master that needs to acquire the right to use the bus is requested to acquire the right to use the bus by another bus master that has not acquired the right to use the bus. At the same time as other bus masters, a priority signal indicating its own priority is output to the signal line, and the right to use the bus is obtained based on a composite signal obtained by synthesizing a plurality of priority signals simultaneously output to the signal line. Determine whether or not.

  If it is determined that the right to use the bus has been acquired, the bus master performs data transfer via the bus.

  Therefore, when determining whether to acquire the right to use the bus, each bus master outputs a priority signal to one signal line, so that the number of signal lines for acquiring the bus increases as the number of bus masters increases. In order to determine whether or not the right to use the bus has been acquired based on a synthesized signal obtained by synthesizing a plurality of priority signals output simultaneously to the signal line, Judgment time for acquisition can be shortened.

  The priority order signal is a digital signal having a predetermined number of bits, and the composite signal is characterized in that a plurality of priority order signals are combined by one of logical sum and logical product for each bit. it can. Thereby, since a digital signal is handled, it can be realized by a simple digital circuit. In addition, this bus master outputs a priority signal to the signal line for each bit, monitors the composite signal in the signal line for each bit, and based on the composite signal, the other bus master has a priority for each bit. It can be determined whether the priority is higher, and output of the priority signal after the other bus master is determined to have higher priority can be stopped.

  Further, the bus master can be connected to the signal line by one of an open drain circuit and an open collector circuit. Thereby, for example, a wired AND circuit can be realized with a simple configuration, and a plurality of priority signals can be synthesized.

  The bus master includes a 3-state buffer and can be connected to a signal line by the 3-state buffer. Thereby, a plurality of priority signals can be synthesized with a simple configuration.

  In addition, when the bus master determines that, based on the composite signal in the signal line, the storage unit that stores the priority set in the bus master that has acquired the right to use the bus and the right to use the bus, When the self priority is updated to the lowest priority and another bus master acquires the right to use the bus, if the self priority is lower than the priority stored in the storage means, the self priority is increased. Updating means for updating as described above. Thereby, all bus masters can acquire the right to use the bus in order.

  According to a third aspect of the present invention, there is provided an information processing apparatus that performs data transfer, a bus for transmitting an input signal, and a priority order that is connected to the bus and that acquires the right to use the bus. The bus master having a plurality of defined bus masters, and the bus master having acquired the right to use the bus and the bus master in need of acquiring the right to use the bus, When acquisition is requested, a priority signal indicating its own priority is output to the bus simultaneously with the other bus master, and based on a synthesized signal obtained by synthesizing the plurality of priority signals simultaneously output to the bus. A bus master group that determines whether the right to use the bus has been acquired, and performs data transfer via the bus when it is determined that the right to use the bus has been acquired. It is configured to include a.

  According to the information processing apparatus according to the third invention, the bus master that has acquired the right to use the bus and the bus master that needs to acquire the right to use the bus have acquired the right to use the bus by another bus master. When a request is issued, a priority signal indicating its own priority is output to the bus simultaneously with other bus masters, and the bus is used based on a composite signal obtained by combining a plurality of priority signals output simultaneously to the bus. Determine whether you have acquired the right. If the bus master determines that the right to use the bus has been acquired, the bus master performs data transfer via the bus.

  Therefore, when determining whether to acquire the right to use the bus, each bus master outputs a priority signal to the bus, so that the number of signal lines for acquiring the bus is prevented from increasing as the number of bus masters increases. It is also possible to determine whether or not the right to use the bus has been acquired based on a composite signal obtained by combining a plurality of priority signals output simultaneously to the bus. Time can be shortened.

  In addition, since it is possible to determine bus acquisition and data transfer using only the bus, an inexpensive configuration can be achieved.

  As described above, according to the information processing apparatus and the bus usage right acquisition method of the present invention, each bus master outputs a priority signal to one signal line when determining whether to acquire the bus usage right. The number of bus acquisition signal lines can be prevented from increasing as the number of bus masters increases, and based on a synthesized signal obtained by synthesizing a plurality of priority signals simultaneously output to the signal lines. Since it is determined whether or not the right to use the bus has been acquired, it is possible to reduce the determination time for acquiring the right to use the bus.

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  As shown in FIG. 1, the information processing apparatus 10 according to the first embodiment includes a bus 12 for performing data transfer, and one determination for transmitting a signal for determining the acquisition of the right to use the bus 12. N bus masters 16A to 16C that are connected to the signal line 14, the bus 12 and the determination signal line 14 and transfer data via the bus 12 when the right to use the bus 12 is acquired. I have.

  As shown in FIG. 2, each of the bus masters 16A to 16C is provided with an output buffer 18 and an input buffer 20 that are bidirectionally connected to the determination signal line 14, and the output buffer 18 is an open drain. It is a buffer composed of either a circuit or an open collector circuit. The outputs of the output buffers 18 of the bus masters 16A to 16C are commonly connected to the determination signal line 14, and are wired OR (also logically AND, so they are also called wired AND). Therefore, the signal on the determination signal line 14 is a signal synthesized by taking the logical product of the signal levels from the output buffer 18.

  Since the output buffer 18 is a buffer composed of an open drain circuit and an open collector circuit, the determination signal line 14 is provided with a pull-up resistor 22. The input buffer 20 outputs a REQIN signal based on the signal transmitted through the determination signal line 14.

  The bus masters 16A to 16C are provided with a bus acquisition determination sequencer 24 configured by a sequential circuit that outputs the REQOUT signal to the output buffer 18 and receives the REQIN signal from the input buffer 20. When a high-level REQOUT signal is output from the acquisition determination sequencer 24, the output buffer 18 connects the determination signal line 14 to the ground potential so that the determination signal line 14 becomes a low-level potential. Yes. Therefore, the output buffer 18 outputs either a low level or a high level digital signal to the determination signal line 14 based on the input REQOUT signal.

  The bus acquisition determination sequencer 24 outputs a BUSOK signal indicating whether or not the right to use the bus 12 has been acquired to a bus control circuit described later, and has acquired the right to use the bus 12. In a state, a high level BUSOK signal is output. In a state where the right to use the bus 12 is not acquired, a low level BUSOK signal is output.

  Each of the bus masters 16A to 16C is provided with a priority level register 26 in which information indicating a priority order (priority level value) is stored. The CPU of the information processing apparatus 10 (not shown) stores the bus masters 16A to 16C. Priorities are determined in advance for each, and information (priority level values) indicating the priorities is stored in the priority level register 26 via the bus 12.

  As shown in FIG. 3, for example, priority level values of 0 to 7 are assigned to the priority level values of 8 bus masters, and the priority level value is a 3-bit value. In the present embodiment, the highest priority level value is set to 0, and the lowest priority level value is set to 7. The priority level value stored in the priority level register 26 is input to the bus acquisition determination sequencer 24 as PLVL [2: 0]. As a precondition in the present embodiment, the priority level value is unique for all bus masters, and the same priority order is not set for a plurality of bus masters.

  Each of the bus masters 16A to 16C is provided with a bus control circuit 28 that controls data transfer via the bus 12, and is provided with a specific circuit 30 that is mounted to realize a function specific to the bus master. . The bus master is, for example, a memory unit, an Ethernet (registered trademark) controller, or a hard disk controller, and the unique circuit 30 is a circuit for realizing these unique functions. The data transfer performed by the bus masters 16A to 16C includes not only transmitting data but also receiving data.

  Examples of the bus 12 include a PCI bus, a CPU bus, and a memory bus.

  Next, the meaning of the signal in the determination signal line 14 will be described with reference to FIGS. As shown in FIG. 4, a case where the number of bus masters is 1 to 4 and the priority level value is a 2-bit value will be described. The determination signal line 14 is normally in an idle state, and in this state, the signal on the determination signal line 14 is at a high level. In the state where the bus acquisition determination is performed, the Start bit (signal is at a low level) is first synchronized with the bus clock, followed by the priority level determination field. The priority level determination field is made up of a 2-bit signal, and after the priority level determination field, the Idle state is entered or the next bus acquisition determination starting from the Start bit is made.

  Further, when the number of bus masters is 1 to 8, as shown in FIG. 5, the priority level value is a 3-bit value, and the priority level determination field is a 3-bit signal. Hereinafter, a case where the priority level value is a 3-bit value will be described.

  Next, the bus acquisition determination process executed by the bus acquisition determination sequencer 24 will be described with reference to FIG. Hereinafter, the case of the bus acquisition determination sequencer 24 of the bus master 16A will be described as an example.

  First, in step 100, a high-level REQOUT signal is output to the output buffer 18 as an idle state, and a low-level BUSOK signal is output to the bus control circuit 28. In step 102, the REQIN signal is at a high level. In addition, it is determined whether there is a bus usage right acquisition request, and there is no bus usage right acquisition request from the other bus masters 16B, 16C, so that the REQIN signal is at a high level and the bus control circuit 28 of the bus master 16A. If there is no request for acquiring the right to use the bus, step 102 is repeated. On the other hand, there is a request for acquiring the right to use the bus from the other bus masters 16B and 16C, or the REQIN signal goes low, or an external instruction is issued. As a result, the bus control circuit 28 needs to acquire the right to use the bus. From 28 in the case where there is used right acquisition request of the bus 12, the process proceeds to step 104.

  In step 104, it is determined whether or not the REQIN signal is at a high level and there is a bus usage right acquisition request. There is a bus usage right acquisition request from another bus master 16B, 16C, and the REQIN signal goes to a low level. Alternatively, if there is no bus use right acquisition request from the bus control circuit 28, the routine proceeds to step 107. On the other hand, if there is no request for acquiring the right to use the bus from the other bus masters 16B and 16C, the REQIN signal is at a high level, and there is a request for acquiring the right to use the bus 12 from the bus control circuit 28, step 106 follows. The low level REQOUT signal is output, the output buffer 18 is set to the ground potential, the other bus masters 16B and 16C are informed that the bus use right acquisition determination is to be performed, and the routine proceeds to step 108.

  In step 107, it is determined whether or not it is necessary to acquire the right to use the bus 12. If the bus control circuit 28 needs to acquire the right to use the bus, the process proceeds to step 108. If it is not necessary to acquire the right to use the bus, the process returns to step 102 because it does not participate in the determination of acquiring the bus usage right.

  In step 108, a signal indicating PLVL [2], which is the MSB side bit of the priority level value PLVL [2: 0] stored in the priority level register 26 as the REQOUT signal in accordance with the bus clock, is output to the output buffer 18. The priority order signal is output from the output buffer 18. The BUSOK signal is output again at the same level as the BUSOK signal output immediately before. In step 110, it is determined whether PLVL [2] is 1 and the REQIN signal is at a low level. PLVL [2] is 1, and PLVL [2] of another bus master is 0. In this case, a low-level priority signal is output from another buster, the signal on the determination signal line 14 synthesized by the logical product of the bits on the MSB side becomes low level, and the REQIN signal becomes low level. If this is the case, the other bus master determines that the priority is higher, gives up the right to use the bus, stops outputting the signal indicating the priority level value as the REQOUT signal, and receives priority from the output buffer 18. The output of the rank signal is stopped, and the process returns to step 100. However, PLVL [2] is 0, or high level priority signals are output from all the bus masters 16A to 16C. , Signal decision signal line 14 synthesized by the logical product is high level, the REQIN signal is high, the process proceeds to step 112.

  In step 112, a signal indicating PLVL [1] is output as the REQOUT signal, a priority signal is output from the output buffer 18, and a signal having the same level as the BUSOK signal output immediately before is output again as the BUSOK signal. To do. In step 114, it is determined whether PLVL [1] is 1 and the REQIN signal is at a low level. PLVL [1] is 1, and PLVL [1] of another bus master is 0. In this case, a low-level priority signal is output from another buster, the signal of the determination signal line 14 synthesized by the logical product of the target bits is low, and the REQIN signal is low. The other bus masters determine that the priority is higher, give up the bus use right, stop outputting the signal indicating the priority level value, and stop outputting the priority signal from the output buffer 18. Then, the process returns to Step 100, but if PLVL [1] is 0 or the REQIN signal is at the high level, the process proceeds to Step 116.

  In step 116, a signal indicating PLVL [0] is output as the REQOUT signal, the priority signal is output from the output buffer 18, and a signal having the same level as the BUSOK signal output immediately before is output again as the BUSOK signal. To do. In step 118, it is determined whether PLVL [0] is 1 and the REQIN signal is at a low level. PLVL [0] is 1, and PLVL [0] of another bus master is 0. If the determination signal line 14 is at the low level and the REQIN signal is at the low level, the other bus masters determine that the priority is higher and give up the right to use the bus. Returning to 100, if PLVL [0] is 0 or the REQIN signal is at high level, the routine proceeds to step 120.

  In step 120, the BUSOUT signal is set to the high level, and it is determined that the right to use the bus has been acquired, and the high level BUSOK signal is output to the bus control circuit 28. Then, the bus control circuit 28 starts data transfer via the bus 12.

  In the next step 122, it is determined whether or not the REQIN signal is at a high level. There is no request for acquiring the right to use the bus from other bus masters 16B and 16C, and the REQIN signal is not set to a low level by the Start bit. If it is level, step 122 is repeated, but if there is a bus use acquisition request from another bus master 16B, 16C, and there is a Start bit in the determination signal line 14, and the REQIN signal becomes low level, the flow returns to step 108, The bus use right acquisition determination is performed by the processing from step 108 to step 118.

  When the bus master 16A that has acquired the right to use the bus 12 ends the data transfer, the bus usage right is abandoned and a low-level BUSOK signal is output to the bus control circuit 28.

  Next, the signal level state of the determination signal line 14 when each of the bus masters 16A to 16C operates as described above will be described with reference to FIG. The bus master 16B (priority level value is 2, PVLV [2: 0] is 010) has acquired the right to use the bus, and the bus master 16A (priority level value is 1, PVLV [2: 0] is 001) first. A case will be described in which acquisition of a bus use right is requested and the bus master 16C (priority level value is 5, PVLV [2: 0] is 101) needs to acquire the bus use right.

  First, the bus master 16A first outputs the Start bit to the determination signal line 14 in synchronization with the bus clock, sets the determination signal line 14 to the low level, and outputs from the output buffer 18 of the bus master 16A at the timing of the next bus clock. A low level signal is output to the determination signal line 14 as a priority signal indicating 0 which is PLVL [2]. At this time, the other bus master 16B outputs a low-level priority signal indicating 0, which is its own PLVL [2], simultaneously to the bus master 16A to the determination signal line 14, and the bus master 16C has its own PLVL [2]. A high level priority signal indicating 1 is output to the determination signal line 14.

  In addition, a high level signal is output to the determination signal line 14 from a bus master not participating in the determination to acquire the right to use the bus.

  As a result, since the low-level priority signal is output to the determination signal line 14 connected by the wired AND, Bit2 in the priority level determination field becomes low level.

  Here, the bus master 16C determines that the other bus master has a higher priority, gives up the right to use the bus, stops outputting the priority level signal indicating the priority level value from the output buffer 18, Continue to output level signals.

  Similarly to the above, a priority signal is output to the determination signal line 14 for Bit1 and Bit0 in the priority level determination field, and the bus master who has given up the right to use the bus and participates in the determination to acquire the right to use the bus. As a result, the bus master 16A determines that the bus master 16A has the highest priority and does not give up the right to use the bus. Obtain usage rights. The signal in the priority level determination field indicates the priority level value of the bus master that acquires the right to use the bus.

  Thereafter, after the bus master 16A completes the data transfer and gives up the right to use the bus, the bus master 16C outputs the Start bit to the determination signal line 14, sets the determination signal line 14 to the low level, and the timing of the next bus clock. Thus, a high-level priority signal is output as a signal indicating 1 which is PLVL [2] from the output buffer 18 of the bus master 16C. At this time, the output buffer 18 of another bus master 16B outputs a low-level priority signal indicating 0 which is its own PLVL [2] simultaneously with the bus master 16C. As a result, a low-level signal is output to the determination signal line 14 that is connected to the wired AND, so that Bit 2 in the priority level determination field is at the low level.

  Here, the bus master 16C determines that the other bus master has a higher priority, gives up the right to use the bus, and stops outputting the priority signal indicating the priority level value from the output buffer 18. Continue to output high level signals.

  Similarly to the above, a signal is also output to the determination signal line 14 for Bit1 and Bit0 in the priority level determination field, and as a result, the bus master 16B determines that its own priority is highest and acquires the bus use right. .

  As described above, according to the information processing apparatus according to the first embodiment, each bus master outputs a priority signal to one determination signal line when determining whether to acquire the right to use the bus. Therefore, it is possible to prevent an increase in the number of signal lines for determining bus acquisition as the number of bus masters increases.

  In addition, in order to determine whether or not each bus master has acquired the right to use the bus based on a signal obtained by combining a plurality of priority signals output simultaneously to the determination signal line by logical product for each bit. The determination time for acquiring the right to use the bus can be shortened.

  In addition, since the signal input / output by the bus master is a digital signal composed of a high level signal and a low level signal, the bus master can be realized by a simple digital circuit, not a complicated circuit that handles many signal levels. Can do.

  In addition, by connecting each bus master to the determination signal line by one of an open drain circuit and an open collector circuit, for example, a wired AND circuit can be realized with a simple configuration, and a plurality of priority signals Can be synthesized.

  In the above embodiment, the case where another bus master can request acquisition of the right to use the bus while performing data transfer has been described as an example. However, buses from other bus masters until data transfer is completed. The use right acquisition request may be prohibited. In that case, after the data transfer is completed, a signal indicating that the bus use right is released from the bus master that has acquired the bus use right can be output, and a request for acquiring the bus use right can be made to another bus master. You can let them know that you ’ve become. In addition, regardless of the end of data transfer, a request for acquiring a bus use right by another bus master may be prohibited for a predetermined period after a bus master acquires the bus use right.

  Next, a second embodiment will be described. Note that portions similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The second embodiment is different from the first embodiment in that the output buffer is not a buffer constituted by an open drain circuit or an open collector circuit but is constituted by a three-state buffer.

  Only when the Start bit signal is output and when the signal indicating the priority level value is output, the bus acquisition determination sequencer 24 outputs the REQOUT signal of either the high level or the low level, and other than that. In this case, the REQOUT signal is not output. When the REQOUT signal is not output, the output buffer is in a high impedance state (High-Z state).

  Next, the signal level state of the determination signal line 14 when each of the bus masters 16A to 16C operates will be described with reference to FIG.

  First, in the idle state, since all the bus masters 16A to 12C are not driven with respect to the determination signal line 14, the output buffers of all the bus masters 16A to 12C are in the high-Z state. 22, the signal on the determination signal line 14 is at a high level.

  Also, in each bus master 16A-12C, when a high level REQOUT signal is output from the bus acquisition determination sequencer 24 to the output buffer, a high level signal is output to the determination signal line 14 to determine the bus acquisition determination. When the low-level REQOUT signal is output from the sequencer 24 to the output buffer, a low-level signal is output to the determination signal line 14.

  Therefore, if an output buffer composed of a three-state buffer is used, even if the device does not include an output buffer composed of an open drain circuit or a collector drain circuit, the increase in the signal line for judgment and the bus acquisition judgment are made. Therefore, it is possible to easily realize a reduction in time.

  In addition, since each bus master is connected to the determination signal by a three-state buffer, a plurality of priority signals can be synthesized with a simple configuration.

  Next, a third embodiment will be described. Note that portions similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the third embodiment, the priority level value stored in the priority level register of the bus master is not fixed but variable, and the bus master can acquire the bus use right in a round robin manner. This is different from the embodiment.

  As shown in FIG. 9, a current master level storage register 202 and a comparison / addition circuit 204 are provided in the bus master 216 of the information processing apparatus 200 according to the third embodiment. The current priority level storage register 202 constantly monitors the REQIN signal, and always monitors the result of determination of acquiring the bus use right regardless of whether or not it participates in the determination of acquiring the bus use right. As a result, the priority level value of the bus master 216 that has acquired the right to use the bus is stored.

  The comparison / addition circuit 204 compares the value of the current priority level storage register 202 with the value of the priority level register 26. If the value of the priority level register 26 is lower in priority, the priority level register 26 Change the value to increase the priority by one. Further, when the self-acquisition / addition circuit 204 has acquired the right to use the bus, the comparison / addition circuit 204 updates the value of the priority level register 26 so that the priority becomes the lowest.

  Next, the update status of the priority level register values of all the bus masters 216 will be described with reference to FIG. Note that a total of eight bus masters 216A to 216H are provided, and at time 0, priority level values are set in order for the bus masters 216A to 216H by the CPU, and the bus use right acquisition request is made simultaneously. A case where it occurs from the bus masters 216B to 216F will be described.

  First, in the state of time 0, the bus use right acquisition determination process is performed, and the bus master 216B acquires the bus use right. At time 1, the priority level value of the bus master 216B has a priority by updating the priority level value. In the bus masters 216C to 216H, which are updated to the lowest priority level value 7 and at the same time set with a priority level value higher than the priority level value 1, their own priority level value is decremented so that the priority level increases by one. Updated.

  In the next bus usage right acquisition determination process, the bus master 216C acquires the bus usage right, and at time 2, the priority level value of the bus master 216C is updated to the priority level value 7 having the lowest priority by updating the priority level value. At the same time, in the bus masters 216B and 216D to 216H in which the priority level value larger than the priority level value 1 is set, the own priority level value is decremented and updated.

  Then, the data transfer by the bus master 216C is completed, there is no request for acquiring the bus use right, the bus master 216D acquires the bus use right by the next bus use right acquisition determination process, and at time 3, the priority level value is updated. The priority level value of the bus master 216D is updated to the priority level value 7, and at the same time, in the bus masters 216B, 216C, 216E to 216H in which the priority level value larger than the priority level value 1 is set, its own priority level value is decremented. Has been updated. At this time, it is assumed that the bus master 216A participates in acquiring the right to use the bus.

  Also, the bus master 216A acquires the bus use right by the next bus use right acquisition determination process, and at time 4, the priority level value of the bus master 216A is updated to the priority level value 7 by updating the priority level value. In the bus masters 216B to 216H in which the priority level value greater than 0 is set, the own priority level value is decremented and updated.

  Then, the data transfer by the bus master 216A is completed, there is no request for acquiring the bus usage right, the bus master 216E acquires the bus usage right by the next bus usage right acquisition determination process, and at time 5, the priority level value is updated. The priority level value of the bus master 216E is updated to the priority level value 7. At the same time, in the bus masters 216A to 216D and 216F to 216H in which the priority level value larger than the priority level value 0 is set, its own priority level value is decremented. Has been updated.

  Next, the data transfer by the bus master 216E is completed, there is no request for acquiring the bus use right, the bus master 216F acquires the bus use right by the next bus use right acquisition determination process, and at time 6, the same as above By updating the priority level value, the priority level value of the bus master 216F is updated to the priority level value 7. In the bus masters 216A to 216E, 216G, and 216H, its own priority level value is decremented and updated.

  Also, the data transfer by the bus master 216F is completed, the request for acquiring the bus use right is lost, and the bus master 216B acquires the bus use right by the next bus use right acquisition determination process. By updating the level value, the priority level value of the bus master 216B is updated to the priority level value 7, and in the bus masters 216A, 216C to 216H, its own priority level value is decremented and updated.

  By updating the priority level value as described above, the bus use right is acquired in the order of bus master 216B → bus master 216C → bus master 216D → bus master 216A → bus master 216E → bus master 216F → bus master 216B. Each of 216A to 216H can acquire the right to use the bus.

  As described above, according to the information processing apparatus according to the third embodiment, every time a determination to acquire the right to use the bus is made, the priority level value of each bus master is updated, so that all the round robin methods are used. Bus masters can acquire the right to use the bus in order.

  Next, a fourth embodiment will be described. Note that portions similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the fourth embodiment, the first point is that one signal line serves as both a bus for performing data transfer and a signal line for transmitting a signal for determining the right to use the bus. This is different from the embodiment.

  As shown in FIG. 11, after a signal transmission for determining the use of the bus is performed on one signal line, data transfer is performed by the bus master that has acquired the bus use right during a predetermined period. It has come to be.

  Therefore, it is possible to configure a serial bus that performs determination processing for bus use right acquisition and data transfer with one signal line, and an inexpensive configuration suppresses the increase in the number of determination signal lines and shortens time for determining bus acquisition. Can be realized.

It is the schematic which shows the structure of the information processing apparatus which concerns on the 1st Embodiment of this invention. It is the schematic which shows the structure of the bus master which concerns on the 1st Embodiment of this invention. It is a table showing an example of a priority level value. It is a figure which shows the signal level state of the signal line for judgment in case a priority level value is 2 bits. It is a figure which shows the signal level state of the signal line for judgment in case a priority level value is 3 bits. It is a flowchart which shows the content of the bus acquisition judgment processing routine in the sequencer for bus acquisition judgment of the bus master which concerns on the 1st Embodiment of this invention. It is a figure which shows the relationship between the signal output from each bus master in the 1st Embodiment of this invention, and the signal level state of the signal line for judgment. It is a figure which shows the relationship between the signal output from each bus master in the 2nd Embodiment of this invention, and the signal level state of the signal line for judgment. It is the schematic which shows the structure of the bus master which concerns on the 3rd Embodiment of this invention. It is a figure which shows the update condition of the priority level of the bus master which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

10, 200 Information processing device 12 Bus 14 Determination signal lines 16, 16 A, 16 B, 16 C, 216 Bus master 18 Output buffer 20 Input buffer 24 Bus acquisition determination sequencer 26 Priority level register 28 Bus control circuit 202 Current priority level storage register 204 Comparison / addition circuit

Claims (8)

A bus for data transfer, and
One signal line for transmitting the input signal;
A plurality of bus masters connected to the bus and the signal line and set with a priority for acquiring the right to use the bus, and the bus master that needs to acquire the right to use the bus When acquisition of the right to use the bus is requested by another bus master that has not acquired the right, a priority signal indicating its own priority is output to the signal line simultaneously with the other bus master, and the signal line On the basis of a composite signal obtained by synthesizing a plurality of the priority signals output simultaneously, whether or not the right to use the bus has been acquired, and if it is determined that the right to use the bus has been acquired, A bus master group for transferring data via the bus;
An information processing apparatus including: The priority signal is a digital signal having a predetermined number of bits,
2. The information processing apparatus according to claim 1, wherein the synthesized signal is obtained by synthesizing the priority signal by one of a logical sum and a logical product for each bit.   The bus master outputs the priority signal to the signal line for each bit and monitors a composite signal in the signal line for each bit, and the other bus master has priority for each bit based on the composite signal. The information processing apparatus according to claim 2, wherein it is determined whether or not the priority is higher and the output of the priority signal after the other bus master is determined to have higher priority is stopped.   The information processing apparatus according to claim 1, wherein the bus master is connected to the signal line by one of an open drain circuit and an open collector circuit.   The information processing apparatus according to claim 1, wherein the bus master includes a three-state buffer, and is connected to the signal line by the three-state buffer. The bus master stores the priority set for the bus master that has acquired the right to use the bus based on the composite signal in the signal line;
If it is determined that the right to use the bus has been acquired, update its own priority to the lowest priority,
When another bus master has acquired the right to use the bus, an update means for updating the self priority to be higher if the self priority is lower than the priority stored in the storage means;
The information processing apparatus according to any one of claims 1 to 5, further comprising: A bus for performing data transfer and transmitting an input signal;
The bus master that is connected to the bus and has a plurality of bus masters that have predetermined priorities for acquiring the right to use the bus, and the bus master that has acquired the right to use the bus and the need to acquire the right to use the bus When the bus master requesting the right to use the bus is requested by another bus master, the bus master outputs a priority signal indicating its own priority to the bus at the same time as the other bus master. Based on a synthesized signal obtained by synthesizing a plurality of the priority signals output to the bus at the same time, it is determined whether the right to use the bus has been acquired, and if it is determined that the right to use the bus has been acquired, A bus master group for transferring data via the bus;
An information processing apparatus including: A bus for performing data transfer, a signal line for transmitting an input signal, a bus connected to the bus and the signal line, and a priority order for acquiring the right to use the bus is set. A bus usage right acquisition method in the bus master of an information processing device including a bus master group including a plurality of bus masters,
When it is necessary to acquire the right to use the bus, and when the acquisition of the right to use the bus is requested by another bus master that has not acquired the right to use the bus, the self-priority is given simultaneously with the other bus master. A priority signal indicating a priority is output to the signal line, and whether or not the right to use the bus has been acquired based on a composite signal obtained by combining the plurality of priority signals simultaneously output to the signal line. A bus usage right acquisition method comprising: determining and obtaining data transfer through the bus when it is determined that the bus usage right has been acquired.

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