JP2007206878A - Clock synchronous serial interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit and receive serial data with a master device having a different transmitting and receiving format. <P>SOLUTION: An interface circuit 103 is a clock synchronous serial interface circuit provided in a peripheral device 102 of a system for transmitting a serial clock from a CPU 101 to the peripheral device 102 and transmitting and receiving serial data containing address information of the peripheral device 102 and data information by the serial clock. The interface circuit 103 determines the transmitting format of serial data of the CPU 101 based on the state of a predetermined bit of the serial data by a mode selection part 201 or the like. The serial data is received according to the transmitting format of the CPU 101 by a S/P conversion part 204. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock synchronous serial interface circuit which transmits a serial clock from a master device to a slave device and transmits / receives serial data including address information and data information of the slave device by the serial clock.

  Conventionally, when a peripheral device such as a memory is connected to a CPU, a system is configured in which the CPU serves as a master device and the peripheral device operates as a slave device. In such a system, the master device supplies a serial clock for synchronization to the slave device, and the CPU master device selects a slave device to which the serial signal is transmitted and received by a select signal (for example, Patent Document 1 below) And 2).

  For example, the serial transmission apparatus according to Patent Document 1 below selects and outputs either the first or second slave address selection unit based on the block selection signal from the master controller by the slave address selection unit. Then, the comparison unit compares the slave address detected by the slave address detection unit with the slave address supplied from the slave address selection unit, and outputs the result.

  In addition, the clock synchronous serial interface circuit according to Patent Document 2 described below is a system that selects a slave that is a serial signal transmission / reception partner by a slave select signal when transmitting a serial clock from a master to a slave. It is a clock synchronous serial interface circuit provided.

  Specifically, the serial clock polarity discriminating circuit that automatically discriminates the polarity of the serial clock sent by the master based on the slave select signal and the serial clock received from the master based on the discrimination result of the polarity discriminating circuit A clock generation unit that generates a type of clock required by the slave.

JP 2000-172635 A JP 2000-010917 A

  However, according to the above-described prior art, since it is not a configuration having an interface conversion function that allows access from a plurality of types of master devices to one slave device, There is a problem that a serial transmission device having a unique interface and a serial interface circuit are necessary.

  Also, some slave devices do not have a configuration for writing transfer data from the master device to multiple address spaces at the same time, or control the control signal when writing data from the master device to the slave device continuously by software. There are problems to be solved in terms of system control.

  An object of the present invention is to provide a clock synchronous serial interface circuit that can efficiently cope with serial data transmission / reception with a plurality of master devices having different transmission / reception formats in order to eliminate the above-described problems caused by the prior art. And

  In order to solve the above-described problems and achieve the object, a clock synchronous serial interface circuit according to the invention of claim 1 sends a serial clock from a master device to a slave device, and the address of the slave device by the serial clock. A clock synchronous serial interface circuit provided in the slave device of a system for transmitting and receiving serial data including information and data information, and transmitted from the master device based on a predetermined bit state of the serial data Determining means for determining the transmission format of the serial data; and receiving means for receiving the serial data in accordance with the transmission format determined by the determining means.

  According to the first aspect of the invention, by having the receiving means for receiving the serial data in accordance with the transmission format of the master device, it becomes possible for one slave device to correspond to the transmission formats of a plurality of master devices. , Can expand the expandability of the system. Further, it is not necessary to prepare a plurality of slave devices according to the transmission format, and the cost can be reduced in the operation of the system.

  According to a second aspect of the present invention, a clock synchronous serial interface circuit transmits a serial clock from a master device to a slave device, and transmits and receives serial data including address information and data information of the slave device by the serial clock. A clock-synchronous serial interface circuit provided in the slave device of the system for determining, based on a state of a predetermined bit of the serial data, a determination means for determining a reception format of the serial data of the master device; Transmission means for transmitting the serial data in accordance with the reception format determined by the determination means.

  According to the second aspect of the invention, by having the transmission means for transmitting the serial data in accordance with the reception format of the master device, it becomes possible for one slave device to correspond to the reception formats of a plurality of master devices. , Can expand the expandability of the system. Further, it is not necessary to prepare a plurality of slave devices according to the reception format, and the cost can be reduced in the operation of the system.

  According to a third aspect of the present invention, there is provided the clock synchronous serial interface circuit according to the second aspect, wherein the transmission means can select a clock edge indicating a transmission timing of the serial data from the serial clock. It is characterized by that.

  According to the third aspect of the present invention, since the clock edge can be selected by the transmission means, a circuit corresponding to the reception format of the master device can be freely set, and the expandability of the system can be further improved.

  According to a fourth aspect of the present invention, there is provided a clock synchronous serial interface circuit which transmits a serial clock from a master device to a slave device and transmits / receives serial data including address information and data information of the slave device by the serial clock. A state of a bit of the address information that is a remainder when the address information is larger than the number of bits constituting the address space of the slave device. And writing means for simultaneously writing the data information in an area constituting a shared address in the slave device.

  According to the fourth aspect of the present invention, command setting is performed when handling large-capacity data, such as full-color image data, by simultaneously writing data information from the master device in the area constituting the shared address in the slave device. Data processing efficiency can be improved, such as shortening time.

  According to a fifth aspect of the present invention, there is provided a clock synchronous serial interface circuit which transmits a serial clock from a master device to a slave device and transmits / receives serial data including address information and data information of the slave device by the serial clock. A clock synchronous serial interface circuit provided in the slave device of the system to acquire two signals other than the serial clock and the serial data from the master device, and the acquisition unit Based on a combination of logic levels of two signals, a determination means for determining whether or not to continuously transfer the data information sent from the master device; and when the determination means determines that continuous transfer is to be performed, the slave Dress And updating means for updating an internal address in synchronization with a predetermined counter value generated by the serial clock, characterized in that it comprises a.

  According to the fifth aspect of the present invention, the data transfer time to the slave device is drastically improved by updating the address in the slave device at the time of continuous transfer in synchronization with the specific counter value generated by the serial clock. To reduce the serial data communication time margin.

  According to a sixth aspect of the present invention, there is provided a clock synchronous serial interface circuit which transmits a serial clock from a master device to a slave device and transmits / receives serial data including address information and data information of the slave device by the serial clock. A clock synchronous serial interface circuit provided in the slave device of the system to acquire two signals other than the serial clock and the serial data from the master device, and the acquisition unit Based on two signals, generation means for generating a control clock for controlling the write timing of the serial data sent from the master device, and abnormal states of the serial clock and the two signals are indicated by the control clock. Detecting means for detecting each based on the status of the network, and when detecting the abnormality by the detecting means, stopping means for stopping the serial data transmission / reception operation with the master device, and detecting the abnormality by the detecting means. And an informing means for informing the abnormal state when detected.

  According to the sixth aspect of the present invention, when an abnormality is detected during the serial data transfer period, the serial data transmission / reception operation between the master device and the slave device is stopped and the abnormal state is notified. As a result, even if any abnormality occurs in each signal line of the serial command interface, it is detected immediately and notified to the master device at the same time, so that abnormal operation such as runaway of the system or device can be prevented in advance. it can.

  The clock synchronous serial interface circuit according to the present invention can efficiently cope with serial data transmission / reception with a plurality of master devices having different transmission / reception formats.

  Exemplary embodiments of a clock synchronous serial interface circuit according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment)
(System configuration of data transfer system)
First, the system configuration of the data transfer system 100 according to the embodiment will be described. FIG. 1 is an explanatory diagram of a system configuration of a data transfer system 100 according to the embodiment. The data transfer system 100 according to the embodiment includes a CPU 101 (101a to 101c) as a master device and a peripheral device 102 as a slave device. The peripheral device 102 includes an interface circuit 103 and a device body 104. A plurality of CPUs 101 and peripheral devices 102 are provided, and data is transferred between the respective CPUs 101 and the peripheral devices 102.

  The interface circuit 103 transmits a serial clock from the master device (CPU 101) to the slave device (peripheral device 102), and transmits and receives serial data including address information and data information of the peripheral device 102 by the serial clock. It is an interface circuit.

  The interface circuit 103 supplies two different signals other than the serial clock and serial data from the CPU 101, and gives a write timing from the CPU 101 to the peripheral device 102 by giving the peripheral device 102 a clock independent of the serial clock. Control. At this time, the CPU 101 specifies the transmission format of the CPU 101 according to the state of the specific bit of the serial data to be transferred, and has a serial data receiving circuit that matches the specified transmission format of the CPU 101.

  In this embodiment, it is assumed that the peripheral device 102 to which data is serially transferred has a register having a maximum 13-bit address space and a 1-address 16-bit configuration. In serial transfer, data in units of 8 bits (1 byte) is normally transferred in synchronization with a serial clock in consideration of a transmission format from the CPU 101.

  In this configuration, when data is serially transferred from the CPU 101, in the first 16 bits (2 bytes), the CPU 101 sets data including a read / write identification bit, a parity bit, etc. in addition to the 13-bit address data. Forward. Thereafter, the 16-bit data corresponding to the address pointer is transferred to the peripheral device 102 as the next 16-bit (2 bytes) data.

  Next, the circuit configuration of the interface circuit 103 will be described. FIG. 2 is a block diagram showing a circuit configuration of the interface circuit 103. The interface circuit 103 includes a mode selection unit 201, F / F 202 (202a, 202b), serial counter 203, S / P conversion unit 204, selector 205 (205a to 205c), address / data generation unit 206, register group 207, P / S converter 208 and abnormality detector 209. In addition, the specific operation | movement of each part is demonstrated with reference to FIGS.

(Data format and timing chart during data transfer)
Next, a data format and timing chart when data is transferred from the CPU 101 to the peripheral device 102 will be described as an example in which data: 012356757h is serially transferred. Data transfer includes a little endian method in which data is recorded / transmitted in order from the least significant byte of data divided every 1 byte, and a big endian method in which data is recorded / transmitted in order from the most significant byte.

  First, a case where data is transferred by the little endian method will be described. FIG. 3 is an explanatory diagram showing a data format when serial data transfer is performed by the little endian method. FIG. 4 is a timing chart when serial data transfer is performed in a little endian manner.

  The data format table of FIG. 3 shows the CPU internal address 301, word data 302, byte data 303, CPU transfer order 304, and transfer data 305 to peripheral devices.

  In the timing chart of FIG. 4, a transmission / reception clock 401 and transmission / reception data 402 are shown. In the transmission / reception data 402, data 421 is 1-byte data and indicates 23 × h (see FIG. 3). Data 422 is data of the second byte and indicates 01 × h. Similarly, data 423 is the 3rd byte data, 67 × h, and data 424 is the 4th byte data, indicating 45 × h. The horizontal axis represents time t.

  When serially transferring data: 012356757h from the little-endian CPU 101 to the peripheral device 102, the transfer order is 23h → 01h → 67h → 45h.

  Next, a case where data is transferred by the big endian method will be described. FIG. 5 is an explanatory diagram showing a data format when serial data transfer is performed by the big endian method. FIG. 6 is a timing chart when serial data transfer is performed by the big endian method.

  The data format table of FIG. 5 shows the CPU internal address 501, word data 502, byte data 503, CPU transfer order 504, and transfer data 505 to peripheral devices.

  In the timing chart of FIG. 6, a transmission / reception clock 601 and transmission / reception data 602 are shown. In the transmission / reception data 602, data 621 is 1-byte data and indicates 01 × h (see FIG. 5). Data 622 is data of the second byte and indicates 23 × h. Similarly, data 623 is the 3rd byte data and indicates 45 × h, and data 624 is the 4th byte data and indicates 67 × h. The horizontal axis represents time t.

  When the data: 0123567h is serially transferred from the big endian CPU 101 to the peripheral device 102, the transfer order is 01h → 23h → 45h → 67h.

  As described above, in order to transfer data from a plurality of CPUs 101 having different transmission formats to the peripheral device 102, it is necessary for the peripheral device 102 to match the transmission format (endian etc.) of the CPU 101. In this embodiment, an interface circuit 103 that matches the transmission format is provided in the peripheral device 102 so that it can cope with data transmission from a plurality of CPUs 101.

  Next, synchronous transfer of the interface circuit 103 for each transmission format will be described. First, the clock synchronous serial data transfer from the little endian CPU 101 (hereinafter referred to as CPU 101a) will be described. FIG. 7 is a timing chart in the case of performing clock synchronous serial data transfer by the little endian method. The timing charts shown in FIGS. 7 to 9 below show a case where “4567h” is written from the CPU 101 (CPU 101a to 101c) to the address 0123 of the peripheral device 102.

  In the timing chart of FIG. 7, the peripheral device chip select signal (SYCS_N) 701, serial clock (CLK_SY) 702, serial transfer data (SYDI_N) 703, serial transfer data (SYDO_N) 704 from the peripheral device, and continuous write described later. A mode signal (SYHS_N) 705 is shown.

  The register configuration of the peripheral device 102 is assumed to be an address space 13 bit, 1 address 16 bit configuration, and one register write operation is performed by 8 bits × 4 serial transfers according to the transmission format from the CPU 101a. At this time, among the remaining 3 bits at the time of 13-bit address transfer, 1 bit is set as an RW bit for separating read / write by the peripheral device 102, and the remaining 2 bits are transferred as 0 as unused bits.

  Next, clock-synchronized serial data transfer from the big-endian CPU 101 (hereinafter referred to as CPU 101b) will be described. FIG. 8 is a timing chart in the case of performing clock synchronous serial data transfer by the big endian method. 8, the peripheral device chip select signal (SYCS_N) 801, serial clock (CLK_SY) 802, serial transfer data (SYDI_N) 803, and serial transfer data (SYDO_N) 804 from the peripheral device are the same as FIG. A continuous write mode signal (SYHS_N) 805 to be described later is shown.

  In this case as well, as in the case of the little endian CPU 101, the register configuration of the peripheral device 102 has an address space of 13 bits and an address of 16 bits. According to the transmission format from the CPU 101b, 8 bits × 4 serial transfers are performed once. Assume that a register write operation is performed.

  Further, a clock-synchronized serial data transfer from a big-endian CPU 101 (hereinafter referred to as CPU 101c) different from the CPU 101b will be described. Unlike the CPU 101b, the CPU 101c performs one register write operation by serial transfer of 32 bits × one time for the peripheral device 102 having an address space of 13 bits and 1 address of 16 bits.

  FIG. 9 is a timing chart in the case of performing clock synchronous serial data transfer by the big endian method. 9 is similar to FIGS. 7 and 8, the peripheral device chip select signal (SYCS_N) 901, serial clock (CLK_SY) 902, serial transfer data (SYDI_N) 903, and serial transfer data from the peripheral device ( SYDO_N) 904 and a continuous write mode signal (SYHS_N) 905 described later are shown.

  As described above, the CPU 101c performs one register write operation by serial transfer of 32 bits × one time for the peripheral device 102 having the address space of 13 bits and 1 address of 16 bits. At this time, the remaining 3 bits at the time of 13-bit address transfer are 1 bit as an RW bit that separates read / write by the peripheral device 102, and the remaining 2 bits are transferred as 0 as an unused bit. However, as shown in FIG. Differently, the data is exchanged every 8 bits and transferred from the CPU 101c.

  7 to 9, when SYCS_N 701, 801, 901 and SYHS_N 705, 805, 905 are serially transferred from the CPU 101 in synchronization with CLK_SY 702, 802, 902, SYCS_N = L and SYHS_N = H. Shall be controlled. Here, _N of the signal line is defined as a name meaning low active.

(Operation of interface circuit 103)
Next, the operation of each component of the interface circuit 103 shown in FIG. 2 will be described. First, the mode selection unit 201 receives the chip select signal (SYCS_N) of the peripheral device 102 and the serial data (SYDI_N) from the CPU 101 in synchronization with the serial clock (CLK_SY). A normal write / read mode state and a continuous write mode state are generated by each signal obtained by ANDing the continuous write mode signals.

  Here, the normal write / read mode state is SYCS_N = L, SYHS_N = H. The continuous write mode state is SYCS_N = L and SYHS_N = L. These are valid signals during the period when the serial clock is applied to the peripheral device 102.

  The F / F 202a generates a reset signal of the P / S conversion unit 208 used when reading the serial counter 203 and the peripheral device 102 in synchronization with the negated edge of the SYCS_N signal by CLK_REF. By using the negated edge of the SYCS_N signal, the counter is cleared each time serial data (address information + data) is transferred from the CPU 101, and the internal circuit of the peripheral device 102 can be initialized.

  When the serial data (SYDI_N) from the CPU 101 is input in synchronization with the serial clock, the serial counter 203 starts the internal counter, and at the same time, the S / P converter 204 converts it into parallel data corresponding to the number of input bits. Here, data writing to the register of the peripheral device 102 is performed by generating a write pulse based on a clock independent of the serial clock. This independent clock is a reference clock of the peripheral device 102.

  FIG. 10 is a timing chart when a write pulse is generated using a reference clock. The timing chart shown in FIG. 10 shows a case where “4567h” is written to the address 0123 of the peripheral device 102 from the little-endian CPU 101.

  10 includes a chip select signal (SYCS_N) 1001, a serial clock (CLK_SY) 1002, serial transfer data (SYDI_N) 1003, a CLK_REF frequency 1004, a wren pulse 1005, and a register address determination timing 1006. A shift data determination timing 1007 and an n-address data determination timing 1008 are shown.

  The reference clock of the peripheral device 102 is given without stopping at a constant frequency while the power is on. The reason why the write pulse is not generated with the original serial clock is that the CPU 101 may be controlled to stop the serial clock (High state) every time a certain number of bits are transmitted. This is because there may be a timing restriction such as a write timing delay or a write failure.

  In FIG. 10, since serial data is transferred from the little-endian CPU 101, the serial data is a 13-bit address, and the 16-bit data is input at the timing shown in FIG. The data is exchanged by the address / data generation unit 206 of the peripheral device 102, and the selector 205b selects normal writing or continuous writing.

  Then, the 4567h data is written to a desired address (address 0123h) of the register group 207 by the F / F 202b by a wren pulse generated synchronously from the reference clock. Here, in order to obtain a margin for timing control, CLK_REF frequency> CLK_SY frequency. As described above, in order to receive data from the CPU 101 having a different endian method, the serial / parallel conversion (S / P conversion) data configuration in the peripheral device 102 needs to be matched with the transmission format of the CPU 101.

  Therefore, the CPU 101 transfers unique data that can be selected by the peripheral device 102 regardless of which endian CPU 101 is used. When the peripheral device 102 receives the data, the selection circuit of the CPU 101 and the selector 205 which is a data transmission format switching circuit are activated.

  Next, a case where the CPU 101a to 101c of each endian system is set as the default selection setting of the peripheral device 102 and the CPU 101 having a different endian system is selected and serial data transfer is performed will be described. First, a case where the little endian CPU 101a is selected as the default selection setting and the big endian CPU 101b is selected will be described.

  FIG. 11 is a timing chart of serial transfer data when a big-endian CPU is selected when the default is a little-endian system. This timing chart shows a case where “FFFEh” is written to the peripheral device 102.

  In the timing chart of FIG. 11, the chip select signal (SYCS_N) 1101 of the peripheral device, the serial clock (CLK_SY) 1102, the serial transfer data (SYDI_N) 1103, the asserted state 1104 of the CPU 101a, the asserted state 1105 of the CPU 101b, Serial transfer data (SYDO_N) 1106 and continuous write mode signal (SYHS_N) 1107 are shown. For convenience of description, in the following drawings, the asserted state of the CPU 101a is represented as CPU101 <a>, the asserted state of the CPU101b is represented as CPU101 <b>, and the asserted state of the CPU101c is represented as CPU101 <c>.

  The serial transfer data (SYDI_N) 1103 from the CPU 101a is input in synchronization with the falling edge of the serial clock (CLK_SY) 1102, and the CPU selection circuit is activated in the following procedure.

  First, “FFFEh” is written from the CPU 101 a to the peripheral device 102. Next, dummy data is transferred as subsequent 16-bit data. RW bit = 1 is the same as in the past, but for the portions in which the remaining two bits are set to 0 during normal writing, 1 is assigned to each portion and transferred to the peripheral device 102.

  In other words, only the transfer for selecting the CPU 101 is distinguished from the conventional write transfer by giving the extra bit 1 for transfer. As a result, the serial data reception format of the peripheral device 102 is changed from the default CPU 101a to the CPU 101b, and the serial data from the CPU 101b can be received from the next transfer according to the description of FIG. At this time, in the selector 205a of FIG. 2, the assertion of the state signal changes from the CPU 101a to the CPU 101b.

  Next, a case will be described in which the little-endian CPU 101a is set as the default selection setting and the 32-bit transfer big-endian CPU 101c is selected.

  FIG. 12 is a timing chart of serial transfer data when a 32-bit transfer big endian CPU is selected when the default is the little endian method. This timing chart shows a case where “FFFCh” is written to the peripheral device 102.

  In the timing chart of FIG. 12, similarly to FIG. 11, the chip select signal (SYCS_N) 1201, serial clock (CLK_SY) 1202, serial transfer data (SYDI_N) 1203 of the peripheral device, assert state 1204 of the CPU 101a, assert state of the CPU 101c 1205, serial transfer data (SYDO_N) 1206 from the peripheral device, and continuous write mode signal (SYHS_N) 1207 are shown.

  Also in the case shown in FIG. 12, as in FIG. 11, first, “FFFCh” is written from the CPU 101a to the peripheral device. Next, dummy data is transferred as subsequent 16-bit data. At this time, the transfer format is switched from the CPU 101a to the CPU 101c (the assertion of the status signal changes from the CPU 101a to the CPU 101c). Therefore, as shown in FIG. 9, serial data from the CPU 101c can be received.

  With the above procedure, when the endian CPUs 101a to 101c are set as the default selection of the peripheral device 102, the CPU 101 having a different endian system is selected to perform serial data transfer. Similarly, the combination of other CPUs 101 transfers the serial data from the default CPU 101 to the peripheral device and selects the CPU 101.

  FIG. 13 is a timing chart of serial transfer data when the little endian CPU is selected when the default is the big endian method of 32-bit transfer. This timing chart shows a case where “FFFDh” is written in the peripheral device 102.

  FIG. 14 is a timing chart of serial transfer data in the case of selecting a big-endian CPU of 8-bit transfer when the default is a big-endian method of 32-bit transfer. This timing chart shows a case where “FFFCh” is written to the peripheral device 102.

  FIG. 15 is a timing chart of serial transfer data when a little endian CPU is selected when the default is the big endian system. This timing chart shows a case where “FFFFh” is written to the peripheral device 102.

  FIG. 16 is a timing chart of serial transfer data when a 32-bit transfer big-endian CPU is selected when the default is a big-endian method of 8-bit transfer. This timing chart shows a case where “FFFCh” is written to the peripheral device 102.

  In the timing charts of FIGS. 13 to 16, as in FIG. 12, peripheral device chip select signals (SYCS_N) 1301, 1401, 1501, 1601, serial clocks (CLK_SY) 1302, 1402, 1502, 1602, serial transfer data (SYDI_N) 1303, 1403, 1503, 1603, CPU 101 asserted states 1304, 1305, 1404, 1405, 1504, 1505, 1604, 1605, serial transfer data (SYDO_N) 1306, 1406, 1506, 1606 from peripheral devices Write mode signals (SYHS_N) 1307, 1407, 1507, and 1607 are shown.

  As shown in FIGS. 11 to 16, when the first 12 bits of serial data to the peripheral device is “FFFh”, it is detected that the CPU 101 is a transmission format selection operation, and the value of the subsequent 4-bit data (“Fh” “ Eh "etc.) to identify the CPU 101 transmission format.

  The interface circuit 103 determines normal write / CPU selection using the first 12 bits of data from the CPU 101 to the peripheral device 102, and selects any of the CPUs 101a to 101c using the subsequent 4 bits of data. Regarding the timing at the time of reading, the selection control of the CPU 101 is not started, and the operation is performed as usual.

  As described above, the transmission format of the CPU 101 is specified by determining the transferred serial data by the peripheral device 102. The peripheral device 102 selects a shift circuit that matches the specified format. Since the peripheral device 102 selects the CPU 101a as a default selection, if the CPU 101a selects the CPU 101b or the CPU 101c and then returns to the CPU 101a, the peripheral device 102 uses the transmission format shown in FIGS. It is only necessary to transfer unique serial data.

  Next, a case where data is output from the peripheral device 102 to the CPU 101 will be described. FIG. 17 is a timing chart of serial transfer data when read data is output from a peripheral device to a little endian CPU. This timing chart shows a case where the data at address 0123 of the peripheral device 102 is read to the little-endian CPU 101a.

  FIG. 18 is a timing chart of serial transfer data when read data is output from a peripheral device to a big endian CPU. This timing chart shows a case where the data at the address 0123 of the peripheral device 102 is read to the big-endian CPU 101a.

  17 and 18, the peripheral device chip select signals (SYCS_N) 1701 and 1801, serial clocks (CLK_SY) 1702 and 1802, serial transfer data (SYDI_N) 1703 and 1803, and serial read data (SYDO_N) 1704 are shown. , 1804, and continuous write mode signals (SYHS_N) 1705, 1805, respectively.

  17 and FIG. 18 are compared, serial read data (SYDO_N) 1704 and 1804 are exchanged in units of 8 bits (see P / S conversion unit 208 in FIG. 2). This is in consideration of the reception format of the CPU 101 that receives the read data. Further, a register flag for exchanging read data in units of 8 bits may be provided for debugging the peripheral device 102 or the like. This can also be applied when serial data is written from the CPU 101 to the peripheral device 102.

  17 and 18, the serial data transmission circuit to the CPU 101 may be provided with clock edge selection means. Specifically, a serial clock edge selection register flag is provided in the internal register of the peripheral device 102 so that serial data is transferred to the CPU 101 having an arbitrary transmission / reception format using one of the edges of the serial clock. To.

  In this way, if the register flag of the peripheral device 102 is set in accordance with the change of the CPU 101, the operation can be easily switched (see the selector 205c in FIG. 2). In this case, the default setting value of the flag is matched with the operation edge of the CPU 101 set first. In FIG. 17, the output to the CPU 101 is performed at the falling edge of the serial clock. In FIG. 18, output to the CPU 101 is performed at the rising edge of the serial clock.

  Further, the address information transferred from the CPU 101 is larger than the number of bits constituting the address space of the peripheral device 102, and constitutes the shared address of the peripheral device 102 according to the state of the bits of the address information as a remainder. Data information from the CPU 101 may be simultaneously written in the area.

  FIG. 19 is a timing chart for simultaneous writing from a little endian CPU to a register. The timing chart of FIG. 19 shows a chip select signal (SYCS_N) 1901, serial clock (CLK_SY) 1902, serial transfer data (SYDI_N) 1903, register address 1904, chip select 1905, reference clock (CLK_REF) 1906, wren of peripheral devices. A pulse 1907, data 1908, serial read data (SYDO_N) 1909, and continuous write mode signal (SYHS_N) 1910 are shown.

  As shown in FIG. 19, add [12] bits are given as surplus bits from the CPU 101 to the peripheral device 102 whose address space is configured with add [11: 0]. The add [12] bit is a bit in an area not normally used in data transfer from the CPU 101 to the peripheral device 102, and is set to 0.

  On the other hand, the peripheral device 102 used in a full-color image forming apparatus or the like secures an area for each color in one peripheral device 102 so as to correspond to each color, and registers of the same function are provided in a common address space. May be placed. For example, γ correction table data corresponding to Y (yellow), M (magenta), C (cyan), and BK (black) is arranged at an arbitrary address of add [11: 0].

  Normally, when setting these table data, a method of transferring serial data from the CPU 101 for each block is generally used. However, in this case, when setting the same data, the number of colors is used for data transfer. It takes four times as much time. Therefore, by setting the add [12] bit, which is a surplus bit from the CPU 101, to 1, the same data is written to the common function register at a time.

  As shown in FIG. 19, the add [12] bit state is detected in the register group 207 of FIG. 2 by transferring the address information of 10XXh from the CPU 101. Since the detected bit state is 1, chip select of four registers of cs00XX, cs01XX, cs02XX, and cs03XX are asserted simultaneously.

  As a result, write data can be latched by asserting the wren pulse, and data can be written into the four register spaces of the peripheral device 102 by one serial data transfer, thereby shortening the communication time. Note that if it is not necessary to write simultaneously at the same time, the add [12] bit may be returned to 0 and data may be transmitted from the CPU 101 as usual.

  In addition, a selection circuit for continuously transferring data information from the CPU 101 to the peripheral device 102 according to the combination of the logic levels of the two signals is provided, and the internal address of the peripheral device 102 at the time of continuous transfer is a specific counter generated by a serial clock. It may be updated in synchronization with the value. Specifically, it automatically increments from an arbitrary register address in the peripheral device 102, and provides means corresponding to continuous data transfer (in units of 16 bits) from the CPU 101.

  FIG. 20 is a timing chart in the case where high-speed writing is performed from a little endian CPU to a register. The timing chart of FIG. 20 includes peripheral device chip select signal (SYCS_N) 2001, serial clock (CLK_SY) 2002, serial transfer data (SYDI_N) 2003, serial counter value 2004, address 2005, serial read data (SYDO_N) 2006, A continuous write mode signal (SYHS_N) 2007 is shown respectively.

  As shown in FIG. 20, first, serial transfer is performed in order to perform a normal write operation to an arbitrary address (address n) of the peripheral device 102. As described above, the chip select signal is controlled as SYCS_N, and the continuous write mode signals are controlled as SYCS_N = L and SYHS_N = H. At this time, the peripheral device 102 holds the address value = n transferred from the CPU 101.

  Here, the interface circuit 103 switches the normal write mode to the continuous write mode, but the CPU 101 changes the signal level setting to SYCS_N = L and SYHS_N = L. Further, following the data corresponding to the address = n of the peripheral device 102, the 16-bit serial data from the CPU 101 is subsequently written to the peripheral device 102 successively as n + 1, n + 2,.

  The address increment timing may be executed with an arbitrary value of an internal counter (for example, between 0 and F in the case of a serial clock synchronous counter) that operates during 16-bit transfer of serial data. FIG. 20 shows an example in which the internal address is automatically incremented at the latest rising edge of CLK_SY after the serial counter detects 604 = 05h for the continuous write data from the CPU 101 in the little endian format.

  However, since the write pulse signal (wren) output from the F / F 202b to the register group 207 uses a pulse signal synchronized with the reference clock, there is an asynchronous relationship with the serial clock. Further, depending on the ratio of the clock frequencies to each other, for example, when the serial clock frequency is larger than the reference clock frequency, the timing of incrementing the address is earlier than the timing of generating the write pulse signal (wren), and the address n is increased. Data to be written may be written at address n + 1.

  In such a case, a register flag or the like for arbitrarily changing the address increment timing may be provided according to the frequency ratio of each other, or the register address may be automatically incremented with a sufficient timing margin.

  In addition, the abnormality detection unit 209 detects an abnormal state of the serial clock and two different control signals (a peripheral device chip select signal and a continuous transfer control signal) using a clock independent of the serial clock. Further, when an abnormality is detected during serial data transfer from the CPU 101, the abnormality detection unit 209 stops the serial data transmission / reception operation between the CPU 101 and the peripheral device 102 and notifies the abnormal state.

  Specifically, the abnormality detection unit 209 detects a serial clock or a waveform abnormality (clock loss, noise) of two control signals (chip select signal and continuous transfer control signal of a peripheral device) and the like, and performs serial transfer. Detects errors other than data parity errors.

  FIG. 21 is a timing chart showing normal write timing from a little endian CPU to a peripheral device. In the timing chart of FIG. 21, the chip select signal (SYCS_N) 2101, serial clock (CLK_SY) 2102, serial transfer data (SYDI_N) 2103, serial counter value 2104, reference clock (CLK_REF) 2105, holding counter value 2106 of the peripheral device are shown. , An abnormality detection pulse 2107, a wren pulse 2108, a serial read data (SYDO_N) 2109, and a continuous write mode signal (SYHS_N) 2110 are shown.

  As shown in FIG. 21, for example, when a missing serial clock occurs during a write operation to the peripheral device 102 (part indicated by P in FIG. 21), the internal shift operation is not performed normally, and the serial counter is Incorrect value. As a result, the F / F 202b (wren pulse generation unit) that starts operation at the next rising edge of CLK_SY after serial counter = 1fh (31) does not operate, and the write operation to the 0123h address register is performed. It will not be.

  Therefore, the interface circuit 103 stores in advance the number of serial clock pulses required for one write operation. Then, every time one actual transfer process is completed (in this embodiment, the negate edge of the chip select signal: SYCS_N is detected), the number of serial clocks (CLK_SY) is counted with the reference clock (CLK_REF), Compare with pre-recorded values. When the comparison results are different, it is determined that there is an abnormality, and the abnormality detection unit 209 sends an abnormal state signal to the CPU 101.

  FIG. 22 is a timing chart showing abnormal write timing from a little endian CPU to a peripheral device. In the timing chart of FIG. 22, similarly to FIG. 21, peripheral device chip select signal (SYCS_N) 2201, serial clock (CLK_SY) 2202, serial transfer data (SYDI_N) 2203, serial counter value 2204, reference clock (CLK_REF). 2205, holding counter value 2206, abnormality detection pulse 2207, wren pulse 2208, serial read data (SYDO_N) 2209, and continuous write mode signal (SYHS_N) 2210 are shown.

  Note that the serial clock (CLK_SY) counting method is not limited to the above-described method, as long as the rising or falling edge is counted by the reference clock (CLK_REF).

  As described above, the abnormality detection unit 209 detects an abnormality due to generation of an extra clock such as noise or missing clock. Under the detected abnormal state, data writing to the peripheral device 102 is not performed, and the CPU 101 is notified of the abnormal state. This configuration is applied during a register read operation from the peripheral device 102 to the CPU 101.

  Further, the chip select signal (SYCS_N) and the continuous write mode signal (SYHS_N) are used for mode discrimination like a normal write / read operation and a continuous write operation. Therefore, when an abnormality occurs in these signals, an internal serial counter initialization or an internal serial counter transition abnormality occurs. As a result, each mode transition of normal write / read and continuous write mode does not function normally.

  Therefore, as a method for detecting the occurrence of an abnormality in the control signal, the chip select signal (SYCS_N), the continuous write mode signal (SYHS_N), and the like before the end of one transfer process, as with the serial clock (CLK_SY). If there is a change in the level of), control is performed so that it is determined to be abnormal. Then, as in the case of missing clock, data writing to the peripheral device 102 is not performed, and an abnormal state is notified to the CPU 101 at the same time.

  As described above, by detecting the abnormality timing as shown in FIG. 22 by the abnormality detection unit 209, it is possible to cope with error processing for a state abnormality other than a general parity error. As described above, the abnormality detection unit 209 detects the abnormality using other signals if it is configured to hold the change in the state of each input signal and compare it with the normal state. May be.

  In this embodiment, the CPU 101 to be selected by the peripheral device 102 is set to three types. However, considering the combination of serial data from the CPU 101 and the recognition conditions of the CPU 101 to be specified, there are three or more types. The CPU 101 can also be selected. This makes it possible to construct a system with higher expandability. In the present embodiment, the endian method of the CPU 101 is mainly described in the case of the little endian method. However, the present invention can be similarly applied to the CPU 101 of the big endian method and other methods, and further, a full-color image. It can also be carried out on equipment such as a forming apparatus.

  As described above, according to the clock synchronous serial interface circuit according to the present embodiment, a single slave device transmits and receives a plurality of master devices by transmitting and receiving serial data according to the transmission and reception format of the master device. It becomes possible to correspond to the format, and the expandability of the system can be expanded. Further, it is not necessary to prepare a plurality of slave devices according to the transmission / reception format, and the cost can be reduced in the operation of the system.

  Further, since the clock edge of the serial clock can be selected, a circuit corresponding to the transmission / reception format of the master device can be freely set, and the expandability of the system can be further improved.

  In addition, data processing such as shortening the command setting time when handling large data such as full-color image data by simultaneously writing data information from the master device to the area constituting the shared address inside the slave device Efficiency can be improved.

  When an abnormality is detected during the serial data transfer period, the serial data transmission / reception operation between the master device and the slave device is stopped and an abnormal state is notified. As a result, even if any abnormality occurs in each signal line of the serial command interface, it is detected immediately and notified to the master device at the same time, so that abnormal operation such as runaway of the system or device can be prevented in advance. it can.

  As described above, the clock synchronous serial interface circuit according to the present invention is useful for data transmission / reception with a master apparatus having different transmission / reception formats, and in particular, images of digital full-color printers, digital full-color copiers, digital multifunction peripherals, and the like. Suitable for forming apparatus and communication apparatus.

It is explanatory drawing which shows the system configuration | structure of the data transfer system 100 concerning embodiment. 3 is a block diagram showing a circuit configuration of an interface circuit 103. FIG. It is explanatory drawing which shows the data format in the case of performing serial data transfer by a little endian system. It is a timing chart in the case of performing serial data transfer by a little endian system. It is explanatory drawing which shows the data format in the case of performing serial data transfer by a big endian system. It is a timing chart in the case of performing serial data transfer by a big endian system. It is a timing chart in the case of performing clock synchronous serial data transfer by a little endian system. It is a timing chart in the case of performing clock synchronous serial data transfer by a big endian system. It is a timing chart in the case of performing clock synchronous serial data transfer by a big endian system. 6 is a timing chart when a write pulse is generated using a reference clock. 10 is a timing chart of serial transfer data when a big endian CPU is selected when a default is a little endian system. 10 is a timing chart of serial transfer data when a 32-bit transfer big-endian CPU is selected when the default is a little-endian method. FIG. 6 is a timing chart of serial transfer data when a little endian CPU is selected when a default is a big endian method of 32-bit transfer. FIG. 10 is a timing chart of serial transfer data when a CPU of an 8-bit transfer big endian method is selected when a default is a big endian method of 32 bit transfer. 6 is a timing chart of serial transfer data when a little endian CPU is selected when the default is a big endian system. FIG. 10 is a timing chart of serial transfer data when a 32-bit transfer big endian CPU is selected when the default is an 8-bit transfer big endian method. 6 is a timing chart of serial transfer data when read data is output from a peripheral device to a little endian CPU. 6 is a timing chart of serial transfer data when read data is output from a peripheral device to a big endian CPU. 6 is a timing chart in the case of simultaneous writing from a little endian CPU to a register. 7 is a timing chart when writing data from a little endian CPU to a register at high speed. 6 is a timing chart illustrating normal write timing from a little endian CPU to a peripheral device. 6 is a timing chart showing abnormal write timing from a little endian CPU to a peripheral device.

Explanation of symbols

100 data transfer system 101 CPU
102 Peripheral device 103 Interface circuit 201 Mode selection unit 202a, 202b F / F
203 Serial Counter 204 S / P Converter 205a to 205c Selector 206 Address / Data Generator 207 Register Group 208 P / S Converter 209 Abnormality Detector

Claims (6)

A clock synchronous serial interface circuit provided in the slave device of the system that transmits a serial clock from the master device to the slave device and transmits and receives serial data including address information and data information of the slave device by the serial clock. And
A determination unit that determines a transmission format of the serial data transmitted from the master device based on a predetermined bit state of the serial data;
Receiving means for receiving the serial data in accordance with the transmission format determined by the determining means;
A clock synchronous serial interface circuit comprising: A clock synchronous serial interface circuit provided in the slave device of the system that transmits a serial clock from the master device to the slave device and transmits and receives serial data including address information and data information of the slave device by the serial clock. And
Based on a state of a predetermined bit of the serial data, a determination unit that determines a reception format of the serial data of the master device;
Transmitting means for transmitting the serial data in accordance with the reception format determined by the determining means;
A clock synchronous serial interface circuit comprising:   3. The clock synchronous serial interface circuit according to claim 2, wherein the transmission means can select a clock edge indicating a transmission timing of the serial data from the serial clock. A clock synchronous serial interface circuit provided in the slave device of the system that transmits a serial clock from the master device to the slave device and transmits and receives serial data including address information and data information of the slave device by the serial clock. And
When the address information is larger than the number of bits constituting the address space of the slave device, the data information is stored in an area constituting the shared address inside the slave device based on the bit state of the address information serving as a remainder. A clock synchronous serial interface circuit comprising a writing means for simultaneously writing A clock synchronous serial interface circuit provided in the slave device of the system that transmits a serial clock from the master device to the slave device and transmits and receives serial data including address information and data information of the slave device by the serial clock. And
Obtaining means for obtaining two signals other than the serial clock and the serial data from the master device;
Determining means for determining whether to continuously transfer the data information sent from the master device based on a combination of logic levels of the two signals acquired by the acquiring means;
An update means for updating an address in the slave device in synchronization with a predetermined counter value generated by the serial clock when it is determined by the determination means to be continuously transferred;
A clock synchronous serial interface circuit comprising: A clock synchronous serial interface circuit provided in the slave device of the system that transmits a serial clock from the master device to the slave device and transmits and receives serial data including address information and data information of the slave device by the serial clock. And
Obtaining means for obtaining two signals other than the serial clock and the serial data from the master device;
Generating means for generating a control clock for controlling the write timing of the serial data sent from the master device based on the two signals acquired by the acquiring means;
Detecting means for detecting abnormal states of the serial clock and the two signals based on the state of the control clock;
When detecting an abnormality by the detection means, a stop means for stopping the transmission / reception operation of the serial data with the master device,
In the case where an abnormality is detected by the detection means, an informing means for informing the abnormal state;
A clock synchronous serial interface circuit comprising:

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