JP2012168773A - Bus system and access control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus system capable of suppressing deterioration in a bus utilization ratio even in the case that access is made from each bus master to a bus slave through a plurality of buses.SOLUTION: The bus system relating to the present invention is a bus system which controls access made from a plurality of bus masters 1_1 to 1_4 to at least one bus slave 5 via a plurality of buses 2_1 to 2_3. Each of the buses 2_1 to 2_3 includes an arbitration part 8 for arbitrating a plurality of access requests 16 and 17 inputted from a preceding state and outputting an access request selected by the arbitration to the next stage. The arbitration part 8 updates permissible waiting time information included in an access request 29 to be outputted to the next stage by subtracting a time when the access requests 16 and 17 wait in the buses.

Description

  The present invention relates to a bus system and an access control method, and more particularly to a bus system and an access control method for controlling access from a plurality of bus masters to at least one bus slave.

  In a semiconductor integrated circuit, a bus is used to efficiently communicate information between functional blocks. In general, a circuit using such a bus is used when a plurality of bus masters that transmit access requests, a bus slave that is accessed by the plurality of bus masters, and an access request conflict occurs between the plurality of bus masters. And an arbitration circuit that arbitrates the access request.

  2. Description of the Related Art In recent years, in a semiconductor integrated circuit bus system, functional blocks for processing various applications have increased as the system becomes larger. Accordingly, the necessity of connecting a large number of bus masters and bus slaves has increased, and a configuration having a plurality of buses has become mainstream. However, since the specifications of each bus are different for each functional block, it is difficult for the buses to access each other. In addition, in the transfer via a plurality of buses, there is an increasing need to improve the transfer efficiency of bus access in order to prevent program malfunctions and secure real-time processing.

  Patent Document 1 discloses a technique related to an access control device that arbitrates access requests to a bus slave by a plurality of bus masters. FIG. 8 is a block diagram showing the configuration of the access control device disclosed in Patent Document 1. In FIG. As shown in FIG. 8, the access control device disclosed in Patent Document 1 includes bus slaves BS0 and BS1, bus masters BM0 and BM1 that access the bus slaves BS0 and BS1, and bus masters BM0 and BM1. An access arbitration circuit AC that arbitrates access requests to the bus slaves BS0 and BS1 and a memory circuit MEM are provided. The bus masters BM0 and BM1 access the bus slaves BS0 and BS1 using a common bus. The bus masters BM0 and BM1 are, for example, CPUs or DMA controllers, and the bus slaves BS0, BS1 are, for example, memories, UARTs, or DRAM controllers.

  FIG. 9 is a block diagram illustrating a configuration of the memory circuit MEM and the access arbitration circuit AC included in the access control device disclosed in Patent Document 1. As shown in FIG. 9, the memory circuit MEM includes registers REG0 and REG1, and the access arbitration circuit AC includes an allowable waiting time update circuit AWC and an access request reception circuit ARR. The registers REG0 and REG1 store allowable waiting time information AWI0 and AWI1 output from the bus master BM0, respectively. The bus master BM0 can rewrite the allowable waiting time information AWI0 in the register REG0 and the allowable waiting time information AWI1 in the register REG1, and controls their contents.

  The allowable waiting time update circuit AWC includes counters CT0 and CT1, and updates the allowable waiting time of the access request of each bus master BM0 and BM1 based on the allowable waiting time information AWI0 and AWI1. Here, the allowable waiting time is an allowable time until an access request for a bus slave issued from the bus master is accepted. For example, if the allowable waiting time at a certain time is 100 μs, the bus master access request may be accepted within 100 μs thereafter. Therefore, the allowable waiting time becomes smaller with the lapse of time from when an access request is output until it is accepted.

  The allowable waiting time information AWI0 is time information for determining the allowable waiting time of the access request when the access request is issued from the bus master BM0. The allowable waiting time information AWI1 is time information for determining an allowable waiting time of the access request when the access request is issued from the bus master BM1.

The access request acceptance circuit ARR includes a comparator COM, a request selector RQS, and a control signal selector CSS. When the access requests of the bus masters BM0 and BM1 compete, the access request acceptance circuit ARR compares the allowable waiting times of the bus masters BM0 and BM1 updated by the allowable waiting time update circuit AWC, and based on the comparison result, Arbitrate access requests.

  The counter CT0 receives the allowable waiting time information AWI0 output from the register REG0, the access request signal RQ0 output from the bus master BM0, and the grant signal GRT0 output from the request selector RQS. On the other hand, the counter CT1 receives the allowable waiting time information AWI1 output from the register REG1, the access request signal RQ1 output from the bus master BM1, and the grant signal GRT1 output from the request selector RQS. The counters CT0 and CT1 count down the count value for each clock input, that is, for each rising edge of the system clock CLK based on a system clock CLK (not shown).

  The bus master BM0 outputs an access request to the bus slaves BS0 and BS1 by setting the access request signal RQ0 to “1”. The bus master BM1 outputs an access request to the bus slaves BS0 and BS1 by setting the access request signal RQ1 to “1”.

  The comparator COM of the access request acceptance circuit ARR compares the counter output value COUT0 from the counter CT0 with the counter output value COUT1 from the counter CT1, and based on the comparison result, which of the bus masters BM0 and BM1 is accessed. A priority value PRV indicating whether or not priority is given to request acceptance is generated and output. The request selector RQS receives the access request signal RQ0 from the bus master BM0, the access request signal RQ1 from the bus master BM1, the priority value PRV from the comparator COM, and the grant signal GRT10, and based on these signals Grant signals GRT0 and GRT1 are generated and output. When the grant signal GRT0 is “1”, the access request of the bus master BM0 is accepted, and when the grant signal GRT1 is “1”, the access request of the bus master BM1 is accepted.

  Based on the grant signals GRT0 and GRT1 from the request selector RQS, the control signal selector CSS outputs either the control signal CNT0 output from the bus master BM0 or the control signal CNT1 output from the bus master BM1 as the control signal CNT10. . As a result, either one of the access requests from the bus masters BM0 and BM1 is accepted. The control signal selector CSS also outputs an access request signal RQ10. The control signals CNT0 and CNT1 are signals for controlling the bus slaves BS0 and BS1 and include a write data signal, an address signal, a read signal, a write signal, and the like, respectively.

  The access control device disclosed in Patent Document 1 shown in FIG. 8 is further provided with an address decoder AD, an AND circuit 10, and a read selector RS. When the access request signal RQ10 from the control signal selector CSS indicates “1”, the address decoder AD decodes the higher address signal among the address signals included in the control signal CNT10 to generate chip select signals CS0 and CS1. Output.

  The chip select signal CS0 is input to the bus slave BS0. When the signal is “1”, the bus slave BS0 is selected. On the other hand, the chip select signal CS1 is input to the bus slave BS1, and when the signal is “1”, the bus slave BS1 is selected. Then, signals other than the upper address signal included in the control signal CNT10 are input to the bus slaves BS0 and BS1.

  The bus slave BS0 outputs a grant signal GRT20 based on its own operating state, and the bus slave BS1 also outputs a grant signal GRT21 based on its own operating state. For example, the bus slaves BS0 and BS1 set the grant signals GRT20 and GRT21 to “0” when being accessed from the bus masters BM0 and BM1 or performing an initial operation, and during the set period, an access request is made. Do not accept.

  The AND circuit 10 calculates the logical product of the grant signals GRT20 and GRT21 and outputs the result to the request selector RQS as the grant signal GRT10. Therefore, when the grant signal GRT10 indicates “0”, access to both the bus slaves BS0 and BS1 is prohibited.

  In the access control device disclosed in Patent Document 1, the bus masters BM0 and BM1 use a bundle of signal lines between the access arbitration circuit AC and the bus slaves BS0 and BS1 as a common bus, and use the common bus. To access the bus slaves BS0 and BS1.

  The read selector RS also outputs one of the read data signals RDD20 and RDD21 output from the bus slaves BS0 and BS1 based on the control signal CNTS output from the address decoder AD and indicating the bus slave being accessed. The data is output to the bus masters BM0 and BM1 as RDD10.

  As described above, the access control device disclosed in Patent Document 1 compares the allowable waiting times in the bus masters BM0 and BM1, and accepts an access request from either of the bus masters BM0 and BM1 based on the comparison result. It is done. Therefore, it is possible to grant an access right to a bus master with a small allowable waiting time when access requests compete. As a result, the time (access latency) required for accessing the bus slaves BS0 and BS1 of each bus master BM0 and BM1 is within an allowable range without sacrificing data transfer performance between the bus masters BM0 and BM1 and the bus slaves BS0 and BS1. Can fit.

  Furthermore, since the allowable waiting time information AWI0 and AWI1 are stored in the rewritable storage circuit MEM, the allowable waiting time information AWI0 and AWI1 can be updated according to the system specifications and the operating state of the system. Therefore, optimum data transfer performance can be realized between the bus masters BM0 and BM1 and the bus slaves BS0 and BS1. Thereby, for example, even when each bus master BM0, BM1 handles a large amount of data such as moving image data in real time, it is possible to prevent a system failure such as an image display being disabled.

  Patent Document 2 discloses a bus arbitration circuit that can shorten the time required to obtain a bus use permission at the time of bus arbitration. In the bus arbitration circuit disclosed in Patent Document 2, when bus use requests from a plurality of bus masters compete, the bus master of the bus master that accesses the bus slave having a short response time has the highest priority. Low bus master latency can be reduced.

JP 2006-40019 A JP 2004-78508 A

  In the access control device according to Patent Document 1 shown in FIGS. 8 and 9, the configuration in which the access arbitration circuit AC, the address decoder AD, the read selector RS, and the AND circuit 10 are combined is a general bus configuration. Therefore, the access control device according to Patent Document 1 includes the general bus configuration and the memory circuit MEM. At this time, the connection line between the bus master BM0 and the access arbitration circuit AC in FIG. 8 corresponds to a bundle of the access request signal RQ0, the control signal CNT0, and the grant signal GRT0 in FIG.

  FIG. 10 is a diagram for explaining the problem of the present invention, and shows a bus system in which a plurality of buses (access control devices) disclosed in Patent Document 1 are connected. The bus system shown in FIG. 10 includes bus masters 101 to 104, a bus slave 105, storage circuits 111, 121, 131, and buses 112, 122, 132. Each of the buses 112, 122, and 132 includes a general bus (that is, a configuration in which the access arbitration circuit AC, the address decoder AD, the read selector RS, and the AND circuit 10 disclosed in Patent Document 1 are combined). Each of the storage circuits 111, 121, and 131 illustrated in FIG. 10 corresponds to the storage circuit MEM included in the access control device according to Patent Document 1.

  In the bus system shown in FIG. 10, the bus master 101 transfers the waiting time (hereinafter, the allowable waiting time) that the bus masters 101 to 104 can accept to the storage circuits 111, 121, and 131 corresponding to the buses 112, 122, and 132. Write). That is, the allowable waiting time of the bus master 101 and the bus master 102 is written in the storage circuit 111 corresponding to the bus 112. The allowable waiting times of the bus master 101, the bus master 102, and the bus master 103 are written in the storage circuit 121 corresponding to the bus 122. In the storage circuit 131 corresponding to the bus 132, the allowable waiting time of the bus master 101, the bus master 102, the bus master 103, and the bus master 104 is written. At this time, for example, values obtained by dividing the allowable waiting time from the bus master 101 to the bus slave 105 into three equal parts are written in the storage circuits 111, 121, and 131, respectively.

  The bus 112 receives the access request 106_1 from the bus master 101 and the access request 106_2 from the bus master 102, and arbitrates these access requests 106_1 and 106_2 based on the allowable waiting time stored in the storage circuit 111. The access request 107_1 is output to the bus 122. The bus 122 receives the access request 107_1 output from the bus 112 and the access request 106_3 from the bus master 103, and arbitrates these access requests 107_1 and 106_3 based on the allowable waiting time stored in the storage circuit 121. The arbitrated access request 107_2 is output to the bus 132. The bus 132 receives the access request 107_2 output from the bus 122 and the access request 106_4 from the bus master 104, and arbitrates these access requests 107_2 and 106_4 based on the allowable waiting time stored in the storage circuit 131. The arbitrated access request 107_3 is output to the bus slave 105.

  However, in the bus system shown in FIG. 10, the allowable waiting time written in each of the storage circuits 111, 121, 131 is fixed to a predetermined value as described above. That is, for example, each storage circuit 111, 121, 131 is written with a value (for example, a value obtained by dividing the allowable waiting time) from the bus master 101 to the bus slave 105, and each of these values is written. It is an independent value for each bus.

  For this reason, for example, even if the access request 106_1 of the bus master 101 is output as the access request 107_1 after the arbitration earlier than the allowable waiting time stored in the storage circuit 111 in the bus 112, the bus 122 has an excess in the bus 112. The access request 107_1 and the access request 106_3 are arbitrated using the allowable waiting time (fixed value) stored in the storage circuit 121 without considering the allowable waiting time.

  In this way, in the bus system shown in FIG. 10, the allowable waiting time written in each storage circuit 111, 121, 131 is fixed to a predetermined value, so that a plurality of buses from each bus master 101 to 104 to bus slave 105 can be obtained. When accessing via the lines 112, 122, and 132, there is a problem that the use efficiency of these buses is lowered.

  A bus system according to the present invention is a bus system that controls access from a plurality of bus masters to at least one bus slave via a plurality of buses, each of the buses receiving a plurality of access requests input from a preceding stage. And an arbitration unit that outputs the access request selected by the arbitration to the next stage, and the arbitration unit outputs the access request that is output to the next stage by subtracting the time that the access request waited on the bus. Update the allowable waiting time information included in the request.

  In the bus system according to the present invention, in each bus, a plurality of access requests input to each bus are arbitrated and the allowable waiting time of the access request is updated. That is, in the bus system according to the present invention, the allowable waiting time can be carried over to the next bus when passing through a plurality of buses, so that the bus use efficiency can be improved.

  An access control method according to the present invention is an access control method for controlling access from a plurality of bus masters to at least one bus slave via a plurality of buses, wherein each of the buses is input from a plurality of stages. The access request is arbitrated, the access request selected by the arbitration is output to the next stage, and the access request output to the next stage is subtracted from the time spent waiting on the bus to be output to the next stage. The allowable waiting time information included in is updated.

  In the access control method according to the present invention, in each bus, a plurality of access requests input to each bus are arbitrated and the allowable waiting time of the access request is updated. That is, in the access control method according to the present invention, the allowable waiting time can be carried over to the next bus when passing through a plurality of buses, so that the bus use efficiency can be improved.

  According to the present invention, it is possible to provide a bus system and an access control method capable of suppressing a decrease in bus use efficiency even when each bus master accesses a bus slave via a plurality of buses.

1 is a block diagram showing a bus system according to a first exemplary embodiment; FIG. 3 is a block diagram illustrating a configuration of each bus included in the bus system according to the first embodiment. FIG. 6 is a block diagram illustrating a configuration of each bus included in a bus system according to a second exemplary embodiment. 6 is a timing chart showing the operation of each bus provided in the bus system according to the second exemplary embodiment; 10 is a flowchart showing the operation of each bus provided in the bus system according to the second exemplary embodiment; FIG. 10 is a block diagram illustrating a configuration of each bus included in a bus system according to a third embodiment. 10 is a timing chart showing the operation of each bus provided in the bus system according to the third exemplary embodiment; 1 is a block diagram showing a configuration of an access control device disclosed in Patent Document 1. FIG. 10 is a block diagram illustrating a configuration of a storage circuit and an access arbitration circuit included in an access control device disclosed in Patent Document 1. FIG. It is a figure for demonstrating the subject of this invention.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of the bus system according to the first embodiment. The bus system according to the present embodiment shown in FIG. 1 includes bus masters 1_1 to 1_4, buses 2_1 to 2_3, and a bus slave 5. The bus system according to the present embodiment is a bus system that accesses at least one bus slave 5 from a plurality of bus masters 1_1 to 1_4 via a plurality of buses 2_1 to 2_3.

  The bus 2_1 receives the access request 6_1 from the bus master 1_1 and the access request 6_2 from the bus master 1_2, arbitrates these access requests 6_1 and 6_2, and outputs the arbitrated access request 7_1 to the bus 2_2. The bus 2_2 receives the access request 7_1 output from the bus 2_1 and the access request 6_3 from the bus master 1_3, arbitrates these access requests 7_1 and 6_3, and outputs the arbitrated access request 7_2 to the bus 2_3. The bus 2_3 receives the access request 7_2 output from the bus 2_2 and the access request 6_4 from the bus master 1_4, arbitrates these access requests 7_2 and 6_4, and outputs the access request 7_3 after arbitration to the bus slave 5.

  In FIG. 1, arrows between bus masters and buses, between buses, and between buses and bus slaves are bidirectional arrows. This indicates that a response signal is transmitted from the bus slave 5 to the bus masters 1_1 to 1_4. In this embodiment, since arbitration of access requests is described, each arrow is expressed as an access request 6_1 or the like.

  Moreover, although the case where the bus system shown in FIG. 1 includes four bus masters is illustrated, the number of bus masters can be arbitrarily determined. Moreover, although the case where the bus system shown in FIG. 1 includes one bus slave is illustrated, the number of bus slaves can also be arbitrarily determined. Furthermore, in the bus system shown in FIG. 1, the case where each of the buses 2_1 to 2_3 arbitrates two access requests is illustrated, but the number of access requests that each bus arbitrates may be two or more.

  FIG. 2 is a block diagram showing a configuration of each bus provided in the bus system according to the present embodiment. A bus 2 shown in FIG. The arbitration unit 8 includes access request separation units 12 and 13, a request control unit 14, and an access request coupling unit 15. These components are supplied with a clock signal from a clock supply source (not shown), and these components operate in synchronization with the clock signal.

  The bus 2 shown in FIG. 2 corresponds to the buses 2_1 to 2_3 shown in FIG. If the bus 2 shown in FIG. 2 is the bus 2_1 shown in FIG. 1, the access requests 16 and 17 from the previous stage and the access request 29 to the next stage inputted to the bus 2 shown in FIG. These correspond to the access requests 6_1, 6_2, and 7_1 shown in FIG. When the bus 2 shown in FIG. 2 is the bus 2_2 shown in FIG. 1, the access requests 16 and 17 from the previous stage and the access request 29 to the next stage inputted to the bus 2 shown in FIG. 1 corresponds to the access requests 7_1, 6_3, and 7_2 shown in FIG. When the bus 2 shown in FIG. 2 is the bus 2_3 shown in FIG. 1, the access requests 16 and 17 from the previous stage and the access request 29 to the next stage inputted to the bus 2 shown in FIG. 1 corresponds to the access requests 7_2, 6_4, and 7_3 shown in FIG.

  The access request separation unit 12 receives the access request 16 from the previous stage and separates the access request signal 21 and the allowable waiting time information 22 included in the access request 16. Then, the access request separation unit 12 outputs the separated access request signal 21 and the allowable waiting time information 22 to the request control unit 14, respectively.

  The access request separation unit 13 receives the access request 17 from the previous stage and separates the access request signal 23 and the allowable waiting time information 24 included in the access request 17. Then, the access request separation unit 13 outputs the separated access request signal 23 and the allowable waiting time information 24 to the request control unit 14, respectively.

  The access request separators 12 and 13 are provided corresponding to the access requests 16 and 17 from the previous stage input to the bus 2. In the example shown in FIG. 2, since there are two access requests from the previous stage, the bus 2 has two access request separation units. However, when the number of access requests from the previous stage is larger than this, A number of access request separation units equal to the number of access requests can be provided. For example, when the access request from the previous stage is already separated into the access request signal and the allowable waiting time information, the access request separation units 12 and 13 may be omitted as appropriate.

  The request control unit 14 inputs the access request signal 21 and the allowable waiting time information 22 separated by the access request separating unit 12, and the access request signal 23 and the acceptable waiting time information 24 separated by the access request separating unit 13, The access request signals 21 and 23 are arbitrated using the allowable waiting time information 22 and 24, and the access request signal 26 selected by the arbitration is output.

  In addition, the request control unit 14 updates the input allowable waiting time information 22 and 24. The updated allowable waiting time information 27 and 28 is output to the access request combining unit 15. Here, the updated allowable waiting time information 27 corresponds to the updated allowable waiting time information of the access request signal 21, and the updated allowable waiting time information 28 corresponds to the updated allowable waiting time information of the access request signal 23. It corresponds.

  The allowable waiting time information can be updated, for example, by subtracting the waiting time in the bus 2 of the selected access request signal 26. Specifically, the allowable waiting time information of the selected access request signal 26 is obtained by subtracting the time that the selected access request signal 26 waits on the bus 2 from the allowable waiting time information at the time of input to the bus 2. Can be updated.

  In addition, the request control unit 14 outputs access request reception information 25 indicating which access request signal is selected from the access request signal 21 and the access request signal 23 to the access request combining unit 15.

  The access request combining unit 15 combines the selected access request signal 26 and the updated allowable waiting time information 27 and 28 output from the request control unit 14, and accesses the combined access request to the next stage. Output as request 29. Specifically, when the access request signal 21 is selected in the request control unit 14, the access request combining unit 15 includes the selected access request signal 26 (that is, the access request signal 21) and updated allowable waiting time information. 27. Further, when the access request signal 23 is selected in the request control unit 14, the access request combining unit 15 displays the selected access request signal 26 (that is, the access request signal 23) and the updated allowable waiting time information 28. Join.

  At this time, the access request combining unit 15 receives the access request reception information 25 output from the request control unit 14, and which access request signal is selected from the access request signal 21 and the access request signal 23. Can know. Based on the access request reception information 25, the access request combining unit 15 combines the updated allowable waiting time information (27 or 28) and the selected access request signal 26.

  For example, when the access request signal and the allowable waiting time information can be output separately as an access request to the next stage, the access request combining unit 15 can be omitted as appropriate. That is, in the bus system according to the present embodiment, the access requests 6_1 to 6_4 from the bus masters 1_1 to 1_4 and the access requests 7_1 to 7_3 from the buses 2_1 to 2_3 are separated into access request signals and allowable waiting time information, respectively. Therefore, the access request separating units 12 and 13 and the access request combining unit 15 can be omitted.

  In the bus system shown in FIG. 10, the allowable waiting time written in each of the storage circuits 111, 121, 131 is fixed to a predetermined value. For this reason, for example, even if the access request 106_1 of the bus master 101 is output earlier than the allowable waiting time stored in the storage circuit 111 in the bus 112, the excessive allowable waiting time in the bus 112 is considered in the bus 122. Instead, the access request 107_1 and the access request 106_3 are arbitrated using the allowable waiting time (fixed value) stored in the storage circuit 121. For this reason, the bus system shown in FIG. 10 has a problem that the use efficiency of the bus decreases.

  Specifically, for example, in the bus system shown in FIG. 10, the allowable waiting time from the bus master 101 to the bus slave 105 is 7 cycles, the allowable waiting time from the bus master 104 to the bus slave 105 is 3 cycles, The waiting time at 122 and 132 is 2 cycles. Here, it is assumed that the allowable waiting time (7 cycles) from the bus master 101 to the bus slave 105 is divided into three, and 2 cycles are allocated to the buses 112 and 122 and 3 cycles are allocated to the bus 132. The output from the bus master 101 and the input to the bus 112 are the same cycle, the output from the bus 112 and the input to the bus 122 are the same cycle, and the output from the bus 122 and the input to the bus 132 are the same. In the cycle, the output from the bus 132 and the input to the bus slave 105 are performed in the same cycle. The same applies to other bus masters.

  For example, it is assumed that the bus master 101 and the bus master 104 transfer simultaneously on the bus 132. At this time, the allowable waiting times of the bus master 101 and the bus master 104 are the same three cycles. Therefore, when the bus master 101 preferentially uses the bus 132, the transfer cycle from the bus master 104 to the bus slave 105 becomes four cycles, which exceeds the allowable waiting time (3 cycles) of the bus master 104.

  On the other hand, the transfer cycle from the bus master 101 to the bus slave 105 is 4 cycles, so that 3 cycles can be provided for 7 cycles, which is the entire allowable waiting time. As a result, the transfer from the bus master 101 to the bus slave 105 is a transfer with a margin, while the transfer from the bus master 104 to the bus slave 105 is a transfer that exceeds the allowable waiting time. As described above, the bus system shown in FIG. 10 has a problem that the use efficiency of the bus is lowered.

  On the other hand, in the bus system according to the present embodiment, in each of the buses 2_1 to 2_3, a plurality of access requests input to each bus are arbitrated and the allowable waiting time of the access request is updated. That is, in the bus system according to the present embodiment, the allowable waiting time can be carried over to the next bus when passing through a plurality of buses, so that the bus use efficiency can be improved.

  When the bus system according to the present embodiment is applied to the above example, the allowable waiting time of the bus 132 between the bus master 101 and the bus slave 105 can be increased by the amount of allowance in the allowable waiting time. (Can carry over). By increasing the allowable waiting time of the bus 132 in this way, the use of the bus 132 of the bus master 104 can be prioritized, and the access request can be transferred from the bus master 104 to the bus slave 105 within the allowable waiting time.

  As described above, according to the invention according to the present embodiment, even when each bus master accesses a bus slave via a plurality of buses, it is possible to suppress a decrease in bus use efficiency. A system and access control method can be provided.

Embodiment 2
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration of each bus provided in the bus system according to the second exemplary embodiment of the present invention. Also in this embodiment, the bus 2 shown in FIG. 3 corresponds to each of the buses 2_1 to 2_3 of the bus system shown in FIG. The bus system according to the present embodiment shows a more detailed configuration of the bus system according to the first embodiment. In addition, the same code | symbol is attached | subjected about the component same as Embodiment 1, and the overlapping description is abbreviate | omitted suitably.

  The bus 2 shown in FIG. 3 includes an arbitration unit 8. The arbitration unit 8 includes access request separation units 12 and 13, a request control unit 14, and an access request coupling unit 15. These components are supplied with a clock signal from a clock supply source (not shown), and these components operate in synchronization with the clock signal. Since the configurations and operations of the access request separating units 12 and 13 and the access request combining unit 15 are the same as those in the first embodiment, a duplicate description is omitted.

  The request control unit 14 includes allowable waiting time calculation units 45 and 48, top priority determination units 46 and 49, a counter 50, and an access request signal selection unit 51. The counter 50 generates a count value 67 according to the clock signal. The allowable waiting time calculation unit 45 and the highest priority determination unit 46 are provided corresponding to the access request 16 from the previous stage, and perform various processes using the allowable waiting time information 22 separated by the access request separation unit 12. carry out. The allowable waiting time calculation unit 48 and the highest priority determination unit 49 are provided corresponding to the access request 17 from the previous stage, and perform various processes using the allowable waiting time information 24 separated by the access request separation unit 13. carry out.

  That is, a set of allowable waiting time calculation unit and top priority determination unit are provided corresponding to one access request. In the example shown in FIG. 2, since there are two access requests from the preceding stage, two sets of allowable waiting time calculation units and top priority determination units are provided, but the number of access requests from the preceding stage is larger than this. If there are many, a set of allowable waiting time calculation units and top priority determination units equal to the number of access requests are provided.

  The allowable waiting time calculation unit 45 receives the allowable waiting time information 22, generates a threshold value 68 using the allowable waiting time information 22, and outputs the generated threshold value 68 to the highest priority determination unit 46. Here, the threshold value 68 is a value used when determining whether or not the access request signal 21 should be given the highest priority when the access request signal 21 and the access request signal 23 are arbitrated. For example, the threshold 68 may be half of the allowable waiting time. In this case, when the waiting time of the access request signal 21 exceeds half of the allowable waiting time, the access request signal 21 can be preferentially transferred.

  In the bus system according to the present embodiment, the allowable waiting time calculation unit 45 can generate the threshold 68 using the count value 67 of the counter 50. For example, when the allowable waiting time information 22 is 30 cycles (hereinafter, it may be indicated only by a number such as “30”), the allowable waiting time calculation unit 45 is half of the allowable waiting time “30”. A certain “15” can be set as the target waiting time. If the count value 67 in this case is “20”, the threshold value 68 can be set to 20 + 15 = 35. The counter 50 increments the count value 67 at a constant cycle.

  The highest priority determination unit 46 determines whether to output the access request signal 21 with the highest priority based on the threshold 68. Specifically, the threshold value 68 generated by the allowable waiting time calculation unit 45 is compared with the count value 67 of the counter 50, and when the count value 67 exceeds the threshold value 68, the access request signal selection unit 51 receives the maximum value. A priority signal 70 is output.

  Similarly, the allowable waiting time calculator 48 receives the allowable waiting time information 24, generates a threshold 69 using the allowable waiting time information 24, and outputs the generated threshold 69 to the highest priority determination unit 49. Here, the threshold 69 is a value used when determining whether or not the access request signal 23 should be given the highest priority at the time of arbitration between the access request signal 21 and the access request signal 23. For example, the threshold 69 may be half of the allowable waiting time. In this case, when the waiting time of the access request signal 23 exceeds half of the allowable waiting time, the access request signal 23 can be preferentially transferred.

  In the bus system according to the present embodiment, the allowable waiting time calculation unit 48 can generate the threshold 69 using the count value 67 of the counter 50. For example, when the allowable waiting time information 24 is “38”, the allowable waiting time calculation unit 48 can set “19” which is half of the allowable waiting time “38” as the target waiting time. If the count value 67 in this case is “20”, the threshold 69 can be 20 + 19 = 39.

  The highest priority determination unit 49 determines whether to output the access request signal 23 with the highest priority based on the threshold 69. Specifically, the threshold 69 generated by the allowable waiting time calculation unit 48 is compared with the count value 67 of the counter 50, and when the count value 67 exceeds the threshold 69, the access request signal selection unit 51 receives the maximum value. A priority signal 71 is output.

  The access request signal selection unit 51 includes an access request signal 21 separated by the access request separation unit 12, an access request signal 23 separated by the access request separation unit 13, a top priority signal 70 output from the top priority determination unit 46, The highest priority signal 71 output from the highest priority determination unit 49 is input. Then, the access request signal having the higher priority among the access request signals 21 and 23 based on the determination result of the highest priority determination units 46 and 49, that is, the highest priority signals 70 and 71 is used as the selected access request signal 26. The data is output to the access request combining unit 15.

  For example, when the highest priority signal 70 is at a high level and the highest priority signal 71 is at a low level, the access request signal 21 is output to the access request combining unit 15 as the selected access request signal 26. When the highest priority signal 70 is at a low level and the highest priority signal 71 is at a high level, the access request signal 23 is output to the access request combining unit 15 as the selected access request signal 26.

  When the highest priority signals 70 and 71 are both low level or high level, the access request signal selector 51 operates as a general arbitration circuit, and arbitrates the access request signals 21 and 23. Also in this case, the arbitrated access request signal is output to the access request combining unit 15 as the selected access request signal 26.

  Further, the access request signal selection unit 51 outputs the access request reception information 25 to the allowable waiting time calculation units 45 and 48 and the access request combining unit 15. The access request acceptance information 25 is information indicating which access request signal of the access request signals 21 and 23 is selected. The access request acceptance information 25 is output at the same timing as the timing at which the selected access request signal 26 is output, for example.

  The allowable waiting time calculation units 45 and 48 determine that the selected access request is based on the allowable waiting time when the access requests 16 and 17 corresponding to the access request signals 21 and 23 selected by the access request signal selection unit 51 are input. The allowable waiting time information of the selected access request is updated by subtracting the waiting time in 2.

  The allowable waiting time calculation unit 45 is updated using the allowable waiting time information 22, the count value 67, and the threshold 68 at the timing when the access request reception information 25 indicating that the access request signal 21 is selected is supplied. The allowable waiting time information 27 is generated, and the updated allowable waiting time information 27 is output to the access request combining unit 15. For example, the allowable waiting time calculation unit 45 sets the allowable waiting time information 22 to “30”, the target waiting time to “15” which is half of the allowable waiting time “30”, the threshold 68 to “35”, and the access request reception information 25. Assuming that the count value 67 at the timing at which is supplied is “40”, “10” (that is, 15− (40−35) = 10) is output as the updated allowable waiting time information 27.

  Similarly, the allowable waiting time calculation unit 48 uses the allowable waiting time information 24, the count value 67, and the threshold value 69 at the timing when the access request reception information 25 indicating that the access request signal 23 is selected is supplied. The updated allowable waiting time information 28 is generated, and the updated allowable waiting time information 28 is output to the access request combining unit 15.

  Note that the allowable waiting time calculation unit 45 does not indicate that the access request reception information 25 indicates that the access request signal 21 is selected as the selected access request signal 26 (that is, another access request signal is selected). If it is, the updated allowable waiting time information 27 is not generated. Similarly, when the access request reception information 25 does not indicate that the access request signal 23 is selected as the selected access request signal 26 (that is, another access request signal is selected). If this is the case, the updated allowable waiting time information 28 is not generated.

  The access request combining unit 15 receives the access request reception information 25 and the selected access request signal 26 output from the access request signal selection unit 51 and the updated allowable waiting time information 27 and 28. When the access request reception information 25 indicates that the access request signal 21 is selected, the access request combining unit 15 determines that the selected access request signal 26 (that is, the access request signal 21) and the updated allowable waiting time. The information 27 is combined, and the combined access request is output as an access request 29 to the next stage. When the access request acceptance information 25 indicates that the access request signal 23 is selected, the access request combining unit 15 determines that the selected access request signal 26 (that is, the access request signal 23) and the updated allowable waiting time. The information 28 is combined, and the combined access request is output as an access request 29 to the next stage.

  Next, the operation of the bus system according to the present embodiment will be described. FIG. 4 is a timing chart showing the operation of the bus 2 provided in the bus system according to the present embodiment.

  As shown in FIG. 4, at T1, the access request 16 from the previous stage and the access request 17 from the previous stage are supplied to the access request separation unit 12 and the access request separation unit 13, respectively. In addition, the access request separator 12 and the access request separator 13 output the access request signal 21 and the access request signal 23 to the access request signal selector 51, respectively. Further, the access request separation unit 12 outputs “30” as the allowable wait time information 22 to the allowable wait time calculation unit 45, and the access request separation unit 13 outputs the allowable wait time information 24 to the allowable wait time calculation unit 48. 38 "is output.

  At T <b> 2, the allowable waiting time calculation unit 45 outputs a threshold value 68 to the highest priority determination unit 46. Here, since the allowable waiting time information 22 is “30”, the allowable waiting time calculation unit 45 sets “15” which is half of the allowable waiting time “30” as the target waiting time. Since the count value 67 is “20”, the threshold value 68 is 20 + 15 = 35. Further, the allowable waiting time calculation unit 48 outputs a threshold value 69 to the highest priority determination unit 49. Here, since the allowable waiting time information 24 is “38”, the allowable waiting time calculation unit 48 sets “19” which is half of the allowable waiting time “38” as the target waiting time. Since the count value 67 is “20”, the threshold 69 is 20 + 19 = 39.

  Thereafter, the highest priority determination units 46 and 49 continue to compare the threshold values 68 and 69 with the count value 67, respectively. At T 11, the highest priority determination unit 46 outputs the highest priority signal 70 to the access request signal selection unit 51 because “36” that is the count value 67 has exceeded “35” that is the threshold 68.

  At T14, the access request reception information 25 and the selected access request signal 26 are output from the access request signal selection unit 51. That is, the access request signal 21 is output as the selected access request signal 26. Further, access request acceptance information 25 indicating that the selected access request signal 26 is the access request signal 21 is output.

  Further, at T <b> 14, the allowable waiting time calculating unit 45 outputs the updated allowable waiting time information 27 to the access request combining unit 15. Here, the allowable waiting time calculator 45 is “30” as the allowable waiting time information 22, “15” as the target waiting time (half of the allowable waiting time “30”), “35” as the threshold 68, and access. The updated allowable waiting time information 27 is calculated using “40” which is the count value 67 at the timing when the request acceptance information 25 is supplied. In this case, “10” (that is, 15− (40−35) = 10) is output as the updated allowable waiting time information 27.

  At T15, the access request combining unit 15 outputs an access request 29 to the next stage in which the access request signal 21 and the allowable waiting time information 27 are combined. Note that the access request 17 from the previous stage is in a waiting state from T1 to T15.

  By such an operation, it is possible to update the allowable waiting time of access requests together with arbitration of a plurality of access requests.

  Next, an access control method in the bus system according to the present embodiment will be described with reference to the flowchart shown in FIG.

  When the bus 2 receives the access requests 16 and 17 from the previous stage, the allowable waiting time calculators 45 and 48 calculate thresholds 68 and 69 (step S1). Here, the thresholds 68 and 69 are values used to determine an access request signal to be output with the highest priority when the access request signal 21 and the access request signal 23 are arbitrated.

  Next, the highest priority determination units 46 and 49 compare the threshold values 68 and 69 with the count value 67, respectively (step S2). When the count value 67 is larger than the threshold value 68 (step S2: Yes), the priority of the access request signal 21 is set to the highest priority. On the other hand, when the count value 67 is larger than the threshold value 69 (step S2: Yes), the priority of the access request signal 23 is set to the highest priority. When the count value 67 is smaller than the threshold values 68 and 69 (step S2: No), the process moves to step S4 without determining the priority order.

  When the access request conflicts (that is, when both the access request signal 21 and the access request signal 23 are at the high level), the access request signal selection unit 51 permits the access request according to the priority order (Step S4: Yes). That is, when the highest priority signal 70 is at a high level and the highest priority signal 71 is at a low level, the access request signal 21 is output to the access request combining unit 15. Further, when the highest priority signal 70 is at the low level and the highest priority signal 71 is at the high level, the access request signal 23 is output to the access request combining unit 15.

  Further, the access request signal selector 51 determines that the access requests are in conflict and the highest priority access request has not been determined (that is, when the highest priority signals 70 and 71 are both at the low level, or the highest priority signal 70 , 71 are both at a high level), arbitration of the access request 21 and the access request 23 is performed as a general arbitration circuit, one access request is permitted, and the process proceeds to step S6 (step S4: Yes).

  Further, the access request signal selection unit 51 determines that the access request is not considered in the priority order when the access requests are not competing (that is, when only one of the access request signal 21 and the access request signal 23 is at a high level). Is permitted (step S4: Yes).

  On the other hand, when another bus master is using the bus, the access request signal selection unit 51 moves to step S5 without permitting the access request (step S4: No). The counter 50 increments the count value 67 (step S5). Then, it moves to step S2.

  When the access request is permitted in step S4, the access request combining unit 15 combines the access request signal and the allowable waiting time information and outputs it as an access request to the next stage (step S6).

  As described above, in the bus system according to the present embodiment, in each of the buses 2_1 to 2_3 illustrated in FIG. Has been updated. That is, in the bus system according to the present embodiment, the allowable waiting time can be carried over to the next bus when passing through a plurality of buses, so that the bus use efficiency can be improved.

  Next, the effect of the invention according to the present embodiment will be specifically described using the bus system shown in FIG. Similarly to the bus system shown in FIG. 10 described in the first embodiment, the allowable waiting time from the bus master 1_1 to the bus slave 5 is “7”, the allowable waiting time from the bus master 1_4 to the bus slave 5 is “3”, Further, it is assumed that the threshold for each bus is half of the allowable waiting time.

  If the access request 6_1 from the bus master 1_1 is used for two cycles on the bus 2_1, the remaining allowable waiting time is “5”. At this time, the bus 2_1 outputs an access request 7_1 to which “5”, which is the remaining allowable waiting time, is added to the bus 2_2. If the access request 7_1 from the bus 2_1 is used for one cycle in the bus 2_2, the remaining allowable waiting time is “4”. At this time, the bus 2_2 outputs to the bus 2_3 an access request 7_2 to which "4" that is the remaining allowable waiting time is added.

  In the bus 2_3, when the access request 7_2 and the access request 6_4 from the bus master 1_4 compete, the allowable waiting time of the access request 7_2 is “4”, so the threshold value is “2”. Further, since the allowable waiting time of the access request 6_4 of the bus master 1_4 is “3”, the threshold value is “1”. Therefore, the access request 6_4 of the bus master 1_4 is preferentially selected. As a result, the transfer cycle from the bus master 1_4 to the bus slave 5 is "2", and the transfer cycle from the bus master 1_1 to the bus slave 5 is "6". Thus, by using the bus system according to the present embodiment, it is possible to provide a bus system that can transfer an access request within an allowable waiting time without any bias.

  As described above, according to the invention according to the present embodiment, even when each bus master accesses a bus slave via a plurality of buses, it is possible to suppress a decrease in bus use efficiency. And an access control method can be provided.

Embodiment 3
Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of each bus provided in the bus system according to the third embodiment of the present invention. Also in this embodiment, the bus 3 shown in FIG. 6 corresponds to each of the buses 2_1 to 2_3 of the bus system shown in FIG. The bus system according to the present embodiment differs from the bus systems according to the first and second embodiments in that the bus 3 (arbitration unit 9) includes a remaining allowable waiting time return unit 80. Other than this, since it is the same as that of the bus system according to the first and second embodiments, the same components are denoted by the same reference numerals, and redundant description will be omitted as appropriate.

  The remaining allowable waiting time returning unit 80 illustrated in FIG. 6 has a function of returning the allowable waiting time information received by the bus slave 5 illustrated in FIG. 1 to the bus masters 1_1 to 1_4 as the transmission sources as remaining allowable waiting time information. The remaining allowable waiting time return unit 80 inputs the remaining allowable waiting time information 81 from the next stage and the access request 29 to the next stage, and the remaining allowable waiting time from the next stage according to the access request 29 to the next stage. The information 81 is output as the remaining allowable waiting time information 82 and 83 for the previous stage. Here, the access request 29 to the next stage includes information related to the transmission source bus master (that is, information related to the bus master connected to the bus slave 5). The remaining allowable waiting time return unit 80 can return the remaining allowable waiting time information to the transmission source bus master by using the information related to the transmission source bus master.

  If the bus 3 shown in FIG. 6 is the bus 2_3 shown in FIG. 1, the remaining allowable waiting time information 81 from the next stage shown in FIG. 6 is the remaining allowable waiting time information from the bus slave 5 shown in FIG. Corresponding to 7_3 (in this case, reference numeral 7_3 is the remaining allowable waiting time information output from the next stage to the previous stage. The same applies in this paragraph), and the remaining allowable waiting time information 82 to the previous stage shown in FIG. Corresponds to the remaining allowable waiting time information 7_2 output to the bus 2_2 shown in FIG. 1, and the remaining allowable waiting time information 83 to the previous stage shown in FIG. 6 is the remaining allowable waiting time information output to the bus master 1_4 shown in FIG. Corresponds to 6_4. When the bus 3 shown in FIG. 6 is the bus 2_2 shown in FIG. 1, the remaining allowable waiting time information 81 from the next stage shown in FIG. 6 is changed to the remaining allowable waiting time information 7_2 from the bus 2_3 shown in FIG. Correspondingly, the remaining allowable waiting time information 82 for the preceding stage shown in FIG. 6 corresponds to the remaining allowable waiting time information 7_1 output to the bus 2_1 shown in FIG. 1, and the remaining allowable waiting time information 83 for the preceding stage shown in FIG. Corresponds to the remaining allowable waiting time information 6_3 output to the bus master 1_3 shown in FIG. When the bus 3 shown in FIG. 6 is the bus 2_1 shown in FIG. 1, the remaining allowable waiting time information 81 from the next stage shown in FIG. 6 is changed to the remaining allowable waiting time information 7_1 from the bus 2_2 shown in FIG. Correspondingly, the remaining allowable waiting time information 82 for the preceding stage shown in FIG. 6 corresponds to the remaining allowable waiting time information 6_1 output to the bus master 1_1 shown in FIG. 1, and the remaining allowable waiting time information 83 for the preceding stage shown in FIG. Corresponds to the remaining allowable waiting time information 6_2 output to the bus master 1_2 shown in FIG.

  Next, the operation of the bus system according to the present embodiment will be described using the flowchart shown in FIG. Note that the operation of the bus system according to the present embodiment is the same as the operation of the bus system according to the second embodiment (see FIG. 4) until T15, and a duplicate description will be omitted.

  At T16, remaining allowable waiting time information 81 is output from the next stage. For example, when the bus 3 is the bus 2_3 in FIG. 1, at T16, the bus slave 5 extracts the allowable waiting time information from the received access request 7_3, and uses the allowable waiting time information as the remaining allowable waiting time information 81. Output to the remaining allowable waiting time return unit 80 of 2_3.

  In T17, the remaining allowable waiting time returning unit 80 specifies the transmission source bus master from the access request 29 to the next stage, and returns the remaining allowable waiting time information to the specified bus master. For example, when the bus 3 is the bus 2_3 in FIG. 1, at T17, the remaining allowable waiting time return unit 80 specifies the source bus master (for example, bus master 1_1) from the access request 29 to the next stage, and specifies In order to return the remaining allowable waiting time information to the bus master 1-1, the remaining allowable waiting time information 82 is output to the bus 2_2.

  Thereafter, the remaining allowable waiting time return unit 80 provided in the bus 2_2 specifies the transmission source bus master 1_1 from the access request 29 to the next stage, and returns the remaining allowable waiting time information to the specified bus master 1_1. The remaining allowable waiting time information 82 is output at 2_1. Further, the remaining allowable waiting time return unit 80 included in the bus 2_1 specifies the source bus master 1_1 from the access request 29 to the next stage, and returns the remaining allowable waiting time information 82 to the specified bus master 1_1.

  By such an operation, the remaining allowable waiting time return unit 80 included in each of the buses 2_1 to 2_3 returns the allowable waiting time information received by the bus slave 5 to the transmitting bus masters 1_1 to 1_4 as the remaining allowable waiting time information. Can do. The bus master 1_1 occupies the buses 2_1 to 2_3 until the remaining allowable waiting time information is returned from the bus slave 5 to the bus master 1_1. Therefore, the other bus masters 1_2 to 1_4 use the buses 2_1 to 2_3. I can't.

  The bus masters 1_1 to 1_4 that have received the remaining allowable waiting time information can improve the bus use efficiency by using the remaining waiting time information. For example, when the returned remaining waiting time is less than 0, the bus masters 1_1 to 1_4 reduce the allowable waiting time added to the access request from the next access request issuance, and obtain the bus use right with higher priority. Can be made. On the other hand, if the returned remaining waiting time remains sufficiently, the bus usage right can be given priority to other bus masters by setting a large allowable waiting time from the next access request issuance. Can be.

  As described above, in the bus system according to the present embodiment, the use of the bus is performed by returning the allowable waiting time information received by the bus slave 5 as the remaining allowable waiting time information to the source bus masters 1_1 to 1_4. Efficiency can be further improved.

  Note that the configuration in which the bus according to FIG. 2 described in the first embodiment is provided with the remaining allowable waiting time return unit 80 can achieve the same effects as the bus system according to the present embodiment.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

1-1, 1-2, 1-3, 1-4 Bus master 2, 3, 2-1, 2-2, 2-3 bus 5 Bus slave 8, 9 Arbitration unit 12, 13 Access request separation unit 14 Request control unit 15 Access request coupling unit 16, 17 Access request from the previous stage 21 and 23 Access request signals 22 and 24 Permissible waiting time information 25 Access request reception information 26 Selected access request signals 27 and 28 Updated allowed waiting time information 29 Access requests 45 and 48 to the next stage Permissible waiting time calculation unit 46, 49 Maximum priority determination unit 50 Counter 51 Access request signal selection unit 67 Count value 68, 69 Threshold 70, 71 Top priority signal 80 Remaining allowable waiting time return unit 81 Remaining allowable waiting time information 82, 83 from the next stage To the previous stage Remaining allowable waiting time information

Claims (18)

A bus system that controls access from a plurality of bus masters to at least one bus slave via a plurality of buses,
Each of the buses includes an arbitration unit that arbitrates a plurality of access requests input from the previous stage and outputs the access request selected by the arbitration to the next stage,
The arbitration unit updates the allowable waiting time information included in the access request output to the next stage by subtracting the time that the access request waited on the bus.
Bus system. The arbitration unit includes an access request separation unit provided corresponding to each of the input access requests,
The access request separator separates an access request signal included in the input access request and the allowable waiting time information;
The bus system according to claim 1. The arbitration unit further includes a request control unit,
The request control unit
Input the access request signal and the allowable waiting time information separated by the access request separation unit,
Arbitrating the access request signal, outputting the access request signal selected by the arbitration,
Updating the allowable waiting time information of the selected access request signal by subtracting the time that the access request signal waited on the bus;
The bus system according to claim 2. The mediation unit
An access request combining unit that combines the selected access request signal output from the request control unit and the updated allowable waiting time information;
The access request combining unit outputs an access request combining the selected access request signal and the updated allowable waiting time information as an access request output to the next stage.
The bus system according to claim 3. The mediation unit
A highest priority determination unit that determines whether to output the input access request with the highest priority based on the allowable waiting time information included in the input access request;
An access request signal selection unit that selects an access request output to the next stage based on a determination result of the highest priority determination unit;
The bus system according to any one of claims 1 to 4, further comprising: The highest priority determination unit determines that the input access request is output with the highest priority when a count value generated according to a clock signal exceeds a threshold value determined based on the allowable waiting time information.
The bus system according to claim 5.   The arbitration unit further includes an allowable waiting time calculation unit that updates the allowable waiting time information of the access request by subtracting the time that the access request waited on the bus from the allowable waiting time when the access request is input. The bus system according to any one of claims 1 to 6.   The said arbitration part is further provided with the remaining allowable waiting time return part which returns the said allowable waiting time information which the said bus slave received to the bus master of a transmission source as remaining allowable waiting time information. The described bus system.   The bus system according to claim 8, wherein the bus master sets the allowable waiting time using the remaining allowable waiting time information. An access control method for controlling access from a plurality of bus masters to at least one bus slave via a plurality of buses,
Each of the buses arbitrates a plurality of access requests input from the previous stage, and outputs the access request selected by the arbitration to the next stage.
Update the allowable waiting time information included in the access request output to the next stage by subtracting the time that the access request output to the next stage waits on the bus,
Access control method. Separating an access request signal included in each access request input to the bus and the allowable waiting time information;
The access control method according to claim 10. Arbitrate the separated access request signal, and output the access request signal selected by the arbitration,
Updating the allowable waiting time information of the selected access request signal by subtracting the time that the selected access request signal waited on the bus;
The access control method according to claim 11.   The access control method according to claim 12, wherein the selected access request signal and the updated allowable waiting time information are combined, and the combined access request is output as an access request output to the next stage. Determining whether to output the input access request with the highest priority based on the allowable waiting time information included in the access request input to the bus;
Selecting an access request to be output to the next stage based on the determination result;
The access control method according to any one of claims 10 to 13. Determining a threshold based on the allowable waiting time information;
Compare the count value generated according to the clock signal and the threshold,
When the count value exceeds the threshold, it is determined that the input access request is output with the highest priority.
The access control method according to claim 14.   16. The allowable waiting time information of the access request is updated by subtracting the time that the access request waited on the bus from the allowable waiting time at the time of inputting the access request. Access control method.   The access control method according to any one of claims 10 to 16, wherein the allowable waiting time information received by the bus slave is returned to the transmission source bus master as remaining allowable waiting time information.   The access control method according to claim 17, wherein the bus master sets the allowable waiting time using the remaining allowable waiting time information.

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