JPH04276845A - Bus arbitration circuit - Google Patents

Abstract

PURPOSE:To protect a particular DMA controller from occupying a bus for a long period to act, and to enable a CPU to obtain the right of occupancy of the bus for the CPU in a period of time shorter than that by the conventional one even when the CPU is set into an emergent state of using the bus urgently. CONSTITUTION:Both a first DMA controller 20 and a nth DMA controller 30 output a request signal for using a bus at a time, and when a bus adjusting section 60 gives priority to the first DMA controller 20 to operate, after a certain period of time passes, the nth DMA controller 30 outputs an interrupt signal. An interrupt control circuit 70 outputs an emergent interrupt signal to a CPU10. The CPU10, when receiving this signal, temporarily outputs a flag setting signal to a flag register 25 to mask a bus request signal 150, thereby causing the bus adjusting circuit 60 to give the right of using bus to the nth DMA controller 30.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration circuit, and in particular to a bus arbitration circuit, and in particular, data shared by a data processing device comprising one CPU, a plurality of DMA (direct memory access) control devices, and an internal storage device of the CPU. The present invention relates to a bus arbitration circuit that arbitrates the right to use a transmission bus.

0002

2. Description of the Related Art A bus arbitration circuit is provided in a data processing device comprising a CPU (central processing unit), a plurality of DMA control devices, an internal storage device of the CPU, and the like. A CPU that uses this bus for the bus shared by the CPU, multiple DMA control devices, and internal storage device described above.
If there is a request to use this bus simultaneously from the PU and multiple DMA control devices, that is, if contention for the bus occurs, the above-mentioned bus is installed in the data processing device to avoid contention for the bus. An arbitration circuit is provided, and the bus arbitration circuit adjusts the requests of the CPU and the plurality of DMA control devices to use the above-mentioned bus at the same time, based on predetermined bus usage priority. Competing D that has requested use of the bus
One of the MAs or the DMA and the CPU is selected and given the right to use the bus.

[0003] The above-mentioned DMA control device reads out data stored in the internal storage device of the CPU, and reads out the data stored in the internal storage device of the CPU.
When writing data to a host device of the PU, or when reading data stored in an external storage device or a host device other than the data processing device mentioned above and writing it to the internal storage device mentioned above, control of reading and writing of these data is performed as described above. This is a control device that performs control without using the CPU. moreover,
Generally, the above-mentioned data processing apparatus is provided with a plurality of DMA control apparatuses, and these DMA control apparatuses each have a specific external storage device or a host device of the above-mentioned data processing apparatus and an internal storage within the above-mentioned data processing apparatus. Controls the transfer of data to and from devices. Furthermore, these D
The MA control device performs the data transfer described above when receiving a data transfer request from the CPU described above.

0004

[Problems to be Solved by the Invention] The above-mentioned conventional bus arbitration circuit, when the right to use the above-mentioned bus is granted to a certain DMA control device, disables the DM that has been given the right to use the bus.
Until the A control device completes the data transfer, while the DMA control device is controlling the data transfer, the CPU or other DMA requests the bus arbitration circuit to use the bus. Even if a request is made, the use request is put on hold. For example, even if the CPU wants to use the bus in a hurry, it will not be able to use the bus until the operation of the DMA control device that has the right to use the bus is completed. This CP
U cannot use the bus, and the amount of data controlled by the DMA controller that has obtained the right to use the bus is so large that it takes a long time to control a series of data transfers. In some cases, other DMA control devices or the aforementioned CPU have to wait for a long time after issuing a request to use the bus.

[0005] An object of the present invention is to prevent the DMA control device that has obtained the right to use the bus from transferring data when a predetermined time elapses when the data transfer operation time by the DMA control device that has obtained the right to use the bus is long.
When a bus use request is sent from the A control unit or the CPU, the other DMA that issued the bus use request
Or, give the CPU the right to use the bus and use one specific DM.
Rather than concentrating the use of the above-mentioned bus only on the A control device for a long time, it also gives other DMA control devices an opportunity to use the bus, and also when the CPU issues the above-mentioned bus use request. An object of the present invention is to provide a bus arbitration circuit that can obtain the right to use a bus in a shorter time than conventional ones.

[0006]

[Means for Solving the Problems] A bus arbitration circuit according to the present invention has a CPU that operates according to a microprogram, and a bus arbitration circuit according to the present invention.
An internal storage device of the PU and a plurality of DMA control devices that control data input/output between the internal storage device and an external storage device or a host device of the CPU are connected via a bus, and the CPU and the DMA control device are connected via a bus. A bus arbitration circuit that grants the right to use the bus to the CPU and one of the plurality of DMA control devices at the same time based on a predetermined priority when a device uses the bus. A flag is set while a flag setting signal is input, and a bus use request signal requesting the use of the bus outputted from the corresponding DMA control device is masked. When the flag is not set, the masking means allows the bus use request signal from the corresponding DMA control device to pass through as is. When the bus use request signal is received at a predetermined priority, a bus use permission signal is sent that gives the right to use the bus to one of the DMA and the CPU that sent the bus use request signal. A bus arbitration unit that outputs an output, and an operation that uses the bus only while the bus use permission signal is given, and continuously outputs the use request signal while using the bus, and the bus arbitration unit said plurality of DMA control devices have means for outputting an interrupt signal when a predetermined time elapses after the use of said bus is suspended by said bus request signal and output of said bus use request signal is started; an interrupt control circuit that receives all of the interrupt signals and outputs an emergency interrupt signal when it receives at least one of the interrupt signals; and an interrupt control circuit other than the DMA control device that outputs the interrupt signal when it receives the emergency interrupt signal. means for outputting the flag setting signal for a predetermined period of time to the flag register provided corresponding to the DMA control device; and the CPU having means for outputting the flag setting signal to all flag registers for a predetermined period of time.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the bus arbitration circuit of the present invention.

As shown in FIG. 1, the bus arbitration circuit of this embodiment includes a CPU 10 and a first DMA control device 20 that operate according to a microprogram stored in advance.
and the n-th DMA control device 30 and the internal storage device 40.
via a bus 50. In the figure, DM
The A control device is the first DMA control device 20 and the nth DMA
Although only two controllers 30 are shown, in general any number of DMA controllers can be connected.

The first DMA control device 20 and the nth D
Each of the MA control devices 30 is a DMA controller that controls data transfer between a specific storage device of a host device (not shown) or a specific external storage device (not shown) and the internal storage device 40 via a bus 50. It is a control device.

The first DMA control device 20 and the nth DMA
For example, the address of the data to be read first among the data stored in the internal storage device 40, the data length of the data to be read, and the read data are stored in each control device 30 from the CPU 10 via the bus 50. When the start address of a series of data to be read out of the data stored in the external storage device mentioned above is specified, or the start address of a series of data to be read out of the data stored in the above-mentioned external storage device is specified. The data length of a series of data and the start address in the internal storage device 40 to which the read data is to be written are specified, and, for example, DMA activation signals 100 and 110 from the CPU 10 are sent to the first DMA control device and the first DMA control device, respectively. When applied to the n-th DMA control device, bus use request signals 150 and 160 requesting the use of the bus 50 are output from the first DMA control device 20 and the n-th DMA control device 30 to the bus arbitration unit 60, respectively. .

When the bus arbitration unit 60 receives bus use request signals for the bus 50 simultaneously from the CPU 10, the first DMA control device 20, and the n-th DMA control device 30, in what order? It is decided in advance whether to grant the right to use the bus 50. For example, the CPU 10 has the highest right to use the bus 50, the first DMA control device 20 has the second highest right to use the bus 50, and the nth DMA control device 30 has the second highest right to use the bus 50. If it is the lowest, the first DMA control device 20 as described above
When a bus use request signal is simultaneously output from the n-th DMA control device 30, the bus arbitration unit 60 transmits the bus use permission signal 155, which permits use of the bus 50, to the first DMA control device 30.
output to the control device 20, and the first DMA control device 2
0 is granted permission to use the bus 50.

When the first DMA control device 20 receives this bus use permission signal 155, it starts from the address previously specified by the CPU 10, for example, in the internal storage device 40 and has a data length specified in advance by the CPU 10. The read data is transferred via the bus 50 to a pre-specified external storage device (not shown) that is predetermined in correspondence with the first DMA control device 20. Control of writing after the address is performed without going through the CPU 10. In addition,
The address for starting writing to the external storage device is specified in advance to the first DMA control device 20 by the CPU 10, as described above.

In this way, while the bus use permission signal 155 is being outputted from the bus arbitration unit 60 and the first DMA control device 20 is transferring the above-mentioned data, the nth
The use of the bus 50 from the n-th DMA control device 30 is suspended by the arbitration unit 60, but this suspension continues for more than a preset time after the n-th DMA control device 30 sends out the bus use request signal 160. When the time has elapsed, the n-th DMA control device 30 outputs an interrupt signal 130 to the interrupt control circuit 70. When the interrupt signal 130 is input, the interrupt control circuit 70 outputs the emergency interrupt signal 170 to CP.
Output to U10.

Note that the first DMA control device 20 also
If the use of the bus 50 is suspended by the bus arbitration unit 60 after requesting a bus use request signal in the same way as the DMA control device 30 of
The interrupt control circuit 70 is set to output the interrupt signal 120. Also, when the interrupt signal 120 is applied, the interrupt control circuit 70 outputs the emergency interrupt signal 170 in the same way as when the interrupt signal 130 is applied. Output.

The CPU 10 monitors the state of data transfer being performed by the first DMA control device 20 via the bus 50, and when the above-mentioned emergency interrupt signal 170 is input, the bus arbitration section 60 Flag register 25 of flag registers 25 and 35 that are internally held corresponding to the No. 1 DMA control device 20 and the n-th DMA control device 30, respectively.
A flag setting signal synchronized with data transfer via the bus 50 is output to the bus 50. It is assumed that the CPU 10 sets the timing for transmitting this flag setting signal at an appropriate time. Flag register 25 in bus arbitration unit 60
The flag is set while the flag setting signal is received. The bus use request signal 150 output from the first DMA control device 20 to the bus arbitration unit 60 is controlled by this flag register 25, and when the flag register 25 is set, the bus use request signal 150 is output to the bus arbitration unit 60. It is masked at the input end to block transmission of the bus use request signal 150 to the inside of the bus arbitration unit 60. In such a state, only the bus use request signal 160 output from the n-th DMA control device 30 is input to the bus arbitration unit 60, so the bus arbitration unit 60 has until now been
Bus use permission signal 155 that was output to the A control device 20
and outputs a bus use permission signal 165 to the n-th DMA control device 30. Therefore, the first DM
The A control device 20 stops its operation, and the n-th DMA control device 30 starts data transfer control using the bus 50. However, since the flag setting signal that the CPU 10 outputs to the flag register 25 of the bus arbitration unit 60 is disconnected after the predetermined period of time described above has elapsed, the setting of the flag in the flag register 25 is canceled and the first DMA control device 10 Bus use request signal 150 output from
Since the masking effect on the bus arbitration unit 60 is canceled,
Since this bus use request signal 150 is input into the inside of the bus 50, the bus arbitration unit 60 again selects the first
A bus use permission signal 15 is sent to the DMA control device 20 of
5, and at the same time, the output of the bus use permission signal 165 that was being output to the n-th DMA control device 30 is stopped.

Similarly, only the n-th DMA control device 30 first outputs the bus use request signal 160 and the bus arbitration unit 60
sends the bus use permission signal 165 to the n-th DMA control device 30.
When the first DMA control device 20 is in a state of outputting
outputs the bus use request signal 155 to the bus arbitration section 60, the request is put on hold by the bus arbitration section 60, and when a preset time has elapsed, the first DMA control device 20
An interrupt signal 120 is output from. This interrupt signal 120
When the interrupt signal 130 is output, the interrupt control circuit 70 performs the same operation as when the interrupt signal 130 is input, and as a result, the CPU 1
From 0 onwards, a flag setting signal is output to the flag register 35 in the bus arbitration section 60. CPU in flag register 35
When the flag setting signal is output from 10, the flag is set and the bus use request signal 160 inputted from the n-th DMA control device 30 to the bus arbitration unit 60 is masked at its input terminal, and this bus use request signal is 160 is masked from being transmitted to the inside of the bus arbitration unit 60. Therefore, in such a state, while the flag setting signal is being output from the CPU 10 to the flag register 35, the right to use the bus 50 is transferred from the n-th DMA control device 30 to the first The process will now move on to the DMA control device 20.

Furthermore, bus use request signals 150 and 16 are sent from the first DMA control device 20 and the n-th DMA control device 30.
0 is output to the bus arbitration unit 60, and as described above, when the bus 50 is used alternately by these two DMA control devices, and when the CPU 10 urgently uses the bus 50, the CPU 10 outputs a bus use request signal 140 to the bus arbitration unit 60 from the flag register 2.
If a flag setting signal is outputted for a preset time to DMA controllers 5 and 35, the bus use request signals 150 and 160 outputted from the two DMA control devices mentioned above are simultaneously masked. Since the bus arbitration device 60 outputs a bus use permission signal to the bus 50 and the CPU 10 is given the right to use the bus 50, the CPU 10
The bus 50 can be used in a short time after the bus 50 is outputted the bus 50 use request signal 140.

[0019]

As explained above, the bus arbitration circuit of the present invention prevents a specific DMA control device from monopolizing the bus for a long time, and
The flag setting signal can also be used to give the A control device an opportunity to permit use of the bus, and if the CPU urgently wants to use the bus when these DMA control devices are using the bus. By outputting from the CPU, the CPU
This has the effect that U can use the bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a bus arbitration circuit of the present invention.

[Explanation of symbols]

10 CPU 20 First DMA control device 25 Flag register 30 n-th DMA control device 35 Flag register 40 Internal storage device 50 bus 60 Bus arbitration department 70 Interrupt control circuit

Claims (1)

[Claims] 1. A CPU that operates according to a microprogram, an internal storage device of the CPU, and a plurality of DMA control devices that control data input/output between the internal storage device and an external storage device or a host device of the CPU. are connected via a bus, and when the CPU and the DMA control device use the bus, the CPU and the plurality of
A bus arbitration circuit that grants the right to use the bus to one of the MA control devices is provided corresponding to each of the plurality of DMA control devices, and as long as a flag setting signal is input, a flag is set and the above-mentioned response is set. The bus use request signal output from the corresponding DMA control device that requests the use of the bus is masked, and when the flag is not set, the bus use request signal from the corresponding DMA control device is passed through as is. and upon receiving the bus use request signal from two or more of the plurality of DMA control devices and the CPU at the same time via the masking means, the DMA transmits the bus use request signal according to a predetermined priority order. and a bus arbitration unit that outputs a bus use permission signal that grants one of the CPUs the right to use the bus, and an operation that uses the bus only while the bus use permission signal is provided. Yes, while the bus is being used, the use request signal is continuously output, and the use of the bus is suspended by the bus arbitration unit, and a predetermined time has elapsed since output of the bus use request signal was started. Then, the plurality of DMA control devices have means for outputting an interrupt signal, and an interrupt control circuit receives all of the interrupt signals and outputs an emergency interrupt signal when at least one of the interrupt signals is received. and upon receiving the emergency interrupt signal, the D other than the DMA control device that outputs the interrupt signal.
Means for outputting the flag setting signal for a predetermined period of time to the flag register provided corresponding to the MA control device; and all of the above when it becomes necessary for the CPU to use the bus preferentially. and a means for outputting the flag setting signal to a flag register of the CPU for a predetermined period of time.